This does not include all instructions for S- and M-mode from the
priviledged spec, but these are the common ones that we will definitely
need (and use ourselves)
Actually, this is RV64IMZifencei and RV32IMZifencei:
- As per RISC-V, RV64I of course includes RV32I
- The M extension is not separable in a good way since it just adds more
arithmetic instructions that are represented in a common class with
other I instructions.
- Zifencei is just one instruction (FENCE.I) that doesn't need its own
file.
These structs just handle decoding the raw bit format, including details
like sign extending, but not interpreting these bits or translating them
to higher level constructs.
The next series of commits will add full RV64GC decoding, but since this
is a lot of code, it is split up into semi-logical chunks which each
contain plenty of dead code initially.
This first commit adds the RISC-V register definitions and enums
necessary for RV64GC; that is, no vector registers.
We can easily detect the architecture from a given ELF file or just use
the native architecture. Importantly, this allows every implemented
target architecture to be disassembled on every host architecture.
At the moment, there's only two generic methods used on Instruction, so
generalizing those allows handling Instructions generically by many
tools. This commit updates the length() interface to use size_t, but not
the serialization interface to use String since that requires a lot more
changes. The serialization interface is however cleaned up and
genericised.
Note that the implementations still construct a non-heap-allocated
Instruction with their creation function, since that yields no
performance degradation for users of arch-specific Instruction like UE.
InstructionStream, SymbolProvider and Disassembler are already generic
interfaces, so we can separate those from the x86-specific code. The
x86-specific code is moved to a new x86 subdirectory, which will be
accompanied by other architecture-specific directories soon.
Before making this library generic for our different architectures,
let's rename it to indicate this general purpose. The namespace is
changed to Disassembly::X86 since all code is still x86-specific at the
moment, and this namespace will remain in existence to host x86-specific
parts in addition to new sub-namespaces like Disassembly::RISCV and
Disassembly::Aarch64.
Linus Groh