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https://github.com/Vita3K/unicorn.git
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first atttempt at SPARC64 fixes, no longer SEGV's, set CPU model to: Sun UltraSparc IV
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parent
fe807952d0
commit
893e6abcbd
@ -33,19 +33,23 @@
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static void sun4u_init(struct uc_struct *uc, MachineState *machine)
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{
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const char *cpu_model = machine->cpu_model;
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SPARCCPU *cpu;
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if (cpu_model == NULL)
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cpu_model = "sun4uv";
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cpu_model = "Sun UltraSparc IV";
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if (cpu_sparc_init(uc, cpu_model) == NULL) {
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cpu = cpu_sparc_init(uc, cpu_model);
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if (cpu == NULL) {
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fprintf(stderr, "Unable to find Sparc CPU definition\n");
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exit(1);
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}
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cpu_sparc_set_id(&cpu->env, 0);
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}
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void sun4u_machine_init(struct uc_struct *uc)
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{
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QEMUMachine sun4u_machine = {
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static QEMUMachine sun4u_machine = {
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.name = "sun4u",
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.init = sun4u_init,
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.max_cpus = 1, // XXX for now
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@ -6,6 +6,7 @@
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#include "sysemu/cpus.h"
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#include "unicorn.h"
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#include "cpu.h"
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#include "unicorn_common.h"
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#define READ_QWORD(x) ((uint64)x)
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@ -15,6 +16,22 @@
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#define READ_BYTE_L(x) (x & 0xff)
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static bool sparc_stop_interrupt(int intno)
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{
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switch(intno) {
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default:
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return false;
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case TT_ILL_INSN:
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return true;
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}
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}
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static void sparc_set_pc(struct uc_struct *uc, uint64_t address)
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{
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((CPUSPARCState *)uc->current_cpu->env_ptr)->pc = address;
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((CPUSPARCState *)uc->current_cpu->env_ptr)->npc = address + 4;
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}
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void sparc_reg_reset(struct uc_struct *uc)
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{
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CPUArchState *env = first_cpu->env_ptr;
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@ -75,7 +92,7 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
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default: break;
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case UC_SPARC_REG_PC:
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SPARC_CPU(uc, mycpu)->env.pc = *(uint64_t *)value;
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SPARC_CPU(uc, mycpu)->env.npc = *(uint64_t *)value + 8;
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SPARC_CPU(uc, mycpu)->env.npc = *(uint64_t *)value + 4;
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break;
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}
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}
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@ -93,4 +110,7 @@ void sparc64_uc_init(struct uc_struct* uc)
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uc->reg_read = sparc_reg_read;
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uc->reg_write = sparc_reg_write;
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uc->reg_reset = sparc_reg_reset;
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uc->set_pc = sparc_set_pc;
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uc->stop_interrupt = sparc_stop_interrupt;
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uc_common_init(uc);
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}
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@ -3,9 +3,22 @@
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from unicorn import *
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from unicorn.sparc_const import *
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PAGE_SIZE = 1 * 1024 * 1024
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uc = Uc(UC_ARCH_SPARC, UC_MODE_64)
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uc.reg_write(UC_SPARC_REG_SP, 100)
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uc.reg_write(UC_SPARC_REG_FP, 100)
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print 'writing sp = 100, fp = 100'
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print 'writing sp = 100, %%i0 = 2000'
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# 0: b0 06 20 01 inc %i0
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# 4: b2 06 60 01 inc %i1
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CODE = "\xb0\x06\x20\x01" \
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"\xb2\x06\x60\x01"
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uc.mem_map(0, PAGE_SIZE)
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uc.mem_write(0, CODE)
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uc.emu_start(0, len(CODE), 0, 2)
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print 'sp =', uc.reg_read(UC_SPARC_REG_SP)
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print 'fp =', uc.reg_read(UC_SPARC_REG_FP)
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print 'i0 =', uc.reg_read(UC_SPARC_REG_I0)
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print 'i1 =', uc.reg_read(UC_SPARC_REG_I1)
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