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more cleanup in qemu/include/hw/

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This commit is contained in:
Nguyen Anh Quynh 2017-01-19 15:20:06 +08:00
parent 287e047fdb
commit 8a5b12c6f9
9 changed files with 0 additions and 207 deletions
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2
qemu/header_gen.py
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@ -3075,9 +3075,7 @@ mips_symbols = (
'cpu_mips_store_compare',
'cpu_mips_start_count',
'cpu_mips_stop_count',
'cpu_mips_clock_init',
'mips_machine_init',
'cpu_mips_irq_init_cpu',
'cpu_mips_kseg0_to_phys',
'cpu_mips_phys_to_kseg0',
'cpu_mips_kvm_um_phys_to_kseg0',

35
qemu/hw/mips/cputimer.c
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@ -129,38 +129,3 @@ void cpu_mips_stop_count(CPUMIPSState *env)
env->CP0_Count += (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
TIMER_FREQ, get_ticks_per_sec());
}
#if 0
static void mips_timer_cb (void *opaque)
{
CPUMIPSState *env;
env = opaque;
#if 0
qemu_log("%s\n", __func__);
#endif
if (env->CP0_Cause & (1 << CP0Ca_DC))
return;
/* ??? This callback should occur when the counter is exactly equal to
the comparator value. Offset the count by one to avoid immediately
retriggering the callback before any virtual time has passed. */
env->CP0_Count++;
cpu_mips_timer_expire(env);
env->CP0_Count--;
}
#endif
void cpu_mips_clock_init (CPUMIPSState *env)
{
#if 0
/*
* If we're in KVM mode, don't create the periodic timer, that is handled in
* kernel.
*/
if (!kvm_enabled()) {
env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &mips_timer_cb, env);
}
#endif
}

30
qemu/include/hw/m68k/mcf.h
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@ -1,30 +0,0 @@
#ifndef HW_MCF_H
#define HW_MCF_H
/* Motorola ColdFire device prototypes. */
struct MemoryRegion;
/* mcf_uart.c */
uint64_t mcf_uart_read(void *opaque, hwaddr addr,
unsigned size);
void mcf_uart_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size);
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
void mcf_uart_mm_init(struct MemoryRegion *sysmem,
hwaddr base,
qemu_irq irq, CharDriverState *chr);
/* mcf_intc.c */
qemu_irq *mcf_intc_init(struct MemoryRegion *sysmem,
hwaddr base,
M68kCPU *cpu);
/* mcf_fec.c */
void mcf_fec_init(struct MemoryRegion *sysmem, NICInfo *nd,
hwaddr base, qemu_irq *irq);
/* mcf5206.c */
qemu_irq *mcf5206_init(struct MemoryRegion *sysmem,
uint32_t base, M68kCPU *cpu);
#endif

7
qemu/include/hw/mips/cpudevs.h
View File

@ -7,11 +7,4 @@ uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr);
uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr);
uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr);
/* mips_int.c */
void cpu_mips_irq_init_cpu(CPUMIPSState *env);
/* mips_timer.c */
void cpu_mips_clock_init(CPUMIPSState *);
#endif

125
qemu/include/hw/sparc/grlib.h
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@ -1,125 +0,0 @@
/*
* QEMU GRLIB Components
*
* Copyright (c) 2010-2011 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef _GRLIB_H_
#define _GRLIB_H_
#include "hw/qdev.h"
/* Emulation of GrLib device is base on the GRLIB IP Core User's Manual:
* http://www.gaisler.com/products/grlib/grip.pdf
*/
/* IRQMP */
typedef void (*set_pil_in_fn) (void *opaque, uint32_t pil_in);
void grlib_irqmp_set_irq(void *opaque, int irq, int level);
void grlib_irqmp_ack(DeviceState *dev, int intno);
static inline
DeviceState *grlib_irqmp_create(hwaddr base,
CPUSPARCState *env,
qemu_irq **cpu_irqs,
uint32_t nr_irqs,
set_pil_in_fn set_pil_in)
{
DeviceState *dev;
assert(cpu_irqs != NULL);
dev = qdev_create(NULL, "grlib,irqmp");
qdev_prop_set_ptr(dev, "set_pil_in", set_pil_in);
qdev_prop_set_ptr(dev, "set_pil_in_opaque", env);
if (qdev_init(dev)) {
return NULL;
}
env->irq_manager = dev;
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
*cpu_irqs = qemu_allocate_irqs(grlib_irqmp_set_irq,
dev,
nr_irqs);
return dev;
}
/* GPTimer */
static inline
DeviceState *grlib_gptimer_create(hwaddr base,
uint32_t nr_timers,
uint32_t freq,
qemu_irq *cpu_irqs,
int base_irq)
{
DeviceState *dev;
int i;
dev = qdev_create(NULL, "grlib,gptimer");
qdev_prop_set_uint32(dev, "nr-timers", nr_timers);
qdev_prop_set_uint32(dev, "frequency", freq);
qdev_prop_set_uint32(dev, "irq-line", base_irq);
if (qdev_init(dev)) {
return NULL;
}
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
for (i = 0; i < nr_timers; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, cpu_irqs[base_irq + i]);
}
return dev;
}
/* APB UART */
static inline
DeviceState *grlib_apbuart_create(hwaddr base,
CharDriverState *serial,
qemu_irq irq)
{
DeviceState *dev;
dev = qdev_create(NULL, "grlib,apbuart");
qdev_prop_set_chr(dev, "chrdev", serial);
if (qdev_init(dev)) {
return NULL;
}
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
return dev;
}
#endif /* ! _GRLIB_H_ */

2
qemu/mips.h
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@ -3066,9 +3066,7 @@
#define cpu_mips_store_compare cpu_mips_store_compare_mips
#define cpu_mips_start_count cpu_mips_start_count_mips
#define cpu_mips_stop_count cpu_mips_stop_count_mips
#define cpu_mips_clock_init cpu_mips_clock_init_mips
#define mips_machine_init mips_machine_init_mips
#define cpu_mips_irq_init_cpu cpu_mips_irq_init_cpu_mips
#define cpu_mips_kseg0_to_phys cpu_mips_kseg0_to_phys_mips
#define cpu_mips_phys_to_kseg0 cpu_mips_phys_to_kseg0_mips
#define cpu_mips_kvm_um_phys_to_kseg0 cpu_mips_kvm_um_phys_to_kseg0_mips

2
qemu/mips64.h
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@ -3066,9 +3066,7 @@
#define cpu_mips_store_compare cpu_mips_store_compare_mips64
#define cpu_mips_start_count cpu_mips_start_count_mips64
#define cpu_mips_stop_count cpu_mips_stop_count_mips64
#define cpu_mips_clock_init cpu_mips_clock_init_mips64
#define mips_machine_init mips_machine_init_mips64
#define cpu_mips_irq_init_cpu cpu_mips_irq_init_cpu_mips64
#define cpu_mips_kseg0_to_phys cpu_mips_kseg0_to_phys_mips64
#define cpu_mips_phys_to_kseg0 cpu_mips_phys_to_kseg0_mips64
#define cpu_mips_kvm_um_phys_to_kseg0 cpu_mips_kvm_um_phys_to_kseg0_mips64

2
qemu/mips64el.h
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@ -3066,9 +3066,7 @@
#define cpu_mips_store_compare cpu_mips_store_compare_mips64el
#define cpu_mips_start_count cpu_mips_start_count_mips64el
#define cpu_mips_stop_count cpu_mips_stop_count_mips64el
#define cpu_mips_clock_init cpu_mips_clock_init_mips64el
#define mips_machine_init mips_machine_init_mips64el
#define cpu_mips_irq_init_cpu cpu_mips_irq_init_cpu_mips64el
#define cpu_mips_kseg0_to_phys cpu_mips_kseg0_to_phys_mips64el
#define cpu_mips_phys_to_kseg0 cpu_mips_phys_to_kseg0_mips64el
#define cpu_mips_kvm_um_phys_to_kseg0 cpu_mips_kvm_um_phys_to_kseg0_mips64el

2
qemu/mipsel.h
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@ -3066,9 +3066,7 @@
#define cpu_mips_store_compare cpu_mips_store_compare_mipsel
#define cpu_mips_start_count cpu_mips_start_count_mipsel
#define cpu_mips_stop_count cpu_mips_stop_count_mipsel
#define cpu_mips_clock_init cpu_mips_clock_init_mipsel
#define mips_machine_init mips_machine_init_mipsel
#define cpu_mips_irq_init_cpu cpu_mips_irq_init_cpu_mipsel
#define cpu_mips_kseg0_to_phys cpu_mips_kseg0_to_phys_mipsel
#define cpu_mips_phys_to_kseg0 cpu_mips_phys_to_kseg0_mipsel
#define cpu_mips_kvm_um_phys_to_kseg0 cpu_mips_kvm_um_phys_to_kseg0_mipsel