From 99097cab4c39fb3fc50eea8f0006954f62a149b2 Mon Sep 17 00:00:00 2001 From: Charles Ferguson Date: Thu, 2 Jan 2020 01:42:01 +0000 Subject: [PATCH] Add implementation of access to the ARM SPSR register. (#1178) The SPSR register is named within the Unicorn headers, but the code to access it is absent. This means that it will always read as 0 and ignore writes. This makes it harder to work with changes in processor mode, as the usual way to return from a CPU exception is a `MOVS pc, lr` for undefined instructions or `SUBS pc, lr, #4` for most other aborts - which implicitly restores the CPSR from SPSR. This change adds the access to the SPSR so that it can be read and written as the caller might expect. --- qemu/target-arm/unicorn_arm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qemu/target-arm/unicorn_arm.c b/qemu/target-arm/unicorn_arm.c index 8e1fa115..0e1b1828 100644 --- a/qemu/target-arm/unicorn_arm.c +++ b/qemu/target-arm/unicorn_arm.c @@ -74,6 +74,9 @@ int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun case UC_ARM_REG_CPSR: *(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env); break; + case UC_ARM_REG_SPSR: + *(int32_t *)value = ARM_CPU(uc, mycpu)->env.spsr; + break; //case UC_ARM_REG_SP: case UC_ARM_REG_R13: *(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[13]; @@ -134,6 +137,9 @@ int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, i case UC_ARM_REG_CPSR: cpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value, ~0); break; + case UC_ARM_REG_SPSR: + ARM_CPU(uc, mycpu)->env.spsr = *(uint32_t *)value; + break; //case UC_ARM_REG_SP: case UC_ARM_REG_R13: ARM_CPU(uc, mycpu)->env.regs[13] = *(uint32_t *)value;