Shaders: every per-mip image binding counted; the phi pass in a fixed order

Info::AddBindings counted one binding per image, while the SPIR-V emitter and the pipeline layout
give an image with a binding per mip level (DynamicIndex) one per level: the next stage's
bindings could start inside it and read the wrong resources. Pipeline key version 7, so saved
pipelines are rebuilt once.

The phi simplification pass queued SCC groups in the hash table's order, which depends on block
addresses, so the same shader could compile to different SPIR-V from one run to the next. They
are queued in the SCCs' order now (upstream shadPS4 #5364). Both from Awaken's LanternEngine
(0.9.37 beta 5 and 7).

Co-Authored-By: Awaken <[email protected]>

gpu/shadps4/shader_recompiler/info.h

@@ -255,7 +255,14 @@ struct Info : InfoPersistent {
 
     void AddBindings(Backend::Bindings& bnd) const {
         bnd.buffer += buffers.size();
-        bnd.unified += buffers.size() + images.size() + samplers.size();
+        // bbport: an image with a binding per mip level (MipStorageFallbackMode::DynamicIndex)
+        // takes as many as the SPIR-V emitter and the pipeline layout give it, not one, or the
+        // next stage's bindings start inside it. From Awaken's LanternEngine.
+        u32 image_bindings = 0;
+        for (const auto& image : images) {
+            image_bindings += image.NumBindings(*this);
+        }
+        bnd.unified += buffers.size() + image_bindings + samplers.size();
         bnd.user_data += ud_mask.NumRegs();
     }
 

gpu/shadps4/shader_recompiler/ir/passes/phi_simplification_pass.cpp

@@ -18,6 +18,7 @@
 
 #include <limits>
 #include <unordered_map>
+#include <utility>
 #include <vector>
 #include <boost/container/small_vector.hpp>
 
@@ -352,11 +353,13 @@ static void DeduplicateSccs(std::vector<PhiScc>& sccs) {
 
     std::vector<SccGroup*> worklist;
     worklist.reserve(scc_groups.size());
-    for (auto it = scc_groups.begin(); it != scc_groups.end(); ++it) {
-        auto& group = it->second;
-        if (group.sccs.size() > 1) {
+    // bbport: in the SCCs' order, not the hash table's: the structure hashes include block
+    // addresses, so the table's order changed from run to run and so did the SPIR-V (upstream
+    // shadPS4 #5364, via Awaken's LanternEngine).
+    for (const auto& scc : sccs) {
+        auto& group = scc_groups.at(scc.hash);
+        if (group.sccs.size() > 1 && !std::exchange(group.queued, true)) {
             worklist.push_back(&group);
-            group.queued = true;
         }
     }
 

gpu/shadps4/video_core/renderer_vulkan/vk_pipeline_serialization.cpp

@@ -18,7 +18,8 @@ static constexpr u32 ShaderBinaryVersion = 9u; // layer page-table pairs / guard
 static constexpr u32 ShaderMetaVersion = 7u; // bbport: ImageResource::needs_native
 // bbport 6: stages no longer paired with a vertex shader built for another binding start
 // (StageSpecialization::operator==): the pipelines saved with such pairs are rebuilt.
-static constexpr u32 PipelineKeyVersion = 6u; // bbport: Info layout (ImageResource::needs_native)
+// bbport 7: images with a binding per mip level count all of them (Info::AddBindings).
+static constexpr u32 PipelineKeyVersion = 7u; // bbport: Info layout (ImageResource::needs_native)
 } // namespace Serialization
 
 namespace Vulkan {