مصطفي محمود كمال الدينandRot127 7f5f5fe6e9 RISC-V: Revamp flags to allow fine grained control over aliasing (#3008) ...

This commit adds more flags to control the asm text and detail output.
RISC-V has instructions which have alias or compressed representations.

The new flags now allow to choose which asm text and which details Capstone should decode.
Please see the documentation for details.

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Co-authored-by: Rot127 <[email protected]>

2026-08-30 12:01:34 +00:00

..

test_all.py

RISC-V: add reg_access and test its usages in C and Python (#2895)

2026-04-17 17:40:16 +00:00

test_compatibility_layer.py

RISC-V: Add v5 compatibility behaviour for CS_MODE_RISCVC/RISCV_C (#2996)

2026-07-18 16:58:01 +00:00

test_customized_mnem.py

Python binding: (#2874)

2026-03-02 19:11:38 +00:00

test_iter.py

Python binding: (#2874)

2026-03-02 19:11:38 +00:00

test_lite.py

Python binding: (#2874)

2026-03-02 19:11:38 +00:00

test_riscv_reg_access.py

RISC-V: Revamp flags to allow fine grained control over aliasing (#3008)

2026-08-30 12:01:34 +00:00

test_riscv_sysreg.py

Fix sysreg registers in RISC-V and modify the header patcher to not crash if a header doesn't include all tags of a generated .inc file (#2894)

2026-04-15 09:25:46 +00:00

test_skipdata.py

Python binding: (#2874)

2026-03-02 19:11:38 +00:00