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https://github.com/capstone-engine/capstone.git
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b8fcf27b22
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h * Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction * Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h * Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter * Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h * Backport it from: https://github.com/porto703/capstone/commit/0db412ce3bed9d963caf598a2cb7dc76b41a5a2b * All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly. * Add refactored cs.c for RISCV * Testing all I instructions in test_riscv.c * Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture * Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c * fixed bug related to incorrect initialization of memory after malloc * fix compile bug * Fix compile errors. * move riscv.h to include/capstone * fix indentation issues * fix coding style issues * Fix indentation issues * fix coding style * Move variable declaration to the top of the block * Fix coding indentation * Move some stuff into RISCVMappingInsn.inc * Fix code sytle * remove cs_mode support for RISCV * update asmwriter-inc to LLVM upstream * update the .inc files to riscv upstream * update riscv disassembler function for suport 16bit instructions * update printer & tablegen inc files which have fixed arguments mismatch * update headers and mapping source * add riscv architecture specific test code * fix all RISCV tons of compiler errors * pass final tests * add riscv tablegen patchs * merge with upstream/next * fix cstool missing riscv file * fix root Makefile * add new TableGen patchs for riscv * fix cmakefile.txt of missing one riscv file * fix declaration conflict * fix incompatible declaration type * change riscvc from arch to mode * fix test_riscv warnning * fix code style and add riscv part of test_basic * add RISCV64 mode * add suite for riscv * crack fuzz test * fix getfeaturebits test add riscvc * fix test missing const qualifier warnning * fix testcase type mismatch * fix return value missing * change getfeaturebits test * add test cs files * using a winder type contain the decode string * fix a copy typo * remove useless mode for riscv * change cs file blank type * add repo for update_riscv & fix cstool missing riscv mode * fix typo * add riscv for cstool useage * add TableGen patch for riscv asmwriter * clean ctags file * remove black comment line * fix fuzz related something * fix missing RISCV string of fuzz * update readme, etc.. * add riscv *.s.cs file * add riscv *.s.cs file & clear ctags * clear useless array declarations at capstone_test * update to 5e4069f * update readme change name more formal * change position of riscv after bpf and modify copyright more uniform * clear useless ctags file * change blank with tab in riscv.h * add riscv python bindings * add riscv in __init__.py * fix riscv define value for python binding * fix test_riscv.py typo * add missing riscvc in __init__.py of python bindings * fix alias-insn printer bug, remove useless newline * change inst print delimter from tab to bankspace for travis * add riscv tablegen patch * fix inst output more consistency * add TableGen patch which fix inst output formal * crack the effective address output for detail and change register print function * fix not detail crash bug * change item declaration position at cs_riscv * update riscv.py * change function name more meaningfull * update python binding makefile * fix register enum sequence according to riscvgenreginfo.inc * test function name * add enum s0/fp in riscv.h & update riscv_const.py * add register name enum
83 lines
2.1 KiB
Makefile
83 lines
2.1 KiB
Makefile
PYTHON2 = python
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PYTHON3 = python3
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.PHONY: gen_const install install3 install_cython sdist sdist3 bdist bdist3 clean check
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gen_const:
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cd .. && $(PYTHON2) const_generator.py python
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install:
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rm -rf src/
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if test -n "${DESTDIR}"; then \
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$(PYTHON2) setup.py build install --root="${DESTDIR}"; \
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else \
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$(PYTHON2) setup.py build install; \
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fi
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install3:
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rm -rf src/
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if test -n "${DESTDIR}"; then \
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$(PYTHON3) setup.py build install --root="${DESTDIR}"; \
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else \
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$(PYTHON3) setup.py build install; \
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fi
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# NOTE: Newer cython can be installed by: sudo pip install --upgrade cython
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install_cython:
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rm -rf src/
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if test -n "${DESTDIR}"; then \
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$(PYTHON2) setup_cython.py build install --root="${DESTDIR}"; \
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else \
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$(PYTHON2) setup_cython.py build install; \
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fi
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install3_cython:
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rm -rf src/
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if test -n "${DESTDIR}"; then \
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$(PYTHON3) setup_cython.py build install --root="${DESTDIR}"; \
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else \
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$(PYTHON3) setup_cython.py build install; \
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fi
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# build & upload PyPi package with source code of the core
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sdist:
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rm -rf src/ dist/
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$(PYTHON2) setup.py sdist register upload
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# build & upload PyPi package with source code of the core
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sdist3:
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rm -rf src/ dist/
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$(PYTHON3) setup.py sdist register upload
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# build & upload PyPi package with prebuilt core
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bdist:
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rm -rf src/ dist/
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$(PYTHON2) setup.py bdist_wheel register upload
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# build & upload PyPi package with prebuilt core
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bdist3:
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rm -rf src/ dist/
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$(PYTHON3) setup.py bdist_wheel register upload
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clean:
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rm -rf build/ src/ dist/ *.egg-info
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rm -rf capstone/lib capstone/include pyx/lib pyx/include
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rm -f pyx/*.c pyx/__init__.py
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for f in capstone/*.py; do rm -f pyx/$$(basename $$f)x; done
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rm -f MANIFEST
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rm -f *.pyc capstone/*.pyc
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TESTS = test_basic.py test_detail.py test_arm.py test_arm64.py test_m68k.py test_mips.py
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TESTS += test_ppc.py test_sparc.py test_systemz.py test_x86.py test_xcore.py test_tms320c64x.py
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TESTS += test_m680x.py test_skipdata.py test_mos65xx.py test_bpf.py test_riscv.py
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TESTS += test_evm.py
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check:
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@for t in $(TESTS); do \
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echo Check $$t ... ; \
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./$$t > /dev/null; \
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if [ $$? -eq 0 ]; then echo OK; else echo FAILED; exit 1; fi \
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done
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