mirror of
https://github.com/darlinghq/darling-JavaScriptCore.git
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1125 lines
35 KiB
C++
1125 lines
35 KiB
C++
/*
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* Copyright (C) 2009-2017 Apple Inc. All rights reserved.
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* Copyright (C) 2009 University of Szeged
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* All rights reserved.
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* Copyright (C) 2010 MIPS Technologies, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY MIPS TECHNOLOGIES, INC. ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MIPS TECHNOLOGIES, INC. OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#pragma once
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#if ENABLE(ASSEMBLER) && CPU(MIPS)
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#include "AssemblerBuffer.h"
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#include "JITCompilationEffort.h"
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#include "MIPSRegisters.h"
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#include <limits.h>
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#include <wtf/Assertions.h>
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#include <wtf/SegmentedVector.h>
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namespace JSC {
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typedef uint32_t MIPSWord;
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namespace RegisterNames {
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typedef enum : int8_t {
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#define REGISTER_ID(id, name, r, cs) id,
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FOR_EACH_GP_REGISTER(REGISTER_ID)
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#undef REGISTER_ID
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#define REGISTER_ALIAS(id, alias) id = alias,
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FOR_EACH_REGISTER_ALIAS(REGISTER_ALIAS)
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#undef REGISTER_ALIAS
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InvalidGPRReg = -1,
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} RegisterID;
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typedef enum : int8_t {
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#define REGISTER_ID(id, name, idx) id = idx,
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FOR_EACH_SP_REGISTER(REGISTER_ID)
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#undef REGISTER_ID
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} SPRegisterID;
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typedef enum : int8_t {
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#define REGISTER_ID(id, name, r, cs) id,
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FOR_EACH_FP_REGISTER(REGISTER_ID)
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#undef REGISTER_ID
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InvalidFPRReg = -1,
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} FPRegisterID;
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} // namespace MIPSRegisters
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class MIPSAssembler {
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public:
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typedef MIPSRegisters::RegisterID RegisterID;
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typedef MIPSRegisters::SPRegisterID SPRegisterID;
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typedef MIPSRegisters::FPRegisterID FPRegisterID;
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typedef SegmentedVector<AssemblerLabel, 64> Jumps;
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static constexpr RegisterID firstRegister() { return MIPSRegisters::r0; }
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static constexpr RegisterID lastRegister() { return MIPSRegisters::r31; }
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static constexpr unsigned numberOfRegisters() { return lastRegister() - firstRegister() + 1; }
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static constexpr SPRegisterID firstSPRegister() { return MIPSRegisters::fir; }
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static constexpr SPRegisterID lastSPRegister() { return MIPSRegisters::pc; }
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static constexpr unsigned numberOfSPRegisters() { return lastSPRegister() - firstSPRegister() + 1; }
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static constexpr FPRegisterID firstFPRegister() { return MIPSRegisters::f0; }
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static constexpr FPRegisterID lastFPRegister() { return MIPSRegisters::f31; }
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static constexpr unsigned numberOfFPRegisters() { return lastFPRegister() - firstFPRegister() + 1; }
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static const char* gprName(RegisterID id)
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{
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ASSERT(id >= firstRegister() && id <= lastRegister());
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static const char* const nameForRegister[numberOfRegisters()] = {
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#define REGISTER_NAME(id, name, r, c) name,
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FOR_EACH_GP_REGISTER(REGISTER_NAME)
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#undef REGISTER_NAME
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};
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return nameForRegister[id];
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}
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static const char* sprName(SPRegisterID id)
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{
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ASSERT(id >= firstSPRegister() && id <= lastSPRegister());
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static const char* const nameForRegister[numberOfSPRegisters()] = {
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#define REGISTER_NAME(id, name, idx) name,
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FOR_EACH_SP_REGISTER(REGISTER_NAME)
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#undef REGISTER_NAME
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};
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return nameForRegister[id];
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}
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static const char* fprName(FPRegisterID id)
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{
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ASSERT(id >= firstFPRegister() && id <= lastFPRegister());
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static const char* const nameForRegister[numberOfFPRegisters()] = {
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#define REGISTER_NAME(id, name, r, cs) name,
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FOR_EACH_FP_REGISTER(REGISTER_NAME)
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#undef REGISTER_NAME
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};
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return nameForRegister[id];
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}
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MIPSAssembler()
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: m_indexOfLastWatchpoint(INT_MIN)
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, m_indexOfTailOfLastWatchpoint(INT_MIN)
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{
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}
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AssemblerBuffer& buffer() { return m_buffer; }
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// MIPS instruction opcode field position
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enum {
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OP_SH_RD = 11,
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OP_SH_RT = 16,
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OP_SH_RS = 21,
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OP_SH_SHAMT = 6,
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OP_SH_CODE = 16,
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OP_SH_FD = 6,
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OP_SH_FS = 11,
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OP_SH_FT = 16,
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OP_SH_MSB = 11,
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OP_SH_LSB = 6
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};
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// FCSR Bits
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enum {
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FP_CAUSE_INVALID_OPERATION = 1 << 16
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};
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void emitInst(MIPSWord op)
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{
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void* oldBase = m_buffer.data();
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m_buffer.putInt(op);
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void* newBase = m_buffer.data();
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if (oldBase != newBase)
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relocateJumps(oldBase, newBase);
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}
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void nop()
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{
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emitInst(0x00000000);
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}
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using CopyFunction = void*(&)(void*, const void*, size_t);
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template <CopyFunction copy>
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ALWAYS_INLINE static void fillNops(void* base, size_t size)
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{
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UNUSED_PARAM(copy);
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RELEASE_ASSERT(!(size % sizeof(int32_t)));
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int32_t* ptr = static_cast<int32_t*>(base);
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const size_t num32s = size / sizeof(int32_t);
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const int32_t insn = 0x00000000;
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for (size_t i = 0; i < num32s; i++)
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*ptr++ = insn;
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}
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void sync()
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{
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// FIXME: https://bugs.webkit.org/show_bug.cgi?id=169984
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// We might get a performance improvements by using SYNC_MB in some or
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// all cases.
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emitInst(0x0000000f);
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}
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/* Need to insert one load data delay nop for mips1. */
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void loadDelayNop()
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{
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#if WTF_MIPS_ISA(1)
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nop();
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#endif
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}
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/* Need to insert one coprocessor access delay nop for mips1. */
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void copDelayNop()
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{
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#if WTF_MIPS_ISA(1)
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nop();
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#endif
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}
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void move(RegisterID rd, RegisterID rs)
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{
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/* addu */
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emitInst(0x00000021 | (rd << OP_SH_RD) | (rs << OP_SH_RS));
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}
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/* Set an immediate value to a register. This may generate 1 or 2
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instructions. */
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void li(RegisterID dest, int imm)
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{
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if (imm >= -32768 && imm <= 32767)
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addiu(dest, MIPSRegisters::zero, imm);
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else if (imm >= 0 && imm < 65536)
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ori(dest, MIPSRegisters::zero, imm);
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else {
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lui(dest, imm >> 16);
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if (imm & 0xffff)
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ori(dest, dest, imm);
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}
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}
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void ext(RegisterID rt, RegisterID rs, int pos, int size)
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{
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int msb = size - 1;
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emitInst(0x7c000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (pos << OP_SH_LSB) | (msb << OP_SH_MSB));
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}
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void mfhc1(RegisterID rt, FPRegisterID fs)
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{
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emitInst(0x4460000 | (rt << OP_SH_RT) | (fs << OP_SH_FS));
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}
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void lui(RegisterID rt, int imm)
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{
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emitInst(0x3c000000 | (rt << OP_SH_RT) | (imm & 0xffff));
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}
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void clz(RegisterID rd, RegisterID rs)
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{
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emitInst(0x70000020 | (rd << OP_SH_RD) | (rs << OP_SH_RS) | (rd << OP_SH_RT));
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}
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void addiu(RegisterID rt, RegisterID rs, int imm)
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{
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emitInst(0x24000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (imm & 0xffff));
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}
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void addu(RegisterID rd, RegisterID rs, RegisterID rt)
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{
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emitInst(0x00000021 | (rd << OP_SH_RD) | (rs << OP_SH_RS) | (rt << OP_SH_RT));
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}
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void subu(RegisterID rd, RegisterID rs, RegisterID rt)
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{
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emitInst(0x00000023 | (rd << OP_SH_RD) | (rs << OP_SH_RS) | (rt << OP_SH_RT));
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}
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void mult(RegisterID rs, RegisterID rt)
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{
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emitInst(0x00000018 | (rs << OP_SH_RS) | (rt << OP_SH_RT));
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}
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void div(RegisterID rs, RegisterID rt)
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{
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emitInst(0x0000001a | (rs << OP_SH_RS) | (rt << OP_SH_RT));
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}
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void mfhi(RegisterID rd)
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{
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emitInst(0x00000010 | (rd << OP_SH_RD));
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}
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void mflo(RegisterID rd)
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{
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emitInst(0x00000012 | (rd << OP_SH_RD));
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}
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void mul(RegisterID rd, RegisterID rs, RegisterID rt)
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{
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#if WTF_MIPS_ISA_AT_LEAST(32)
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emitInst(0x70000002 | (rd << OP_SH_RD) | (rs << OP_SH_RS) | (rt << OP_SH_RT));
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#else
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mult(rs, rt);
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mflo(rd);
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#endif
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}
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void andInsn(RegisterID rd, RegisterID rs, RegisterID rt)
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{
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emitInst(0x00000024 | (rd << OP_SH_RD) | (rs << OP_SH_RS) | (rt << OP_SH_RT));
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}
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void andi(RegisterID rt, RegisterID rs, int imm)
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{
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emitInst(0x30000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (imm & 0xffff));
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}
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void nor(RegisterID rd, RegisterID rs, RegisterID rt)
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{
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emitInst(0x00000027 | (rd << OP_SH_RD) | (rs << OP_SH_RS) | (rt << OP_SH_RT));
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}
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void orInsn(RegisterID rd, RegisterID rs, RegisterID rt)
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{
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emitInst(0x00000025 | (rd << OP_SH_RD) | (rs << OP_SH_RS) | (rt << OP_SH_RT));
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}
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void ori(RegisterID rt, RegisterID rs, int imm)
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{
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emitInst(0x34000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (imm & 0xffff));
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}
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void xorInsn(RegisterID rd, RegisterID rs, RegisterID rt)
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{
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emitInst(0x00000026 | (rd << OP_SH_RD) | (rs << OP_SH_RS) | (rt << OP_SH_RT));
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}
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void xori(RegisterID rt, RegisterID rs, int imm)
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{
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emitInst(0x38000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (imm & 0xffff));
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}
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void slt(RegisterID rd, RegisterID rs, RegisterID rt)
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{
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emitInst(0x0000002a | (rd << OP_SH_RD) | (rs << OP_SH_RS) | (rt << OP_SH_RT));
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}
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void sltu(RegisterID rd, RegisterID rs, RegisterID rt)
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{
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emitInst(0x0000002b | (rd << OP_SH_RD) | (rs << OP_SH_RS) | (rt << OP_SH_RT));
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}
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void slti(RegisterID rt, RegisterID rs, int imm)
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{
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emitInst(0x28000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (imm & 0xffff));
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}
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void sltiu(RegisterID rt, RegisterID rs, int imm)
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{
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emitInst(0x2c000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (imm & 0xffff));
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}
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void sll(RegisterID rd, RegisterID rt, int shamt)
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{
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emitInst(0x00000000 | (rd << OP_SH_RD) | (rt << OP_SH_RT) | ((shamt & 0x1f) << OP_SH_SHAMT));
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}
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void sllv(RegisterID rd, RegisterID rt, RegisterID rs)
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{
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emitInst(0x00000004 | (rd << OP_SH_RD) | (rt << OP_SH_RT) | (rs << OP_SH_RS));
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}
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void sra(RegisterID rd, RegisterID rt, int shamt)
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{
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emitInst(0x00000003 | (rd << OP_SH_RD) | (rt << OP_SH_RT) | ((shamt & 0x1f) << OP_SH_SHAMT));
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}
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void srav(RegisterID rd, RegisterID rt, RegisterID rs)
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{
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emitInst(0x00000007 | (rd << OP_SH_RD) | (rt << OP_SH_RT) | (rs << OP_SH_RS));
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}
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void srl(RegisterID rd, RegisterID rt, int shamt)
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{
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emitInst(0x00000002 | (rd << OP_SH_RD) | (rt << OP_SH_RT) | ((shamt & 0x1f) << OP_SH_SHAMT));
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}
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void srlv(RegisterID rd, RegisterID rt, RegisterID rs)
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{
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emitInst(0x00000006 | (rd << OP_SH_RD) | (rt << OP_SH_RT) | (rs << OP_SH_RS));
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}
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void lb(RegisterID rt, RegisterID rs, int offset)
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{
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emitInst(0x80000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (offset & 0xffff));
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loadDelayNop();
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}
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void lbu(RegisterID rt, RegisterID rs, int offset)
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{
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emitInst(0x90000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (offset & 0xffff));
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loadDelayNop();
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}
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void lw(RegisterID rt, RegisterID rs, int offset)
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{
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emitInst(0x8c000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (offset & 0xffff));
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loadDelayNop();
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}
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void lwl(RegisterID rt, RegisterID rs, int offset)
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{
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emitInst(0x88000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (offset & 0xffff));
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loadDelayNop();
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}
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void lwr(RegisterID rt, RegisterID rs, int offset)
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{
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emitInst(0x98000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (offset & 0xffff));
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loadDelayNop();
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}
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void lh(RegisterID rt, RegisterID rs, int offset)
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{
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emitInst(0x84000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (offset & 0xffff));
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loadDelayNop();
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}
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void lhu(RegisterID rt, RegisterID rs, int offset)
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{
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emitInst(0x94000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (offset & 0xffff));
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loadDelayNop();
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}
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void sb(RegisterID rt, RegisterID rs, int offset)
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{
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emitInst(0xa0000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (offset & 0xffff));
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}
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void sh(RegisterID rt, RegisterID rs, int offset)
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{
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emitInst(0xa4000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (offset & 0xffff));
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}
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void sw(RegisterID rt, RegisterID rs, int offset)
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{
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emitInst(0xac000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (offset & 0xffff));
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}
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void jr(RegisterID rs)
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{
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emitInst(0x00000008 | (rs << OP_SH_RS));
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}
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void jalr(RegisterID rs)
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{
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emitInst(0x0000f809 | (rs << OP_SH_RS));
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}
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void jal()
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{
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emitInst(0x0c000000);
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}
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void bkpt()
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{
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int value = 512; /* BRK_BUG */
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emitInst(0x0000000d | ((value & 0x3ff) << OP_SH_CODE));
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}
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static bool isBkpt(void* address)
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{
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int value = 512; /* BRK_BUG */
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MIPSWord expected = (0x0000000d | ((value & 0x3ff) << OP_SH_CODE));
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MIPSWord candidateInstruction = *reinterpret_cast<MIPSWord*>(address);
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return candidateInstruction == expected;
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}
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void bgez(RegisterID rs, int imm)
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{
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emitInst(0x04010000 | (rs << OP_SH_RS) | (imm & 0xffff));
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}
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void bltz(RegisterID rs, int imm)
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{
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emitInst(0x04000000 | (rs << OP_SH_RS) | (imm & 0xffff));
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}
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void beq(RegisterID rs, RegisterID rt, int imm)
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{
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emitInst(0x10000000 | (rs << OP_SH_RS) | (rt << OP_SH_RT) | (imm & 0xffff));
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}
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void bne(RegisterID rs, RegisterID rt, int imm)
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{
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emitInst(0x14000000 | (rs << OP_SH_RS) | (rt << OP_SH_RT) | (imm & 0xffff));
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}
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void bc1t()
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{
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emitInst(0x45010000);
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}
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void bc1f()
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{
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emitInst(0x45000000);
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}
|
|
|
|
void appendJump()
|
|
{
|
|
m_jumps.append(m_buffer.label());
|
|
}
|
|
|
|
void addd(FPRegisterID fd, FPRegisterID fs, FPRegisterID ft)
|
|
{
|
|
emitInst(0x46200000 | (fd << OP_SH_FD) | (fs << OP_SH_FS) | (ft << OP_SH_FT));
|
|
}
|
|
|
|
void subd(FPRegisterID fd, FPRegisterID fs, FPRegisterID ft)
|
|
{
|
|
emitInst(0x46200001 | (fd << OP_SH_FD) | (fs << OP_SH_FS) | (ft << OP_SH_FT));
|
|
}
|
|
|
|
void muld(FPRegisterID fd, FPRegisterID fs, FPRegisterID ft)
|
|
{
|
|
emitInst(0x46200002 | (fd << OP_SH_FD) | (fs << OP_SH_FS) | (ft << OP_SH_FT));
|
|
}
|
|
|
|
void divd(FPRegisterID fd, FPRegisterID fs, FPRegisterID ft)
|
|
{
|
|
emitInst(0x46200003 | (fd << OP_SH_FD) | (fs << OP_SH_FS) | (ft << OP_SH_FT));
|
|
}
|
|
|
|
void lwc1(FPRegisterID ft, RegisterID rs, int offset)
|
|
{
|
|
emitInst(0xc4000000 | (ft << OP_SH_FT) | (rs << OP_SH_RS) | (offset & 0xffff));
|
|
copDelayNop();
|
|
}
|
|
|
|
void ldc1(FPRegisterID ft, RegisterID rs, int offset)
|
|
{
|
|
emitInst(0xd4000000 | (ft << OP_SH_FT) | (rs << OP_SH_RS) | (offset & 0xffff));
|
|
}
|
|
|
|
void swc1(FPRegisterID ft, RegisterID rs, int offset)
|
|
{
|
|
emitInst(0xe4000000 | (ft << OP_SH_FT) | (rs << OP_SH_RS) | (offset & 0xffff));
|
|
}
|
|
|
|
void sdc1(FPRegisterID ft, RegisterID rs, int offset)
|
|
{
|
|
emitInst(0xf4000000 | (ft << OP_SH_FT) | (rs << OP_SH_RS) | (offset & 0xffff));
|
|
}
|
|
|
|
void mtc1(RegisterID rt, FPRegisterID fs)
|
|
{
|
|
emitInst(0x44800000 | (fs << OP_SH_FS) | (rt << OP_SH_RT));
|
|
copDelayNop();
|
|
}
|
|
|
|
void mthc1(RegisterID rt, FPRegisterID fs)
|
|
{
|
|
emitInst(0x44e00000 | (fs << OP_SH_FS) | (rt << OP_SH_RT));
|
|
copDelayNop();
|
|
}
|
|
|
|
void mfc1(RegisterID rt, FPRegisterID fs)
|
|
{
|
|
emitInst(0x44000000 | (fs << OP_SH_FS) | (rt << OP_SH_RT));
|
|
copDelayNop();
|
|
}
|
|
|
|
void sqrtd(FPRegisterID fd, FPRegisterID fs)
|
|
{
|
|
emitInst(0x46200004 | (fd << OP_SH_FD) | (fs << OP_SH_FS));
|
|
}
|
|
|
|
void absd(FPRegisterID fd, FPRegisterID fs)
|
|
{
|
|
emitInst(0x46200005 | (fd << OP_SH_FD) | (fs << OP_SH_FS));
|
|
}
|
|
|
|
void movd(FPRegisterID fd, FPRegisterID fs)
|
|
{
|
|
emitInst(0x46200006 | (fd << OP_SH_FD) | (fs << OP_SH_FS));
|
|
}
|
|
|
|
void negd(FPRegisterID fd, FPRegisterID fs)
|
|
{
|
|
emitInst(0x46200007 | (fd << OP_SH_FD) | (fs << OP_SH_FS));
|
|
}
|
|
|
|
void truncwd(FPRegisterID fd, FPRegisterID fs)
|
|
{
|
|
emitInst(0x4620000d | (fd << OP_SH_FD) | (fs << OP_SH_FS));
|
|
}
|
|
|
|
void cvtdw(FPRegisterID fd, FPRegisterID fs)
|
|
{
|
|
emitInst(0x46800021 | (fd << OP_SH_FD) | (fs << OP_SH_FS));
|
|
}
|
|
|
|
void cvtds(FPRegisterID fd, FPRegisterID fs)
|
|
{
|
|
emitInst(0x46000021 | (fd << OP_SH_FD) | (fs << OP_SH_FS));
|
|
}
|
|
|
|
void cvtwd(FPRegisterID fd, FPRegisterID fs)
|
|
{
|
|
emitInst(0x46200024 | (fd << OP_SH_FD) | (fs << OP_SH_FS));
|
|
}
|
|
|
|
void cvtsd(FPRegisterID fd, FPRegisterID fs)
|
|
{
|
|
emitInst(0x46200020 | (fd << OP_SH_FD) | (fs << OP_SH_FS));
|
|
}
|
|
|
|
void ceqd(FPRegisterID fs, FPRegisterID ft)
|
|
{
|
|
emitInst(0x46200032 | (fs << OP_SH_FS) | (ft << OP_SH_FT));
|
|
copDelayNop();
|
|
}
|
|
|
|
void cngtd(FPRegisterID fs, FPRegisterID ft)
|
|
{
|
|
emitInst(0x4620003f | (fs << OP_SH_FS) | (ft << OP_SH_FT));
|
|
copDelayNop();
|
|
}
|
|
|
|
void cnged(FPRegisterID fs, FPRegisterID ft)
|
|
{
|
|
emitInst(0x4620003d | (fs << OP_SH_FS) | (ft << OP_SH_FT));
|
|
copDelayNop();
|
|
}
|
|
|
|
void cltd(FPRegisterID fs, FPRegisterID ft)
|
|
{
|
|
emitInst(0x4620003c | (fs << OP_SH_FS) | (ft << OP_SH_FT));
|
|
copDelayNop();
|
|
}
|
|
|
|
void cled(FPRegisterID fs, FPRegisterID ft)
|
|
{
|
|
emitInst(0x4620003e | (fs << OP_SH_FS) | (ft << OP_SH_FT));
|
|
copDelayNop();
|
|
}
|
|
|
|
void cueqd(FPRegisterID fs, FPRegisterID ft)
|
|
{
|
|
emitInst(0x46200033 | (fs << OP_SH_FS) | (ft << OP_SH_FT));
|
|
copDelayNop();
|
|
}
|
|
|
|
void coled(FPRegisterID fs, FPRegisterID ft)
|
|
{
|
|
emitInst(0x46200036 | (fs << OP_SH_FS) | (ft << OP_SH_FT));
|
|
copDelayNop();
|
|
}
|
|
|
|
void coltd(FPRegisterID fs, FPRegisterID ft)
|
|
{
|
|
emitInst(0x46200034 | (fs << OP_SH_FS) | (ft << OP_SH_FT));
|
|
copDelayNop();
|
|
}
|
|
|
|
void culed(FPRegisterID fs, FPRegisterID ft)
|
|
{
|
|
emitInst(0x46200037 | (fs << OP_SH_FS) | (ft << OP_SH_FT));
|
|
copDelayNop();
|
|
}
|
|
|
|
void cultd(FPRegisterID fs, FPRegisterID ft)
|
|
{
|
|
emitInst(0x46200035 | (fs << OP_SH_FS) | (ft << OP_SH_FT));
|
|
copDelayNop();
|
|
}
|
|
|
|
void cfc1(RegisterID rt, SPRegisterID fs)
|
|
{
|
|
emitInst(0x44400000 | (rt << OP_SH_RT) | (fs << OP_SH_FS));
|
|
copDelayNop();
|
|
}
|
|
|
|
// General helpers
|
|
|
|
AssemblerLabel labelIgnoringWatchpoints()
|
|
{
|
|
return m_buffer.label();
|
|
}
|
|
|
|
AssemblerLabel labelForWatchpoint()
|
|
{
|
|
AssemblerLabel result = m_buffer.label();
|
|
if (static_cast<int>(result.offset()) != m_indexOfLastWatchpoint)
|
|
result = label();
|
|
m_indexOfLastWatchpoint = result.offset();
|
|
m_indexOfTailOfLastWatchpoint = result.offset() + maxJumpReplacementSize();
|
|
return result;
|
|
}
|
|
|
|
AssemblerLabel label()
|
|
{
|
|
AssemblerLabel result = m_buffer.label();
|
|
while (UNLIKELY(static_cast<int>(result.offset()) < m_indexOfTailOfLastWatchpoint)) {
|
|
nop();
|
|
result = m_buffer.label();
|
|
}
|
|
return result;
|
|
}
|
|
|
|
AssemblerLabel align(int alignment)
|
|
{
|
|
while (!m_buffer.isAligned(alignment))
|
|
bkpt();
|
|
|
|
return label();
|
|
}
|
|
|
|
static void* getRelocatedAddress(void* code, AssemblerLabel label)
|
|
{
|
|
return reinterpret_cast<void*>(reinterpret_cast<char*>(code) + label.offset());
|
|
}
|
|
|
|
static int getDifferenceBetweenLabels(AssemblerLabel a, AssemblerLabel b)
|
|
{
|
|
return b.offset() - a.offset();
|
|
}
|
|
|
|
// Assembler admin methods:
|
|
|
|
size_t codeSize() const
|
|
{
|
|
return m_buffer.codeSize();
|
|
}
|
|
|
|
unsigned debugOffset() { return m_buffer.debugOffset(); }
|
|
|
|
// Assembly helpers for moving data between fp and registers.
|
|
void vmov(RegisterID rd1, RegisterID rd2, FPRegisterID rn)
|
|
{
|
|
#if WTF_MIPS_ISA_REV(2) && WTF_MIPS_FP64
|
|
mfc1(rd1, rn);
|
|
mfhc1(rd2, rn);
|
|
#else
|
|
mfc1(rd1, rn);
|
|
mfc1(rd2, FPRegisterID(rn + 1));
|
|
#endif
|
|
}
|
|
|
|
void vmov(FPRegisterID rd, RegisterID rn1, RegisterID rn2)
|
|
{
|
|
#if WTF_MIPS_ISA_REV(2) && WTF_MIPS_FP64
|
|
mtc1(rn1, rd);
|
|
mthc1(rn2, rd);
|
|
#else
|
|
mtc1(rn1, rd);
|
|
mtc1(rn2, FPRegisterID(rd + 1));
|
|
#endif
|
|
}
|
|
|
|
static unsigned getCallReturnOffset(AssemblerLabel call)
|
|
{
|
|
// The return address is after a call and a delay slot instruction
|
|
return call.offset();
|
|
}
|
|
|
|
// Linking & patching:
|
|
//
|
|
// 'link' and 'patch' methods are for use on unprotected code - such as the code
|
|
// within the AssemblerBuffer, and code being patched by the patch buffer. Once
|
|
// code has been finalized it is (platform support permitting) within a non-
|
|
// writable region of memory; to modify the code in an execute-only execuable
|
|
// pool the 'repatch' and 'relink' methods should be used.
|
|
|
|
static size_t linkDirectJump(void* code, void* to)
|
|
{
|
|
MIPSWord* insn = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(code));
|
|
size_t ops = 0;
|
|
int32_t slotAddr = reinterpret_cast<int>(insn) + 4;
|
|
int32_t toAddr = reinterpret_cast<int>(to);
|
|
|
|
if ((slotAddr & 0xf0000000) != (toAddr & 0xf0000000)) {
|
|
// lui
|
|
*insn = 0x3c000000 | (MIPSRegisters::t9 << OP_SH_RT) | ((toAddr >> 16) & 0xffff);
|
|
++insn;
|
|
// ori
|
|
*insn = 0x34000000 | (MIPSRegisters::t9 << OP_SH_RT) | (MIPSRegisters::t9 << OP_SH_RS) | (toAddr & 0xffff);
|
|
++insn;
|
|
// jr
|
|
*insn = 0x00000008 | (MIPSRegisters::t9 << OP_SH_RS);
|
|
++insn;
|
|
ops = 4 * sizeof(MIPSWord);
|
|
} else {
|
|
// j
|
|
*insn = 0x08000000 | ((toAddr & 0x0fffffff) >> 2);
|
|
++insn;
|
|
ops = 2 * sizeof(MIPSWord);
|
|
}
|
|
// nop
|
|
*insn = 0x00000000;
|
|
return ops;
|
|
}
|
|
|
|
void linkJump(AssemblerLabel from, AssemblerLabel to)
|
|
{
|
|
ASSERT(to.isSet());
|
|
ASSERT(from.isSet());
|
|
MIPSWord* insn = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(m_buffer.data()) + from.offset());
|
|
MIPSWord* toPos = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(m_buffer.data()) + to.offset());
|
|
|
|
ASSERT(!(*(insn - 1)) && !(*(insn - 2)) && !(*(insn - 3)) && !(*(insn - 5)));
|
|
insn = insn - 6;
|
|
linkWithOffset(insn, toPos);
|
|
}
|
|
|
|
static void linkJump(void* code, AssemblerLabel from, void* to)
|
|
{
|
|
ASSERT(from.isSet());
|
|
MIPSWord* insn = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(code) + from.offset());
|
|
|
|
ASSERT(!(*(insn - 1)) && !(*(insn - 2)) && !(*(insn - 3)) && !(*(insn - 5)));
|
|
insn = insn - 6;
|
|
linkWithOffset(insn, to);
|
|
}
|
|
|
|
static void linkCall(void* code, AssemblerLabel from, void* to)
|
|
{
|
|
MIPSWord* insn = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(code) + from.offset());
|
|
linkCallInternal(insn, to);
|
|
}
|
|
|
|
static void linkPointer(void* code, AssemblerLabel from, void* to)
|
|
{
|
|
MIPSWord* insn = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(code) + from.offset());
|
|
ASSERT((*insn & 0xffe00000) == 0x3c000000); // lui
|
|
*insn = (*insn & 0xffff0000) | ((reinterpret_cast<intptr_t>(to) >> 16) & 0xffff);
|
|
insn++;
|
|
ASSERT((*insn & 0xfc000000) == 0x34000000); // ori
|
|
*insn = (*insn & 0xffff0000) | (reinterpret_cast<intptr_t>(to) & 0xffff);
|
|
}
|
|
|
|
static void relinkJump(void* from, void* to)
|
|
{
|
|
MIPSWord* insn = reinterpret_cast<MIPSWord*>(from);
|
|
|
|
ASSERT(!(*(insn - 1)) && !(*(insn - 5)));
|
|
insn = insn - 6;
|
|
int flushSize = linkWithOffset(insn, to);
|
|
|
|
cacheFlush(insn, flushSize);
|
|
}
|
|
|
|
static void relinkJumpToNop(void* from)
|
|
{
|
|
relinkJump(from, from);
|
|
}
|
|
|
|
static void relinkCall(void* from, void* to)
|
|
{
|
|
void* start;
|
|
int size = linkCallInternal(from, to);
|
|
if (size == sizeof(MIPSWord))
|
|
start = reinterpret_cast<void*>(reinterpret_cast<intptr_t>(from) - 2 * sizeof(MIPSWord));
|
|
else
|
|
start = reinterpret_cast<void*>(reinterpret_cast<intptr_t>(from) - 4 * sizeof(MIPSWord));
|
|
|
|
cacheFlush(start, size);
|
|
}
|
|
|
|
static void repatchInt32(void* from, int32_t to)
|
|
{
|
|
MIPSWord* insn = reinterpret_cast<MIPSWord*>(from);
|
|
ASSERT((*insn & 0xffe00000) == 0x3c000000); // lui
|
|
*insn = (*insn & 0xffff0000) | ((to >> 16) & 0xffff);
|
|
insn++;
|
|
ASSERT((*insn & 0xfc000000) == 0x34000000); // ori
|
|
*insn = (*insn & 0xffff0000) | (to & 0xffff);
|
|
cacheFlush(from, 2 * sizeof(MIPSWord));
|
|
}
|
|
|
|
static int32_t readInt32(void* from)
|
|
{
|
|
MIPSWord* insn = reinterpret_cast<MIPSWord*>(from);
|
|
ASSERT((*insn & 0xffe00000) == 0x3c000000); // lui
|
|
int32_t result = (*insn & 0x0000ffff) << 16;
|
|
insn++;
|
|
ASSERT((*insn & 0xfc000000) == 0x34000000); // ori
|
|
result |= *insn & 0x0000ffff;
|
|
return result;
|
|
}
|
|
|
|
static void repatchCompact(void* where, int32_t value)
|
|
{
|
|
repatchInt32(where, value);
|
|
}
|
|
|
|
static void repatchPointer(void* from, void* to)
|
|
{
|
|
repatchInt32(from, reinterpret_cast<int32_t>(to));
|
|
}
|
|
|
|
static void* readPointer(void* from)
|
|
{
|
|
return reinterpret_cast<void*>(readInt32(from));
|
|
}
|
|
|
|
static void* readCallTarget(void* from)
|
|
{
|
|
MIPSWord* insn = reinterpret_cast<MIPSWord*>(from);
|
|
insn -= 4;
|
|
ASSERT((*insn & 0xffe00000) == 0x3c000000); // lui
|
|
int32_t result = (*insn & 0x0000ffff) << 16;
|
|
insn++;
|
|
ASSERT((*insn & 0xfc000000) == 0x34000000); // ori
|
|
result |= *insn & 0x0000ffff;
|
|
return reinterpret_cast<void*>(result);
|
|
}
|
|
|
|
static void cacheFlush(void* code, size_t size)
|
|
{
|
|
intptr_t end = reinterpret_cast<intptr_t>(code) + size;
|
|
__builtin___clear_cache(reinterpret_cast<char*>(code), reinterpret_cast<char*>(end));
|
|
}
|
|
|
|
static ptrdiff_t maxJumpReplacementSize()
|
|
{
|
|
return sizeof(MIPSWord) * 4;
|
|
}
|
|
|
|
static constexpr ptrdiff_t patchableJumpSize()
|
|
{
|
|
return sizeof(MIPSWord) * 8;
|
|
}
|
|
|
|
static void revertJumpToMove(void* instructionStart, RegisterID rt, int imm)
|
|
{
|
|
MIPSWord* insn = static_cast<MIPSWord*>(instructionStart);
|
|
size_t codeSize = 2 * sizeof(MIPSWord);
|
|
|
|
// lui
|
|
*insn = 0x3c000000 | (rt << OP_SH_RT) | ((imm >> 16) & 0xffff);
|
|
++insn;
|
|
// ori
|
|
*insn = 0x34000000 | (rt << OP_SH_RS) | (rt << OP_SH_RT) | (imm & 0xffff);
|
|
++insn;
|
|
// if jr $t9
|
|
if (*insn == 0x03200008) {
|
|
*insn = 0x00000000;
|
|
codeSize += sizeof(MIPSWord);
|
|
}
|
|
cacheFlush(instructionStart, codeSize);
|
|
}
|
|
|
|
static void replaceWithJump(void* instructionStart, void* to)
|
|
{
|
|
ASSERT(!(bitwise_cast<uintptr_t>(instructionStart) & 3));
|
|
ASSERT(!(bitwise_cast<uintptr_t>(to) & 3));
|
|
size_t ops = linkDirectJump(instructionStart, to);
|
|
cacheFlush(instructionStart, ops);
|
|
}
|
|
|
|
static void replaceWithLoad(void* instructionStart)
|
|
{
|
|
MIPSWord* insn = reinterpret_cast<MIPSWord*>(instructionStart);
|
|
ASSERT((*insn & 0xffe00000) == 0x3c000000); // lui
|
|
insn++;
|
|
ASSERT((*insn & 0xfc0007ff) == 0x00000021); // addu
|
|
insn++;
|
|
*insn = 0x8c000000 | ((*insn) & 0x3ffffff); // lw
|
|
cacheFlush(insn, 4);
|
|
}
|
|
|
|
static void replaceWithAddressComputation(void* instructionStart)
|
|
{
|
|
MIPSWord* insn = reinterpret_cast<MIPSWord*>(instructionStart);
|
|
ASSERT((*insn & 0xffe00000) == 0x3c000000); // lui
|
|
insn++;
|
|
ASSERT((*insn & 0xfc0007ff) == 0x00000021); // addu
|
|
insn++;
|
|
*insn = 0x24000000 | ((*insn) & 0x3ffffff); // addiu
|
|
cacheFlush(insn, 4);
|
|
}
|
|
|
|
/* Update each jump in the buffer of newBase. */
|
|
void relocateJumps(void* oldBase, void* newBase)
|
|
{
|
|
// Check each jump
|
|
for (Jumps::Iterator iter = m_jumps.begin(); iter != m_jumps.end(); ++iter) {
|
|
int pos = iter->offset();
|
|
MIPSWord* insn = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(newBase) + pos);
|
|
insn = insn + 2;
|
|
// Need to make sure we have 5 valid instructions after pos
|
|
if ((unsigned)pos >= m_buffer.codeSize() - 5 * sizeof(MIPSWord))
|
|
continue;
|
|
|
|
if ((*insn & 0xfc000000) == 0x08000000) { // j
|
|
int offset = *insn & 0x03ffffff;
|
|
int oldInsnAddress = (int)insn - (int)newBase + (int)oldBase;
|
|
int topFourBits = (oldInsnAddress + 4) >> 28;
|
|
int oldTargetAddress = (topFourBits << 28) | (offset << 2);
|
|
int newTargetAddress = oldTargetAddress - (int)oldBase + (int)newBase;
|
|
int newInsnAddress = (int)insn;
|
|
if (((newInsnAddress + 4) >> 28) == (newTargetAddress >> 28))
|
|
*insn = 0x08000000 | ((newTargetAddress >> 2) & 0x3ffffff);
|
|
else {
|
|
/* lui */
|
|
*insn = 0x3c000000 | (MIPSRegisters::t9 << OP_SH_RT) | ((newTargetAddress >> 16) & 0xffff);
|
|
/* ori */
|
|
*(insn + 1) = 0x34000000 | (MIPSRegisters::t9 << OP_SH_RT) | (MIPSRegisters::t9 << OP_SH_RS) | (newTargetAddress & 0xffff);
|
|
/* jr */
|
|
*(insn + 2) = 0x00000008 | (MIPSRegisters::t9 << OP_SH_RS);
|
|
}
|
|
} else if ((*insn & 0xffe00000) == 0x3c000000) { // lui
|
|
int high = (*insn & 0xffff) << 16;
|
|
int low = *(insn + 1) & 0xffff;
|
|
int oldTargetAddress = high | low;
|
|
int newTargetAddress = oldTargetAddress - (int)oldBase + (int)newBase;
|
|
/* lui */
|
|
*insn = 0x3c000000 | (MIPSRegisters::t9 << OP_SH_RT) | ((newTargetAddress >> 16) & 0xffff);
|
|
/* ori */
|
|
*(insn + 1) = 0x34000000 | (MIPSRegisters::t9 << OP_SH_RT) | (MIPSRegisters::t9 << OP_SH_RS) | (newTargetAddress & 0xffff);
|
|
}
|
|
}
|
|
}
|
|
|
|
private:
|
|
static int linkWithOffset(MIPSWord* insn, void* to)
|
|
{
|
|
ASSERT((*insn & 0xfc000000) == 0x10000000 // beq
|
|
|| (*insn & 0xfc000000) == 0x14000000 // bne
|
|
|| (*insn & 0xffff0000) == 0x45010000 // bc1t
|
|
|| (*insn & 0xffff0000) == 0x45000000); // bc1f
|
|
intptr_t diff = (reinterpret_cast<intptr_t>(to) - reinterpret_cast<intptr_t>(insn) - 4) >> 2;
|
|
|
|
if (diff < -32768 || diff > 32767 || *(insn + 2) != 0x10000003) {
|
|
/*
|
|
Convert the sequence:
|
|
beq $2, $3, target
|
|
nop
|
|
b 1f
|
|
nop
|
|
nop
|
|
nop
|
|
1:
|
|
|
|
to the new sequence if possible:
|
|
bne $2, $3, 1f
|
|
nop
|
|
j target
|
|
nop
|
|
nop
|
|
nop
|
|
1:
|
|
|
|
OR to the new sequence:
|
|
bne $2, $3, 1f
|
|
nop
|
|
lui $25, target >> 16
|
|
ori $25, $25, target & 0xffff
|
|
jr $25
|
|
nop
|
|
1:
|
|
|
|
Note: beq/bne/bc1t/bc1f are converted to bne/beq/bc1f/bc1t.
|
|
*/
|
|
|
|
if (*(insn + 2) == 0x10000003) {
|
|
if ((*insn & 0xfc000000) == 0x10000000) // beq
|
|
*insn = (*insn & 0x03ff0000) | 0x14000005; // bne
|
|
else if ((*insn & 0xfc000000) == 0x14000000) // bne
|
|
*insn = (*insn & 0x03ff0000) | 0x10000005; // beq
|
|
else if ((*insn & 0xffff0000) == 0x45010000) // bc1t
|
|
*insn = 0x45000005; // bc1f
|
|
else if ((*insn & 0xffff0000) == 0x45000000) // bc1f
|
|
*insn = 0x45010005; // bc1t
|
|
else
|
|
ASSERT(0);
|
|
}
|
|
|
|
insn = insn + 2;
|
|
if ((reinterpret_cast<intptr_t>(insn) + 4) >> 28
|
|
== reinterpret_cast<intptr_t>(to) >> 28) {
|
|
*insn = 0x08000000 | ((reinterpret_cast<intptr_t>(to) >> 2) & 0x3ffffff);
|
|
*(insn + 1) = 0;
|
|
return 4 * sizeof(MIPSWord);
|
|
}
|
|
|
|
intptr_t newTargetAddress = reinterpret_cast<intptr_t>(to);
|
|
/* lui */
|
|
*insn = 0x3c000000 | (MIPSRegisters::t9 << OP_SH_RT) | ((newTargetAddress >> 16) & 0xffff);
|
|
/* ori */
|
|
*(insn + 1) = 0x34000000 | (MIPSRegisters::t9 << OP_SH_RT) | (MIPSRegisters::t9 << OP_SH_RS) | (newTargetAddress & 0xffff);
|
|
/* jr */
|
|
*(insn + 2) = 0x00000008 | (MIPSRegisters::t9 << OP_SH_RS);
|
|
return 5 * sizeof(MIPSWord);
|
|
}
|
|
|
|
*insn = (*insn & 0xffff0000) | (diff & 0xffff);
|
|
return sizeof(MIPSWord);
|
|
}
|
|
|
|
static int linkCallInternal(void* from, void* to)
|
|
{
|
|
MIPSWord* insn = reinterpret_cast<MIPSWord*>(from);
|
|
insn = insn - 4;
|
|
|
|
if ((*(insn + 2) & 0xfc000000) == 0x0c000000) { // jal
|
|
if ((reinterpret_cast<intptr_t>(from) - 4) >> 28
|
|
== reinterpret_cast<intptr_t>(to) >> 28) {
|
|
*(insn + 2) = 0x0c000000 | ((reinterpret_cast<intptr_t>(to) >> 2) & 0x3ffffff);
|
|
return sizeof(MIPSWord);
|
|
}
|
|
|
|
/* lui $25, (to >> 16) & 0xffff */
|
|
*insn = 0x3c000000 | (MIPSRegisters::t9 << OP_SH_RT) | ((reinterpret_cast<intptr_t>(to) >> 16) & 0xffff);
|
|
/* ori $25, $25, to & 0xffff */
|
|
*(insn + 1) = 0x34000000 | (MIPSRegisters::t9 << OP_SH_RT) | (MIPSRegisters::t9 << OP_SH_RS) | (reinterpret_cast<intptr_t>(to) & 0xffff);
|
|
/* jalr $25 */
|
|
*(insn + 2) = 0x0000f809 | (MIPSRegisters::t9 << OP_SH_RS);
|
|
return 3 * sizeof(MIPSWord);
|
|
}
|
|
|
|
ASSERT((*insn & 0xffe00000) == 0x3c000000); // lui
|
|
ASSERT((*(insn + 1) & 0xfc000000) == 0x34000000); // ori
|
|
|
|
/* lui */
|
|
*insn = (*insn & 0xffff0000) | ((reinterpret_cast<intptr_t>(to) >> 16) & 0xffff);
|
|
/* ori */
|
|
*(insn + 1) = (*(insn + 1) & 0xffff0000) | (reinterpret_cast<intptr_t>(to) & 0xffff);
|
|
return 2 * sizeof(MIPSWord);
|
|
}
|
|
|
|
AssemblerBuffer m_buffer;
|
|
Jumps m_jumps;
|
|
int m_indexOfLastWatchpoint;
|
|
int m_indexOfTailOfLastWatchpoint;
|
|
};
|
|
|
|
} // namespace JSC
|
|
|
|
#endif // ENABLE(ASSEMBLER) && CPU(MIPS)
|