mirror of
https://github.com/darlinghq/darling-JavaScriptCore.git
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1642 lines
54 KiB
C++
1642 lines
54 KiB
C++
/*
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* Copyright (C) 2008-2017 Apple Inc.
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* Copyright (C) 2009, 2010 University of Szeged
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#pragma once
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#if ENABLE(ASSEMBLER) && CPU(ARM_TRADITIONAL)
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#include "ARMAssembler.h"
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#include "AbstractMacroAssembler.h"
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namespace JSC {
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class MacroAssemblerARM : public AbstractMacroAssembler<ARMAssembler> {
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static const int DoubleConditionMask = 0x0f;
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static const int DoubleConditionBitSpecial = 0x10;
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COMPILE_ASSERT(!(DoubleConditionBitSpecial & DoubleConditionMask), DoubleConditionBitSpecial_should_not_interfere_with_ARMAssembler_Condition_codes);
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public:
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static const unsigned numGPRs = 16;
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static const unsigned numFPRs = 16;
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typedef ARMRegisters::FPRegisterID FPRegisterID;
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enum RelationalCondition {
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Equal = ARMAssembler::EQ,
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NotEqual = ARMAssembler::NE,
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Above = ARMAssembler::HI,
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AboveOrEqual = ARMAssembler::CS,
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Below = ARMAssembler::CC,
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BelowOrEqual = ARMAssembler::LS,
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GreaterThan = ARMAssembler::GT,
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GreaterThanOrEqual = ARMAssembler::GE,
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LessThan = ARMAssembler::LT,
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LessThanOrEqual = ARMAssembler::LE
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};
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enum ResultCondition {
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Overflow = ARMAssembler::VS,
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Signed = ARMAssembler::MI,
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PositiveOrZero = ARMAssembler::PL,
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Zero = ARMAssembler::EQ,
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NonZero = ARMAssembler::NE
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};
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enum DoubleCondition {
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// These conditions will only evaluate to true if the comparison is ordered - i.e. neither operand is NaN.
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DoubleEqual = ARMAssembler::EQ,
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DoubleNotEqual = ARMAssembler::NE | DoubleConditionBitSpecial,
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DoubleGreaterThan = ARMAssembler::GT,
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DoubleGreaterThanOrEqual = ARMAssembler::GE,
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DoubleLessThan = ARMAssembler::CC,
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DoubleLessThanOrEqual = ARMAssembler::LS,
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// If either operand is NaN, these conditions always evaluate to true.
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DoubleEqualOrUnordered = ARMAssembler::EQ | DoubleConditionBitSpecial,
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DoubleNotEqualOrUnordered = ARMAssembler::NE,
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DoubleGreaterThanOrUnordered = ARMAssembler::HI,
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DoubleGreaterThanOrEqualOrUnordered = ARMAssembler::CS,
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DoubleLessThanOrUnordered = ARMAssembler::LT,
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DoubleLessThanOrEqualOrUnordered = ARMAssembler::LE,
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};
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static const RegisterID stackPointerRegister = ARMRegisters::sp;
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static const RegisterID framePointerRegister = ARMRegisters::fp;
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static const RegisterID linkRegister = ARMRegisters::lr;
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static const Scale ScalePtr = TimesFour;
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void add32(RegisterID src, RegisterID dest)
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{
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m_assembler.adds(dest, dest, src);
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}
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void add32(RegisterID op1, RegisterID op2, RegisterID dest)
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{
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m_assembler.adds(dest, op1, op2);
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}
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void add32(TrustedImm32 imm, Address address)
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{
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load32(address, ARMRegisters::S1);
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add32(imm, ARMRegisters::S1);
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store32(ARMRegisters::S1, address);
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}
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void add32(TrustedImm32 imm, RegisterID dest)
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{
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m_assembler.adds(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
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}
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void add32(AbsoluteAddress src, RegisterID dest)
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{
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move(TrustedImmPtr(src.m_ptr), ARMRegisters::S1);
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m_assembler.dtrUp(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0);
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add32(ARMRegisters::S1, dest);
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}
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void add32(Address src, RegisterID dest)
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{
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load32(src, ARMRegisters::S1);
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add32(ARMRegisters::S1, dest);
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}
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void add32(RegisterID src, TrustedImm32 imm, RegisterID dest)
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{
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m_assembler.adds(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
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}
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void and32(RegisterID src, RegisterID dest)
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{
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m_assembler.bitAnds(dest, dest, src);
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}
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void and32(RegisterID op1, RegisterID op2, RegisterID dest)
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{
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m_assembler.bitAnds(dest, op1, op2);
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}
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void and32(TrustedImm32 imm, RegisterID dest)
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{
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ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true);
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if (w & ARMAssembler::Op2InvertedImmediate)
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m_assembler.bics(dest, dest, w & ~ARMAssembler::Op2InvertedImmediate);
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else
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m_assembler.bitAnds(dest, dest, w);
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}
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void and32(TrustedImm32 imm, RegisterID src, RegisterID dest)
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{
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ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true);
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if (w & ARMAssembler::Op2InvertedImmediate)
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m_assembler.bics(dest, src, w & ~ARMAssembler::Op2InvertedImmediate);
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else
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m_assembler.bitAnds(dest, src, w);
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}
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void and32(Address src, RegisterID dest)
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{
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load32(src, ARMRegisters::S1);
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and32(ARMRegisters::S1, dest);
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}
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void lshift32(RegisterID shiftAmount, RegisterID dest)
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{
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lshift32(dest, shiftAmount, dest);
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}
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void lshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
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{
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ARMWord w = ARMAssembler::getOp2Byte(0x1f);
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m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w);
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m_assembler.movs(dest, m_assembler.lslRegister(src, ARMRegisters::S0));
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}
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void lshift32(TrustedImm32 imm, RegisterID dest)
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{
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m_assembler.movs(dest, m_assembler.lsl(dest, imm.m_value & 0x1f));
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}
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void lshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
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{
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m_assembler.movs(dest, m_assembler.lsl(src, imm.m_value & 0x1f));
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}
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void mul32(RegisterID op1, RegisterID op2, RegisterID dest)
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{
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if (op2 == dest) {
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if (op1 == dest) {
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move(op2, ARMRegisters::S0);
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op2 = ARMRegisters::S0;
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} else {
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// Swap the operands.
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RegisterID tmp = op1;
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op1 = op2;
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op2 = tmp;
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}
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}
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m_assembler.muls(dest, op1, op2);
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}
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void mul32(RegisterID src, RegisterID dest)
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{
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mul32(src, dest, dest);
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}
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void mul32(TrustedImm32 imm, RegisterID src, RegisterID dest)
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{
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move(imm, ARMRegisters::S0);
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m_assembler.muls(dest, src, ARMRegisters::S0);
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}
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void neg32(RegisterID srcDest)
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{
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m_assembler.rsbs(srcDest, srcDest, ARMAssembler::getOp2Byte(0));
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}
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void or32(RegisterID src, RegisterID dest)
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{
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m_assembler.orrs(dest, dest, src);
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}
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void or32(RegisterID src, AbsoluteAddress dest)
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{
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move(TrustedImmPtr(dest.m_ptr), ARMRegisters::S0);
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load32(Address(ARMRegisters::S0), ARMRegisters::S1);
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or32(src, ARMRegisters::S1);
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store32(ARMRegisters::S1, ARMRegisters::S0);
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}
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void or32(TrustedImm32 imm, AbsoluteAddress dest)
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{
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move(TrustedImmPtr(dest.m_ptr), ARMRegisters::S0);
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load32(Address(ARMRegisters::S0), ARMRegisters::S1);
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or32(imm, ARMRegisters::S1); // It uses S0 as temporary register, we need to reload the address.
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move(TrustedImmPtr(dest.m_ptr), ARMRegisters::S0);
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store32(ARMRegisters::S1, ARMRegisters::S0);
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}
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void or32(TrustedImm32 imm, Address address)
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{
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load32(address, ARMRegisters::S0);
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or32(imm, ARMRegisters::S0, ARMRegisters::S0);
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store32(ARMRegisters::S0, address);
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}
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void or32(TrustedImm32 imm, RegisterID dest)
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{
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ASSERT(dest != ARMRegisters::S0);
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m_assembler.orrs(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
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}
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void or32(TrustedImm32 imm, RegisterID src, RegisterID dest)
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{
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ASSERT(src != ARMRegisters::S0);
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m_assembler.orrs(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
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}
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void or32(RegisterID op1, RegisterID op2, RegisterID dest)
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{
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m_assembler.orrs(dest, op1, op2);
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}
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void rshift32(RegisterID shiftAmount, RegisterID dest)
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{
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rshift32(dest, shiftAmount, dest);
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}
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void rshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
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{
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ARMWord w = ARMAssembler::getOp2Byte(0x1f);
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m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w);
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m_assembler.movs(dest, m_assembler.asrRegister(src, ARMRegisters::S0));
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}
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void rshift32(TrustedImm32 imm, RegisterID dest)
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{
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rshift32(dest, imm, dest);
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}
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void rshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
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{
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if (!imm.m_value)
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move(src, dest);
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else
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m_assembler.movs(dest, m_assembler.asr(src, imm.m_value & 0x1f));
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}
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void urshift32(RegisterID shiftAmount, RegisterID dest)
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{
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urshift32(dest, shiftAmount, dest);
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}
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void urshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
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{
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ARMWord w = ARMAssembler::getOp2Byte(0x1f);
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m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w);
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m_assembler.movs(dest, m_assembler.lsrRegister(src, ARMRegisters::S0));
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}
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void urshift32(TrustedImm32 imm, RegisterID dest)
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{
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m_assembler.movs(dest, m_assembler.lsr(dest, imm.m_value & 0x1f));
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}
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void urshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
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{
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if (!imm.m_value)
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move(src, dest);
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else
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m_assembler.movs(dest, m_assembler.lsr(src, imm.m_value & 0x1f));
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}
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void sub32(RegisterID src, RegisterID dest)
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{
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m_assembler.subs(dest, dest, src);
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}
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void sub32(RegisterID left, RegisterID right, RegisterID dest)
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{
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m_assembler.subs(dest, left, right);
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}
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void sub32(TrustedImm32 imm, RegisterID dest)
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{
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m_assembler.subs(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
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}
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void sub32(TrustedImm32 imm, Address address)
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{
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load32(address, ARMRegisters::S1);
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sub32(imm, ARMRegisters::S1);
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store32(ARMRegisters::S1, address);
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}
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void sub32(Address src, RegisterID dest)
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{
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load32(src, ARMRegisters::S1);
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sub32(ARMRegisters::S1, dest);
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}
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void sub32(RegisterID src, TrustedImm32 imm, RegisterID dest)
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{
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m_assembler.subs(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
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}
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void xor32(RegisterID src, RegisterID dest)
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{
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m_assembler.eors(dest, dest, src);
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}
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void xor32(RegisterID op1, RegisterID op2, RegisterID dest)
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{
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m_assembler.eors(dest, op1, op2);
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}
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void xor32(Address src, RegisterID dest)
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{
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load32(src, ARMRegisters::S1);
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xor32(ARMRegisters::S1, dest);
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}
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void xor32(TrustedImm32 imm, RegisterID dest)
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{
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if (imm.m_value == -1)
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m_assembler.mvns(dest, dest);
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else
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m_assembler.eors(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
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}
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void xor32(TrustedImm32 imm, RegisterID src, RegisterID dest)
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{
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if (imm.m_value == -1)
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m_assembler.mvns(dest, src);
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else
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m_assembler.eors(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
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}
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void countLeadingZeros32(RegisterID src, RegisterID dest)
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{
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#if WTF_ARM_ARCH_AT_LEAST(5)
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m_assembler.clz(dest, src);
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#else
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UNUSED_PARAM(src);
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UNUSED_PARAM(dest);
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RELEASE_ASSERT_NOT_REACHED();
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#endif
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}
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void load8(ImplicitAddress address, RegisterID dest)
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{
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m_assembler.dataTransfer32(ARMAssembler::LoadUint8, dest, address.base, address.offset);
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}
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void load8(BaseIndex address, RegisterID dest)
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{
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m_assembler.baseIndexTransfer32(ARMAssembler::LoadUint8, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
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}
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void load8(const void* address, RegisterID dest)
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{
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move(TrustedImmPtr(address), ARMRegisters::S0);
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m_assembler.dataTransfer32(ARMAssembler::LoadUint8, dest, ARMRegisters::S0, 0);
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}
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void load8SignedExtendTo32(Address address, RegisterID dest)
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{
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m_assembler.dataTransfer16(ARMAssembler::LoadInt8, dest, address.base, address.offset);
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}
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void load8SignedExtendTo32(BaseIndex address, RegisterID dest)
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{
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m_assembler.baseIndexTransfer16(ARMAssembler::LoadInt8, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
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}
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void load16(ImplicitAddress address, RegisterID dest)
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{
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m_assembler.dataTransfer16(ARMAssembler::LoadUint16, dest, address.base, address.offset);
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}
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void load16(BaseIndex address, RegisterID dest)
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{
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m_assembler.baseIndexTransfer16(ARMAssembler::LoadUint16, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
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}
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void load16SignedExtendTo32(BaseIndex address, RegisterID dest)
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{
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m_assembler.baseIndexTransfer16(ARMAssembler::LoadInt16, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
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}
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void load32(ImplicitAddress address, RegisterID dest)
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{
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m_assembler.dataTransfer32(ARMAssembler::LoadUint32, dest, address.base, address.offset);
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}
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void load32(BaseIndex address, RegisterID dest)
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{
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m_assembler.baseIndexTransfer32(ARMAssembler::LoadUint32, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
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}
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#if CPU(ARMV5_OR_LOWER)
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void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest);
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#else
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void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest)
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{
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load32(address, dest);
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}
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#endif
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void load16Unaligned(BaseIndex address, RegisterID dest)
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{
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load16(address, dest);
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}
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void abortWithReason(AbortReason reason)
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{
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move(TrustedImm32(reason), ARMRegisters::S0);
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breakpoint();
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}
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void abortWithReason(AbortReason reason, intptr_t misc)
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{
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move(TrustedImm32(misc), ARMRegisters::S1);
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abortWithReason(reason);
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}
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ConvertibleLoadLabel convertibleLoadPtr(Address address, RegisterID dest)
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{
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ConvertibleLoadLabel result(this);
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ASSERT(address.offset >= 0 && address.offset <= 255);
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m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, address.base, address.offset);
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return result;
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}
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DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest)
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{
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DataLabel32 dataLabel(this);
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m_assembler.ldrUniqueImmediate(ARMRegisters::S0, 0);
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m_assembler.dtrUpRegister(ARMAssembler::LoadUint32, dest, address.base, ARMRegisters::S0);
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return dataLabel;
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}
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static bool isCompactPtrAlignedAddressOffset(ptrdiff_t value)
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{
|
|
return value >= -4095 && value <= 4095;
|
|
}
|
|
|
|
DataLabelCompact load32WithCompactAddressOffsetPatch(Address address, RegisterID dest)
|
|
{
|
|
DataLabelCompact dataLabel(this);
|
|
ASSERT(isCompactPtrAlignedAddressOffset(address.offset));
|
|
if (address.offset >= 0)
|
|
m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, address.base, address.offset);
|
|
else
|
|
m_assembler.dtrDown(ARMAssembler::LoadUint32, dest, address.base, address.offset);
|
|
return dataLabel;
|
|
}
|
|
|
|
DataLabel32 store32WithAddressOffsetPatch(RegisterID src, Address address)
|
|
{
|
|
DataLabel32 dataLabel(this);
|
|
m_assembler.ldrUniqueImmediate(ARMRegisters::S0, 0);
|
|
m_assembler.dtrUpRegister(ARMAssembler::StoreUint32, src, address.base, ARMRegisters::S0);
|
|
return dataLabel;
|
|
}
|
|
|
|
void store8(RegisterID src, BaseIndex address)
|
|
{
|
|
m_assembler.baseIndexTransfer32(ARMAssembler::StoreUint8, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
|
|
}
|
|
|
|
void store8(RegisterID src, ImplicitAddress address)
|
|
{
|
|
m_assembler.dtrUp(ARMAssembler::StoreUint8, src, address.base, address.offset);
|
|
}
|
|
|
|
void store8(RegisterID src, const void* address)
|
|
{
|
|
move(TrustedImmPtr(address), ARMRegisters::S0);
|
|
m_assembler.dtrUp(ARMAssembler::StoreUint8, src, ARMRegisters::S0, 0);
|
|
}
|
|
|
|
void store8(TrustedImm32 imm, ImplicitAddress address)
|
|
{
|
|
TrustedImm32 imm8(static_cast<int8_t>(imm.m_value));
|
|
move(imm8, ARMRegisters::S1);
|
|
store8(ARMRegisters::S1, address);
|
|
}
|
|
|
|
void store8(TrustedImm32 imm, const void* address)
|
|
{
|
|
TrustedImm32 imm8(static_cast<int8_t>(imm.m_value));
|
|
move(TrustedImm32(reinterpret_cast<ARMWord>(address)), ARMRegisters::S0);
|
|
move(imm8, ARMRegisters::S1);
|
|
m_assembler.dtrUp(ARMAssembler::StoreUint8, ARMRegisters::S1, ARMRegisters::S0, 0);
|
|
}
|
|
|
|
void store16(RegisterID src, BaseIndex address)
|
|
{
|
|
m_assembler.baseIndexTransfer16(ARMAssembler::StoreUint16, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
|
|
}
|
|
|
|
void store32(RegisterID src, ImplicitAddress address)
|
|
{
|
|
m_assembler.dataTransfer32(ARMAssembler::StoreUint32, src, address.base, address.offset);
|
|
}
|
|
|
|
void store32(RegisterID src, BaseIndex address)
|
|
{
|
|
m_assembler.baseIndexTransfer32(ARMAssembler::StoreUint32, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
|
|
}
|
|
|
|
void store32(TrustedImm32 imm, ImplicitAddress address)
|
|
{
|
|
move(imm, ARMRegisters::S1);
|
|
store32(ARMRegisters::S1, address);
|
|
}
|
|
|
|
void store32(TrustedImm32 imm, BaseIndex address)
|
|
{
|
|
move(imm, ARMRegisters::S1);
|
|
m_assembler.baseIndexTransfer32(ARMAssembler::StoreUint32, ARMRegisters::S1, address.base, address.index, static_cast<int>(address.scale), address.offset);
|
|
}
|
|
|
|
void store32(RegisterID src, const void* address)
|
|
{
|
|
m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
|
|
m_assembler.dtrUp(ARMAssembler::StoreUint32, src, ARMRegisters::S0, 0);
|
|
}
|
|
|
|
void store32(TrustedImm32 imm, const void* address)
|
|
{
|
|
m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
|
|
m_assembler.moveImm(imm.m_value, ARMRegisters::S1);
|
|
m_assembler.dtrUp(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0);
|
|
}
|
|
|
|
void pop(RegisterID dest)
|
|
{
|
|
m_assembler.pop(dest);
|
|
}
|
|
|
|
void popPair(RegisterID dest1, RegisterID dest2)
|
|
{
|
|
m_assembler.pop(dest1);
|
|
m_assembler.pop(dest2);
|
|
}
|
|
|
|
void push(RegisterID src)
|
|
{
|
|
m_assembler.push(src);
|
|
}
|
|
|
|
void push(Address address)
|
|
{
|
|
load32(address, ARMRegisters::S1);
|
|
push(ARMRegisters::S1);
|
|
}
|
|
|
|
void push(TrustedImm32 imm)
|
|
{
|
|
move(imm, ARMRegisters::S0);
|
|
push(ARMRegisters::S0);
|
|
}
|
|
|
|
void pushPair(RegisterID src1, RegisterID src2)
|
|
{
|
|
m_assembler.push(src2);
|
|
m_assembler.push(src1);
|
|
}
|
|
|
|
void move(TrustedImm32 imm, RegisterID dest)
|
|
{
|
|
m_assembler.moveImm(imm.m_value, dest);
|
|
}
|
|
|
|
void move(RegisterID src, RegisterID dest)
|
|
{
|
|
if (src != dest)
|
|
m_assembler.mov(dest, src);
|
|
}
|
|
|
|
void move(TrustedImmPtr imm, RegisterID dest)
|
|
{
|
|
move(TrustedImm32(imm), dest);
|
|
}
|
|
|
|
void swap(RegisterID reg1, RegisterID reg2)
|
|
{
|
|
xor32(reg1, reg2);
|
|
xor32(reg2, reg1);
|
|
xor32(reg1, reg2);
|
|
}
|
|
|
|
void signExtend32ToPtr(RegisterID src, RegisterID dest)
|
|
{
|
|
if (src != dest)
|
|
move(src, dest);
|
|
}
|
|
|
|
void zeroExtend32ToPtr(RegisterID src, RegisterID dest)
|
|
{
|
|
if (src != dest)
|
|
move(src, dest);
|
|
}
|
|
|
|
Jump branch8(RelationalCondition cond, Address left, TrustedImm32 right)
|
|
{
|
|
TrustedImm32 right8 = MacroAssemblerHelpers::mask8OnCondition(*this, cond, right);
|
|
MacroAssemblerHelpers::load8OnCondition(*this, cond, left, ARMRegisters::S1);
|
|
return branch32(cond, ARMRegisters::S1, right8);
|
|
}
|
|
|
|
Jump branch8(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
|
|
{
|
|
TrustedImm32 right8 = MacroAssemblerHelpers::mask8OnCondition(*this, cond, right);
|
|
MacroAssemblerHelpers::load8OnCondition(*this, cond, left, ARMRegisters::S1);
|
|
return branch32(cond, ARMRegisters::S1, right8);
|
|
}
|
|
|
|
Jump branch8(RelationalCondition cond, AbsoluteAddress left, TrustedImm32 right)
|
|
{
|
|
TrustedImm32 right8 = MacroAssemblerHelpers::mask8OnCondition(*this, cond, right);
|
|
move(TrustedImmPtr(left.m_ptr), ARMRegisters::S1);
|
|
MacroAssemblerHelpers::load8OnCondition(*this, cond, Address(ARMRegisters::S1), ARMRegisters::S1);
|
|
return branch32(cond, ARMRegisters::S1, right8);
|
|
}
|
|
|
|
Jump branchPtr(RelationalCondition cond, BaseIndex left, RegisterID right)
|
|
{
|
|
load32(left, ARMRegisters::S1);
|
|
return branch32(cond, ARMRegisters::S1, right);
|
|
}
|
|
|
|
Jump branch32(RelationalCondition cond, RegisterID left, RegisterID right, int useConstantPool = 0)
|
|
{
|
|
m_assembler.cmp(left, right);
|
|
return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool));
|
|
}
|
|
|
|
Jump branch32(RelationalCondition cond, RegisterID left, TrustedImm32 right, int useConstantPool = 0)
|
|
{
|
|
internalCompare32(left, right);
|
|
return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool));
|
|
}
|
|
|
|
Jump branch32(RelationalCondition cond, RegisterID left, Address right)
|
|
{
|
|
load32(right, ARMRegisters::S1);
|
|
return branch32(cond, left, ARMRegisters::S1);
|
|
}
|
|
|
|
Jump branch32(RelationalCondition cond, Address left, RegisterID right)
|
|
{
|
|
load32(left, ARMRegisters::S1);
|
|
return branch32(cond, ARMRegisters::S1, right);
|
|
}
|
|
|
|
Jump branch32(RelationalCondition cond, Address left, TrustedImm32 right)
|
|
{
|
|
load32(left, ARMRegisters::S1);
|
|
return branch32(cond, ARMRegisters::S1, right);
|
|
}
|
|
|
|
Jump branch32(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
|
|
{
|
|
load32(left, ARMRegisters::S1);
|
|
return branch32(cond, ARMRegisters::S1, right);
|
|
}
|
|
|
|
Jump branch32WithUnalignedHalfWords(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
|
|
{
|
|
load32WithUnalignedHalfWords(left, ARMRegisters::S1);
|
|
return branch32(cond, ARMRegisters::S1, right);
|
|
}
|
|
|
|
Jump branchTest8(ResultCondition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))
|
|
{
|
|
TrustedImm32 mask8 = MacroAssemblerHelpers::mask8OnCondition(*this, cond, mask);
|
|
MacroAssemblerHelpers::load8OnCondition(*this, cond, address, ARMRegisters::S1);
|
|
return branchTest32(cond, ARMRegisters::S1, mask8);
|
|
}
|
|
|
|
Jump branchTest8(ResultCondition cond, BaseIndex address, TrustedImm32 mask = TrustedImm32(-1))
|
|
{
|
|
TrustedImm32 mask8 = MacroAssemblerHelpers::mask8OnCondition(*this, cond, mask);
|
|
MacroAssemblerHelpers::load8OnCondition(*this, cond, address, ARMRegisters::S1);
|
|
return branchTest32(cond, ARMRegisters::S1, mask8);
|
|
}
|
|
|
|
Jump branchTest8(ResultCondition cond, AbsoluteAddress address, TrustedImm32 mask = TrustedImm32(-1))
|
|
{
|
|
TrustedImm32 mask8 = MacroAssemblerHelpers::mask8OnCondition(*this, cond, mask);
|
|
move(TrustedImmPtr(address.m_ptr), ARMRegisters::S1);
|
|
MacroAssemblerHelpers::load8OnCondition(*this, cond, Address(ARMRegisters::S1), ARMRegisters::S1);
|
|
return branchTest32(cond, ARMRegisters::S1, mask8);
|
|
}
|
|
|
|
Jump branchTest32(ResultCondition cond, RegisterID reg, RegisterID mask)
|
|
{
|
|
ASSERT(cond == Zero || cond == NonZero || cond == Signed || cond == PositiveOrZero);
|
|
m_assembler.tst(reg, mask);
|
|
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
|
}
|
|
|
|
Jump branchTest32(ResultCondition cond, RegisterID reg, TrustedImm32 mask = TrustedImm32(-1))
|
|
{
|
|
ASSERT(cond == Zero || cond == NonZero || cond == Signed || cond == PositiveOrZero);
|
|
ARMWord w = m_assembler.getImm(mask.m_value, ARMRegisters::S0, true);
|
|
if (w & ARMAssembler::Op2InvertedImmediate)
|
|
m_assembler.bics(ARMRegisters::S0, reg, w & ~ARMAssembler::Op2InvertedImmediate);
|
|
else
|
|
m_assembler.tst(reg, w);
|
|
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
|
}
|
|
|
|
Jump branchTest32(ResultCondition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))
|
|
{
|
|
load32(address, ARMRegisters::S1);
|
|
return branchTest32(cond, ARMRegisters::S1, mask);
|
|
}
|
|
|
|
Jump branchTest32(ResultCondition cond, BaseIndex address, TrustedImm32 mask = TrustedImm32(-1))
|
|
{
|
|
load32(address, ARMRegisters::S1);
|
|
return branchTest32(cond, ARMRegisters::S1, mask);
|
|
}
|
|
|
|
Jump jump()
|
|
{
|
|
return Jump(m_assembler.jmp());
|
|
}
|
|
|
|
void jump(RegisterID target)
|
|
{
|
|
m_assembler.bx(target);
|
|
}
|
|
|
|
void jump(Address address)
|
|
{
|
|
load32(address, ARMRegisters::pc);
|
|
}
|
|
|
|
void jump(AbsoluteAddress address)
|
|
{
|
|
move(TrustedImmPtr(address.m_ptr), ARMRegisters::S0);
|
|
load32(Address(ARMRegisters::S0, 0), ARMRegisters::pc);
|
|
}
|
|
|
|
void moveDoubleToInts(FPRegisterID src, RegisterID dest1, RegisterID dest2)
|
|
{
|
|
m_assembler.vmov(dest1, dest2, src);
|
|
}
|
|
|
|
void moveIntsToDouble(RegisterID src1, RegisterID src2, FPRegisterID dest, FPRegisterID)
|
|
{
|
|
m_assembler.vmov(dest, src1, src2);
|
|
}
|
|
|
|
Jump branchAdd32(ResultCondition cond, RegisterID src, RegisterID dest)
|
|
{
|
|
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
|
|
|| (cond == NonZero) || (cond == PositiveOrZero));
|
|
add32(src, dest);
|
|
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
|
}
|
|
|
|
Jump branchAdd32(ResultCondition cond, RegisterID op1, RegisterID op2, RegisterID dest)
|
|
{
|
|
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
|
|
|| (cond == NonZero) || (cond == PositiveOrZero));
|
|
add32(op1, op2, dest);
|
|
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
|
}
|
|
|
|
Jump branchAdd32(ResultCondition cond, TrustedImm32 imm, RegisterID dest)
|
|
{
|
|
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
|
|
|| (cond == NonZero) || (cond == PositiveOrZero));
|
|
add32(imm, dest);
|
|
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
|
}
|
|
|
|
Jump branchAdd32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest)
|
|
{
|
|
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
|
|
|| (cond == NonZero) || (cond == PositiveOrZero));
|
|
add32(src, imm, dest);
|
|
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
|
}
|
|
|
|
Jump branchAdd32(ResultCondition cond, TrustedImm32 imm, AbsoluteAddress dest)
|
|
{
|
|
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
|
|
|| (cond == NonZero) || (cond == PositiveOrZero));
|
|
add32(imm, dest);
|
|
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
|
}
|
|
|
|
Jump branchAdd32(ResultCondition cond, Address src, RegisterID dest)
|
|
{
|
|
load32(src, ARMRegisters::S0);
|
|
return branchAdd32(cond, dest, ARMRegisters::S0, dest);
|
|
}
|
|
void mull32(RegisterID op1, RegisterID op2, RegisterID dest)
|
|
{
|
|
if (op2 == dest) {
|
|
if (op1 == dest) {
|
|
move(op2, ARMRegisters::S0);
|
|
op2 = ARMRegisters::S0;
|
|
} else {
|
|
// Swap the operands.
|
|
RegisterID tmp = op1;
|
|
op1 = op2;
|
|
op2 = tmp;
|
|
}
|
|
}
|
|
m_assembler.mull(ARMRegisters::S1, dest, op1, op2);
|
|
m_assembler.cmp(ARMRegisters::S1, m_assembler.asr(dest, 31));
|
|
}
|
|
|
|
Jump branchMul32(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest)
|
|
{
|
|
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
|
|
if (cond == Overflow) {
|
|
mull32(src1, src2, dest);
|
|
cond = NonZero;
|
|
}
|
|
else
|
|
mul32(src1, src2, dest);
|
|
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
|
}
|
|
|
|
Jump branchMul32(ResultCondition cond, RegisterID src, RegisterID dest)
|
|
{
|
|
return branchMul32(cond, src, dest, dest);
|
|
}
|
|
|
|
Jump branchMul32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest)
|
|
{
|
|
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
|
|
if (cond == Overflow) {
|
|
move(imm, ARMRegisters::S0);
|
|
mull32(ARMRegisters::S0, src, dest);
|
|
cond = NonZero;
|
|
}
|
|
else
|
|
mul32(imm, src, dest);
|
|
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
|
}
|
|
|
|
Jump branchSub32(ResultCondition cond, RegisterID src, RegisterID dest)
|
|
{
|
|
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
|
|
sub32(src, dest);
|
|
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
|
}
|
|
|
|
Jump branchSub32(ResultCondition cond, TrustedImm32 imm, RegisterID dest)
|
|
{
|
|
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
|
|
sub32(imm, dest);
|
|
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
|
}
|
|
|
|
Jump branchSub32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest)
|
|
{
|
|
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
|
|
sub32(src, imm, dest);
|
|
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
|
}
|
|
|
|
Jump branchSub32(ResultCondition cond, RegisterID op1, RegisterID op2, RegisterID dest)
|
|
{
|
|
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
|
|
m_assembler.subs(dest, op1, op2);
|
|
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
|
}
|
|
|
|
Jump branchNeg32(ResultCondition cond, RegisterID srcDest)
|
|
{
|
|
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
|
|
neg32(srcDest);
|
|
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
|
}
|
|
|
|
Jump branchOr32(ResultCondition cond, RegisterID src, RegisterID dest)
|
|
{
|
|
ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero));
|
|
or32(src, dest);
|
|
return Jump(m_assembler.jmp(ARMCondition(cond)));
|
|
}
|
|
|
|
PatchableJump patchableJump()
|
|
{
|
|
return PatchableJump(m_assembler.jmp(ARMAssembler::AL, 1));
|
|
}
|
|
|
|
PatchableJump patchableBranch32(RelationalCondition cond, RegisterID reg, TrustedImm32 imm)
|
|
{
|
|
internalCompare32(reg, imm);
|
|
Jump jump(m_assembler.loadBranchTarget(ARMRegisters::S1, ARMCondition(cond), true));
|
|
m_assembler.bx(ARMRegisters::S1, ARMCondition(cond));
|
|
return PatchableJump(jump);
|
|
}
|
|
|
|
PatchableJump patchableBranch32(RelationalCondition cond, Address address, TrustedImm32 imm)
|
|
{
|
|
internalCompare32(address, imm);
|
|
Jump jump(m_assembler.loadBranchTarget(ARMRegisters::S1, ARMCondition(cond), false));
|
|
m_assembler.bx(ARMRegisters::S1, ARMCondition(cond));
|
|
return PatchableJump(jump);
|
|
}
|
|
|
|
void breakpoint()
|
|
{
|
|
m_assembler.bkpt(0);
|
|
}
|
|
|
|
static bool isBreakpoint(void* address) { return ARMAssembler::isBkpt(address); }
|
|
|
|
Call nearCall()
|
|
{
|
|
m_assembler.loadBranchTarget(ARMRegisters::S1, ARMAssembler::AL, true);
|
|
return Call(m_assembler.blx(ARMRegisters::S1), Call::LinkableNear);
|
|
}
|
|
|
|
Call nearTailCall()
|
|
{
|
|
return Call(m_assembler.jmp(), Call::LinkableNearTail);
|
|
}
|
|
|
|
Call call(RegisterID target)
|
|
{
|
|
return Call(m_assembler.blx(target), Call::None);
|
|
}
|
|
|
|
void call(Address address)
|
|
{
|
|
call32(address.base, address.offset);
|
|
}
|
|
|
|
void ret()
|
|
{
|
|
m_assembler.bx(linkRegister);
|
|
}
|
|
|
|
void compare32(RelationalCondition cond, RegisterID left, RegisterID right, RegisterID dest)
|
|
{
|
|
m_assembler.cmp(left, right);
|
|
m_assembler.mov(dest, ARMAssembler::getOp2Byte(0));
|
|
m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));
|
|
}
|
|
|
|
void compare32(RelationalCondition cond, RegisterID left, TrustedImm32 right, RegisterID dest)
|
|
{
|
|
m_assembler.cmp(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));
|
|
m_assembler.mov(dest, ARMAssembler::getOp2Byte(0));
|
|
m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));
|
|
}
|
|
|
|
void compare8(RelationalCondition cond, Address left, TrustedImm32 right, RegisterID dest)
|
|
{
|
|
TrustedImm32 right8 = MacroAssemblerHelpers::mask8OnCondition(*this, cond, right);
|
|
MacroAssemblerHelpers::load8OnCondition(*this, cond, left, ARMRegisters::S1);
|
|
compare32(cond, ARMRegisters::S1, right8, dest);
|
|
}
|
|
|
|
void test32(ResultCondition cond, RegisterID reg, TrustedImm32 mask, RegisterID dest)
|
|
{
|
|
if (mask.m_value == -1)
|
|
m_assembler.tst(reg, reg);
|
|
else
|
|
m_assembler.tst(reg, m_assembler.getImm(mask.m_value, ARMRegisters::S0));
|
|
m_assembler.mov(dest, ARMAssembler::getOp2Byte(0));
|
|
m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));
|
|
}
|
|
|
|
void test32(ResultCondition cond, Address address, TrustedImm32 mask, RegisterID dest)
|
|
{
|
|
load32(address, ARMRegisters::S1);
|
|
test32(cond, ARMRegisters::S1, mask, dest);
|
|
}
|
|
|
|
void test8(ResultCondition cond, Address address, TrustedImm32 mask, RegisterID dest)
|
|
{
|
|
TrustedImm32 mask8 = MacroAssemblerHelpers::mask8OnCondition(*this, cond, mask);
|
|
MacroAssemblerHelpers::load8OnCondition(*this, cond, address, ARMRegisters::S1);
|
|
test32(cond, ARMRegisters::S1, mask8, dest);
|
|
}
|
|
|
|
void add32(TrustedImm32 imm, RegisterID src, RegisterID dest)
|
|
{
|
|
m_assembler.add(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
|
|
}
|
|
|
|
void add32(TrustedImm32 imm, AbsoluteAddress address)
|
|
{
|
|
load32(address.m_ptr, ARMRegisters::S1);
|
|
add32(imm, ARMRegisters::S1);
|
|
store32(ARMRegisters::S1, address.m_ptr);
|
|
}
|
|
|
|
void add64(TrustedImm32 imm, AbsoluteAddress address)
|
|
{
|
|
ARMWord tmp;
|
|
|
|
move(TrustedImmPtr(address.m_ptr), ARMRegisters::S1);
|
|
m_assembler.dtrUp(ARMAssembler::LoadUint32, ARMRegisters::S0, ARMRegisters::S1, 0);
|
|
|
|
if ((tmp = ARMAssembler::getOp2(imm.m_value)) != ARMAssembler::InvalidImmediate)
|
|
m_assembler.adds(ARMRegisters::S0, ARMRegisters::S0, tmp);
|
|
else if ((tmp = ARMAssembler::getOp2(-imm.m_value)) != ARMAssembler::InvalidImmediate)
|
|
m_assembler.subs(ARMRegisters::S0, ARMRegisters::S0, tmp);
|
|
else {
|
|
m_assembler.adds(ARMRegisters::S0, ARMRegisters::S0, m_assembler.getImm(imm.m_value, ARMRegisters::S1));
|
|
move(TrustedImmPtr(address.m_ptr), ARMRegisters::S1);
|
|
}
|
|
m_assembler.dtrUp(ARMAssembler::StoreUint32, ARMRegisters::S0, ARMRegisters::S1, 0);
|
|
|
|
m_assembler.dtrUp(ARMAssembler::LoadUint32, ARMRegisters::S0, ARMRegisters::S1, sizeof(ARMWord));
|
|
if (imm.m_value >= 0)
|
|
m_assembler.adc(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
|
|
else
|
|
m_assembler.sbc(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
|
|
m_assembler.dtrUp(ARMAssembler::StoreUint32, ARMRegisters::S0, ARMRegisters::S1, sizeof(ARMWord));
|
|
}
|
|
|
|
void sub32(TrustedImm32 imm, AbsoluteAddress address)
|
|
{
|
|
load32(address.m_ptr, ARMRegisters::S1);
|
|
sub32(imm, ARMRegisters::S1);
|
|
store32(ARMRegisters::S1, address.m_ptr);
|
|
}
|
|
|
|
void load32(const void* address, RegisterID dest)
|
|
{
|
|
m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
|
|
m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, ARMRegisters::S0, 0);
|
|
}
|
|
|
|
Jump branch32(RelationalCondition cond, AbsoluteAddress left, RegisterID right)
|
|
{
|
|
load32(left.m_ptr, ARMRegisters::S1);
|
|
return branch32(cond, ARMRegisters::S1, right);
|
|
}
|
|
|
|
Jump branch32(RelationalCondition cond, AbsoluteAddress left, TrustedImm32 right)
|
|
{
|
|
load32(left.m_ptr, ARMRegisters::S1);
|
|
return branch32(cond, ARMRegisters::S1, right);
|
|
}
|
|
|
|
void relativeTableJump(RegisterID index, int scale)
|
|
{
|
|
ASSERT(scale >= 0 && scale <= 31);
|
|
m_assembler.add(ARMRegisters::pc, ARMRegisters::pc, m_assembler.lsl(index, scale));
|
|
|
|
// NOP the default prefetching
|
|
m_assembler.mov(ARMRegisters::r0, ARMRegisters::r0);
|
|
}
|
|
|
|
Call call()
|
|
{
|
|
ensureSpace(2 * sizeof(ARMWord), sizeof(ARMWord));
|
|
m_assembler.loadBranchTarget(ARMRegisters::S1, ARMAssembler::AL, true);
|
|
return Call(m_assembler.blx(ARMRegisters::S1), Call::Linkable);
|
|
}
|
|
|
|
Call tailRecursiveCall()
|
|
{
|
|
return Call::fromTailJump(jump());
|
|
}
|
|
|
|
Call makeTailRecursiveCall(Jump oldJump)
|
|
{
|
|
return Call::fromTailJump(oldJump);
|
|
}
|
|
|
|
DataLabelPtr moveWithPatch(TrustedImmPtr initialValue, RegisterID dest)
|
|
{
|
|
DataLabelPtr dataLabel(this);
|
|
m_assembler.ldrUniqueImmediate(dest, reinterpret_cast<ARMWord>(initialValue.m_value));
|
|
return dataLabel;
|
|
}
|
|
|
|
DataLabel32 moveWithPatch(TrustedImm32 initialValue, RegisterID dest)
|
|
{
|
|
DataLabel32 dataLabel(this);
|
|
m_assembler.ldrUniqueImmediate(dest, static_cast<ARMWord>(initialValue.m_value));
|
|
return dataLabel;
|
|
}
|
|
|
|
Jump branchPtrWithPatch(RelationalCondition cond, RegisterID left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(0))
|
|
{
|
|
ensureSpace(3 * sizeof(ARMWord), 2 * sizeof(ARMWord));
|
|
dataLabel = moveWithPatch(initialRightValue, ARMRegisters::S1);
|
|
Jump jump = branch32(cond, left, ARMRegisters::S1, true);
|
|
return jump;
|
|
}
|
|
|
|
Jump branchPtrWithPatch(RelationalCondition cond, Address left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(0))
|
|
{
|
|
load32(left, ARMRegisters::S1);
|
|
ensureSpace(3 * sizeof(ARMWord), 2 * sizeof(ARMWord));
|
|
dataLabel = moveWithPatch(initialRightValue, ARMRegisters::S0);
|
|
Jump jump = branch32(cond, ARMRegisters::S0, ARMRegisters::S1, true);
|
|
return jump;
|
|
}
|
|
|
|
Jump branch32WithPatch(RelationalCondition cond, Address left, DataLabel32& dataLabel, TrustedImm32 initialRightValue = TrustedImm32(0))
|
|
{
|
|
load32(left, ARMRegisters::S1);
|
|
ensureSpace(3 * sizeof(ARMWord), 2 * sizeof(ARMWord));
|
|
dataLabel = moveWithPatch(initialRightValue, ARMRegisters::S0);
|
|
Jump jump = branch32(cond, ARMRegisters::S0, ARMRegisters::S1, true);
|
|
return jump;
|
|
}
|
|
|
|
DataLabelPtr storePtrWithPatch(TrustedImmPtr initialValue, ImplicitAddress address)
|
|
{
|
|
DataLabelPtr dataLabel = moveWithPatch(initialValue, ARMRegisters::S1);
|
|
store32(ARMRegisters::S1, address);
|
|
return dataLabel;
|
|
}
|
|
|
|
DataLabelPtr storePtrWithPatch(ImplicitAddress address)
|
|
{
|
|
return storePtrWithPatch(TrustedImmPtr(0), address);
|
|
}
|
|
|
|
// Floating point operators
|
|
static bool supportsFloatingPoint()
|
|
{
|
|
return s_isVFPPresent;
|
|
}
|
|
|
|
static bool supportsFloatingPointTruncate()
|
|
{
|
|
return false;
|
|
}
|
|
|
|
static bool supportsFloatingPointSqrt()
|
|
{
|
|
return s_isVFPPresent;
|
|
}
|
|
static bool supportsFloatingPointAbs() { return false; }
|
|
static bool supportsFloatingPointRounding() { return false; }
|
|
|
|
|
|
void loadFloat(ImplicitAddress address, FPRegisterID dest)
|
|
{
|
|
m_assembler.dataTransferFloat(ARMAssembler::LoadFloat, dest, address.base, address.offset);
|
|
}
|
|
|
|
void loadFloat(BaseIndex address, FPRegisterID dest)
|
|
{
|
|
m_assembler.baseIndexTransferFloat(ARMAssembler::LoadFloat, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
|
|
}
|
|
|
|
void loadDouble(ImplicitAddress address, FPRegisterID dest)
|
|
{
|
|
m_assembler.dataTransferFloat(ARMAssembler::LoadDouble, dest, address.base, address.offset);
|
|
}
|
|
|
|
void loadDouble(BaseIndex address, FPRegisterID dest)
|
|
{
|
|
m_assembler.baseIndexTransferFloat(ARMAssembler::LoadDouble, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
|
|
}
|
|
|
|
void loadDouble(TrustedImmPtr address, FPRegisterID dest)
|
|
{
|
|
move(TrustedImm32(reinterpret_cast<ARMWord>(address.m_value)), ARMRegisters::S0);
|
|
m_assembler.doubleDtrUp(ARMAssembler::LoadDouble, dest, ARMRegisters::S0, 0);
|
|
}
|
|
|
|
NO_RETURN_DUE_TO_CRASH void ceilDouble(FPRegisterID, FPRegisterID)
|
|
{
|
|
ASSERT(!supportsFloatingPointRounding());
|
|
CRASH();
|
|
}
|
|
|
|
NO_RETURN_DUE_TO_CRASH void floorDouble(FPRegisterID, FPRegisterID)
|
|
{
|
|
ASSERT(!supportsFloatingPointRounding());
|
|
CRASH();
|
|
}
|
|
|
|
NO_RETURN_DUE_TO_CRASH void roundTowardZeroDouble(FPRegisterID, FPRegisterID)
|
|
{
|
|
ASSERT(!supportsFloatingPointRounding());
|
|
CRASH();
|
|
}
|
|
|
|
void storeFloat(FPRegisterID src, ImplicitAddress address)
|
|
{
|
|
m_assembler.dataTransferFloat(ARMAssembler::StoreFloat, src, address.base, address.offset);
|
|
}
|
|
|
|
void storeFloat(FPRegisterID src, BaseIndex address)
|
|
{
|
|
m_assembler.baseIndexTransferFloat(ARMAssembler::StoreFloat, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
|
|
}
|
|
|
|
void storeDouble(FPRegisterID src, ImplicitAddress address)
|
|
{
|
|
m_assembler.dataTransferFloat(ARMAssembler::StoreDouble, src, address.base, address.offset);
|
|
}
|
|
|
|
void storeDouble(FPRegisterID src, BaseIndex address)
|
|
{
|
|
m_assembler.baseIndexTransferFloat(ARMAssembler::StoreDouble, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
|
|
}
|
|
|
|
void storeDouble(FPRegisterID src, TrustedImmPtr address)
|
|
{
|
|
move(TrustedImm32(reinterpret_cast<ARMWord>(address.m_value)), ARMRegisters::S0);
|
|
m_assembler.dataTransferFloat(ARMAssembler::StoreDouble, src, ARMRegisters::S0, 0);
|
|
}
|
|
|
|
void moveDouble(FPRegisterID src, FPRegisterID dest)
|
|
{
|
|
if (src != dest)
|
|
m_assembler.vmov_f64(dest, src);
|
|
}
|
|
|
|
void moveZeroToDouble(FPRegisterID reg)
|
|
{
|
|
static double zeroConstant = 0.;
|
|
loadDouble(TrustedImmPtr(&zeroConstant), reg);
|
|
}
|
|
|
|
void addDouble(FPRegisterID src, FPRegisterID dest)
|
|
{
|
|
m_assembler.vadd_f64(dest, dest, src);
|
|
}
|
|
|
|
void addDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
|
|
{
|
|
m_assembler.vadd_f64(dest, op1, op2);
|
|
}
|
|
|
|
void addDouble(Address src, FPRegisterID dest)
|
|
{
|
|
loadDouble(src, ARMRegisters::SD0);
|
|
addDouble(ARMRegisters::SD0, dest);
|
|
}
|
|
|
|
void addDouble(AbsoluteAddress address, FPRegisterID dest)
|
|
{
|
|
loadDouble(TrustedImmPtr(address.m_ptr), ARMRegisters::SD0);
|
|
addDouble(ARMRegisters::SD0, dest);
|
|
}
|
|
|
|
void divDouble(FPRegisterID src, FPRegisterID dest)
|
|
{
|
|
m_assembler.vdiv_f64(dest, dest, src);
|
|
}
|
|
|
|
void divDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
|
|
{
|
|
m_assembler.vdiv_f64(dest, op1, op2);
|
|
}
|
|
|
|
void divDouble(Address src, FPRegisterID dest)
|
|
{
|
|
RELEASE_ASSERT_NOT_REACHED(); // Untested
|
|
loadDouble(src, ARMRegisters::SD0);
|
|
divDouble(ARMRegisters::SD0, dest);
|
|
}
|
|
|
|
void subDouble(FPRegisterID src, FPRegisterID dest)
|
|
{
|
|
m_assembler.vsub_f64(dest, dest, src);
|
|
}
|
|
|
|
void subDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
|
|
{
|
|
m_assembler.vsub_f64(dest, op1, op2);
|
|
}
|
|
|
|
void subDouble(Address src, FPRegisterID dest)
|
|
{
|
|
loadDouble(src, ARMRegisters::SD0);
|
|
subDouble(ARMRegisters::SD0, dest);
|
|
}
|
|
|
|
void mulDouble(FPRegisterID src, FPRegisterID dest)
|
|
{
|
|
m_assembler.vmul_f64(dest, dest, src);
|
|
}
|
|
|
|
void mulDouble(Address src, FPRegisterID dest)
|
|
{
|
|
loadDouble(src, ARMRegisters::SD0);
|
|
mulDouble(ARMRegisters::SD0, dest);
|
|
}
|
|
|
|
void mulDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
|
|
{
|
|
m_assembler.vmul_f64(dest, op1, op2);
|
|
}
|
|
|
|
void sqrtDouble(FPRegisterID src, FPRegisterID dest)
|
|
{
|
|
m_assembler.vsqrt_f64(dest, src);
|
|
}
|
|
|
|
void absDouble(FPRegisterID src, FPRegisterID dest)
|
|
{
|
|
m_assembler.vabs_f64(dest, src);
|
|
}
|
|
|
|
void negateDouble(FPRegisterID src, FPRegisterID dest)
|
|
{
|
|
m_assembler.vneg_f64(dest, src);
|
|
}
|
|
|
|
void convertInt32ToDouble(RegisterID src, FPRegisterID dest)
|
|
{
|
|
m_assembler.vmov_vfp32(dest << 1, src);
|
|
m_assembler.vcvt_f64_s32(dest, dest << 1);
|
|
}
|
|
|
|
void convertInt32ToDouble(Address src, FPRegisterID dest)
|
|
{
|
|
load32(src, ARMRegisters::S1);
|
|
convertInt32ToDouble(ARMRegisters::S1, dest);
|
|
}
|
|
|
|
void convertInt32ToDouble(AbsoluteAddress src, FPRegisterID dest)
|
|
{
|
|
move(TrustedImmPtr(src.m_ptr), ARMRegisters::S1);
|
|
load32(Address(ARMRegisters::S1), ARMRegisters::S1);
|
|
convertInt32ToDouble(ARMRegisters::S1, dest);
|
|
}
|
|
|
|
void convertFloatToDouble(FPRegisterID src, FPRegisterID dst)
|
|
{
|
|
m_assembler.vcvt_f64_f32(dst, src);
|
|
}
|
|
|
|
void convertDoubleToFloat(FPRegisterID src, FPRegisterID dst)
|
|
{
|
|
m_assembler.vcvt_f32_f64(dst, src);
|
|
}
|
|
|
|
Jump branchDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right)
|
|
{
|
|
m_assembler.vcmp_f64(left, right);
|
|
m_assembler.vmrs_apsr();
|
|
if (cond & DoubleConditionBitSpecial)
|
|
m_assembler.cmp(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::VS);
|
|
return Jump(m_assembler.jmp(static_cast<ARMAssembler::Condition>(cond & ~DoubleConditionMask)));
|
|
}
|
|
|
|
// Truncates 'src' to an integer, and places the resulting 'dest'.
|
|
// If the result is not representable as a 32 bit value, branch.
|
|
// May also branch for some values that are representable in 32 bits
|
|
// (specifically, in this case, INT_MIN).
|
|
enum BranchTruncateType { BranchIfTruncateFailed, BranchIfTruncateSuccessful };
|
|
Jump branchTruncateDoubleToInt32(FPRegisterID src, RegisterID dest, BranchTruncateType branchType = BranchIfTruncateFailed)
|
|
{
|
|
truncateDoubleToInt32(src, dest);
|
|
|
|
m_assembler.add(ARMRegisters::S0, dest, ARMAssembler::getOp2Byte(1));
|
|
m_assembler.bic(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(1));
|
|
|
|
ARMWord w = ARMAssembler::getOp2(0x80000000);
|
|
ASSERT(w != ARMAssembler::InvalidImmediate);
|
|
m_assembler.cmp(ARMRegisters::S0, w);
|
|
return Jump(m_assembler.jmp(branchType == BranchIfTruncateFailed ? ARMAssembler::EQ : ARMAssembler::NE));
|
|
}
|
|
|
|
Jump branchTruncateDoubleToUint32(FPRegisterID src, RegisterID dest, BranchTruncateType branchType = BranchIfTruncateFailed)
|
|
{
|
|
truncateDoubleToUint32(src, dest);
|
|
|
|
m_assembler.add(ARMRegisters::S0, dest, ARMAssembler::getOp2Byte(1));
|
|
m_assembler.bic(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(1));
|
|
|
|
m_assembler.cmp(ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
|
|
return Jump(m_assembler.jmp(branchType == BranchIfTruncateFailed ? ARMAssembler::EQ : ARMAssembler::NE));
|
|
}
|
|
|
|
// Result is undefined if the value is outside of the integer range.
|
|
void truncateDoubleToInt32(FPRegisterID src, RegisterID dest)
|
|
{
|
|
m_assembler.vcvt_s32_f64(ARMRegisters::SD0 << 1, src);
|
|
m_assembler.vmov_arm32(dest, ARMRegisters::SD0 << 1);
|
|
}
|
|
|
|
void truncateDoubleToUint32(FPRegisterID src, RegisterID dest)
|
|
{
|
|
m_assembler.vcvt_u32_f64(ARMRegisters::SD0 << 1, src);
|
|
m_assembler.vmov_arm32(dest, ARMRegisters::SD0 << 1);
|
|
}
|
|
|
|
// Convert 'src' to an integer, and places the resulting 'dest'.
|
|
// If the result is not representable as a 32 bit value, branch.
|
|
// May also branch for some values that are representable in 32 bits
|
|
// (specifically, in this case, 0).
|
|
void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID, bool negZeroCheck = true)
|
|
{
|
|
m_assembler.vcvt_s32_f64(ARMRegisters::SD0 << 1, src);
|
|
m_assembler.vmov_arm32(dest, ARMRegisters::SD0 << 1);
|
|
|
|
// Convert the integer result back to float & compare to the original value - if not equal or unordered (NaN) then jump.
|
|
m_assembler.vcvt_f64_s32(ARMRegisters::SD0, ARMRegisters::SD0 << 1);
|
|
failureCases.append(branchDouble(DoubleNotEqualOrUnordered, src, ARMRegisters::SD0));
|
|
|
|
// If the result is zero, it might have been -0.0, and 0.0 equals to -0.0
|
|
if (negZeroCheck)
|
|
failureCases.append(branchTest32(Zero, dest));
|
|
}
|
|
|
|
Jump branchDoubleNonZero(FPRegisterID reg, FPRegisterID scratch)
|
|
{
|
|
m_assembler.mov(ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
|
|
convertInt32ToDouble(ARMRegisters::S0, scratch);
|
|
return branchDouble(DoubleNotEqual, reg, scratch);
|
|
}
|
|
|
|
Jump branchDoubleZeroOrNaN(FPRegisterID reg, FPRegisterID scratch)
|
|
{
|
|
m_assembler.mov(ARMRegisters::S0, ARMAssembler::getOp2Byte(0));
|
|
convertInt32ToDouble(ARMRegisters::S0, scratch);
|
|
return branchDouble(DoubleEqualOrUnordered, reg, scratch);
|
|
}
|
|
|
|
// Invert a relational condition, e.g. == becomes !=, < becomes >=, etc.
|
|
static RelationalCondition invert(RelationalCondition cond)
|
|
{
|
|
ASSERT((static_cast<uint32_t>(cond & 0x0fffffff)) == 0 && static_cast<uint32_t>(cond) < static_cast<uint32_t>(ARMAssembler::AL));
|
|
return static_cast<RelationalCondition>(cond ^ 0x10000000);
|
|
}
|
|
|
|
void nop()
|
|
{
|
|
m_assembler.nop();
|
|
}
|
|
|
|
void memoryFence()
|
|
{
|
|
m_assembler.dmbSY();
|
|
}
|
|
|
|
void storeFence()
|
|
{
|
|
m_assembler.dmbISHST();
|
|
}
|
|
|
|
static FunctionPtr readCallTarget(CodeLocationCall call)
|
|
{
|
|
return FunctionPtr(reinterpret_cast<void(*)()>(ARMAssembler::readCallTarget(call.dataLocation())));
|
|
}
|
|
|
|
static void replaceWithJump(CodeLocationLabel instructionStart, CodeLocationLabel destination)
|
|
{
|
|
ARMAssembler::replaceWithJump(instructionStart.dataLocation(), destination.dataLocation());
|
|
}
|
|
|
|
static ptrdiff_t maxJumpReplacementSize()
|
|
{
|
|
return ARMAssembler::maxJumpReplacementSize();
|
|
}
|
|
|
|
static ptrdiff_t patchableJumpSize()
|
|
{
|
|
return ARMAssembler::patchableJumpSize();
|
|
}
|
|
|
|
static bool canJumpReplacePatchableBranchPtrWithPatch() { return false; }
|
|
static bool canJumpReplacePatchableBranch32WithPatch() { return false; }
|
|
|
|
static CodeLocationLabel startOfPatchableBranch32WithPatchOnAddress(CodeLocationDataLabel32)
|
|
{
|
|
UNREACHABLE_FOR_PLATFORM();
|
|
return CodeLocationLabel();
|
|
}
|
|
|
|
static CodeLocationLabel startOfPatchableBranchPtrWithPatchOnAddress(CodeLocationDataLabelPtr)
|
|
{
|
|
UNREACHABLE_FOR_PLATFORM();
|
|
return CodeLocationLabel();
|
|
}
|
|
|
|
static CodeLocationLabel startOfBranchPtrWithPatchOnRegister(CodeLocationDataLabelPtr label)
|
|
{
|
|
return label.labelAtOffset(0);
|
|
}
|
|
|
|
static void revertJumpReplacementToBranchPtrWithPatch(CodeLocationLabel instructionStart, RegisterID reg, void* initialValue)
|
|
{
|
|
ARMAssembler::revertBranchPtrWithPatch(instructionStart.dataLocation(), reg, reinterpret_cast<uintptr_t>(initialValue) & 0xffff);
|
|
}
|
|
|
|
static void revertJumpReplacementToPatchableBranch32WithPatch(CodeLocationLabel, Address, int32_t)
|
|
{
|
|
UNREACHABLE_FOR_PLATFORM();
|
|
}
|
|
|
|
static void revertJumpReplacementToPatchableBranchPtrWithPatch(CodeLocationLabel, Address, void*)
|
|
{
|
|
UNREACHABLE_FOR_PLATFORM();
|
|
}
|
|
|
|
static void repatchCall(CodeLocationCall call, CodeLocationLabel destination)
|
|
{
|
|
ARMAssembler::relinkCall(call.dataLocation(), destination.executableAddress());
|
|
}
|
|
|
|
static void repatchCall(CodeLocationCall call, FunctionPtr destination)
|
|
{
|
|
ARMAssembler::relinkCall(call.dataLocation(), destination.executableAddress());
|
|
}
|
|
|
|
protected:
|
|
ARMAssembler::Condition ARMCondition(RelationalCondition cond)
|
|
{
|
|
return static_cast<ARMAssembler::Condition>(cond);
|
|
}
|
|
|
|
ARMAssembler::Condition ARMCondition(ResultCondition cond)
|
|
{
|
|
return static_cast<ARMAssembler::Condition>(cond);
|
|
}
|
|
|
|
void ensureSpace(int insnSpace, int constSpace)
|
|
{
|
|
m_assembler.ensureSpace(insnSpace, constSpace);
|
|
}
|
|
|
|
int sizeOfConstantPool()
|
|
{
|
|
return m_assembler.sizeOfConstantPool();
|
|
}
|
|
|
|
void call32(RegisterID base, int32_t offset)
|
|
{
|
|
load32(Address(base, offset), ARMRegisters::S1);
|
|
m_assembler.blx(ARMRegisters::S1);
|
|
}
|
|
|
|
#if ENABLE(MASM_PROBE)
|
|
inline TrustedImm32 trustedImm32FromPtr(void* ptr)
|
|
{
|
|
return TrustedImm32(TrustedImmPtr(ptr));
|
|
}
|
|
|
|
inline TrustedImm32 trustedImm32FromPtr(ProbeFunction function)
|
|
{
|
|
return TrustedImm32(TrustedImmPtr(reinterpret_cast<void*>(function)));
|
|
}
|
|
|
|
inline TrustedImm32 trustedImm32FromPtr(void (*function)())
|
|
{
|
|
return TrustedImm32(TrustedImmPtr(reinterpret_cast<void*>(function)));
|
|
}
|
|
#endif
|
|
|
|
private:
|
|
friend class LinkBuffer;
|
|
|
|
void internalCompare32(RegisterID left, TrustedImm32 right)
|
|
{
|
|
ARMWord tmp = (!right.m_value || static_cast<unsigned>(right.m_value) == 0x80000000) ? ARMAssembler::InvalidImmediate : m_assembler.getOp2(-right.m_value);
|
|
if (tmp != ARMAssembler::InvalidImmediate)
|
|
m_assembler.cmn(left, tmp);
|
|
else
|
|
m_assembler.cmp(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));
|
|
}
|
|
|
|
void internalCompare32(Address left, TrustedImm32 right)
|
|
{
|
|
ARMWord tmp = (!right.m_value || static_cast<unsigned>(right.m_value) == 0x80000000) ? ARMAssembler::InvalidImmediate : m_assembler.getOp2(-right.m_value);
|
|
load32(left, ARMRegisters::S1);
|
|
if (tmp != ARMAssembler::InvalidImmediate)
|
|
m_assembler.cmn(ARMRegisters::S1, tmp);
|
|
else
|
|
m_assembler.cmp(ARMRegisters::S1, m_assembler.getImm(right.m_value, ARMRegisters::S0));
|
|
}
|
|
|
|
static void linkCall(void* code, Call call, FunctionPtr function)
|
|
{
|
|
if (call.isFlagSet(Call::Tail))
|
|
ARMAssembler::linkJump(code, call.m_label, function.value());
|
|
else
|
|
ARMAssembler::linkCall(code, call.m_label, function.value());
|
|
}
|
|
|
|
static const bool s_isVFPPresent;
|
|
};
|
|
|
|
} // namespace JSC
|
|
|
|
#endif // ENABLE(ASSEMBLER) && CPU(ARM_TRADITIONAL)
|