2007-06-28 14:29:56 +00:00
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// i386 register table.
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2009-09-02 07:25:43 +00:00
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// Copyright 2007, 2008
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2007-07-05 09:49:03 +00:00
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// Free Software Foundation, Inc.
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//
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// This file is part of the GNU opcodes library.
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//
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// This library is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 3, or (at your option)
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// any later version.
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//
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// It is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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// License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with GAS; see the file COPYING. If not, write to the Free
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// Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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// 02110-1301, USA.
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2007-06-28 14:29:56 +00:00
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// Make %st first as we test for it.
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2008-02-13 10:14:40 +00:00
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st, FloatReg|FloatAcc, 0, 0, 11, 33
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2007-06-28 14:29:56 +00:00
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// 8 bit regs
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2008-02-13 10:14:40 +00:00
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al, Reg8|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval
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cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval
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dl, Reg8, 0, 2, Dw2Inval, Dw2Inval
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bl, Reg8, 0, 3, Dw2Inval, Dw2Inval
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ah, Reg8, 0, 4, Dw2Inval, Dw2Inval
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ch, Reg8, 0, 5, Dw2Inval, Dw2Inval
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dh, Reg8, 0, 6, Dw2Inval, Dw2Inval
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bh, Reg8, 0, 7, Dw2Inval, Dw2Inval
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axl, Reg8|Acc|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
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cxl, Reg8, RegRex64, 1, Dw2Inval, Dw2Inval
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dxl, Reg8, RegRex64, 2, Dw2Inval, Dw2Inval
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bxl, Reg8, RegRex64, 3, Dw2Inval, Dw2Inval
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spl, Reg8, RegRex64, 4, Dw2Inval, Dw2Inval
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bpl, Reg8, RegRex64, 5, Dw2Inval, Dw2Inval
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sil, Reg8, RegRex64, 6, Dw2Inval, Dw2Inval
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dil, Reg8, RegRex64, 7, Dw2Inval, Dw2Inval
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r8b, Reg8, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval
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r9b, Reg8, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval
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r10b, Reg8, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval
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r11b, Reg8, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval
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r12b, Reg8, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval
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r13b, Reg8, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
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r14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
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r15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
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2007-06-28 14:29:56 +00:00
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// 16 bit regs
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2008-02-13 10:14:40 +00:00
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ax, Reg16|Acc|Word, 0, 0, Dw2Inval, Dw2Inval
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cx, Reg16, 0, 1, Dw2Inval, Dw2Inval
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dx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval
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bx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
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sp, Reg16, 0, 4, Dw2Inval, Dw2Inval
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bp, Reg16|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
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si, Reg16|BaseIndex, 0, 6, Dw2Inval, Dw2Inval
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di, Reg16|BaseIndex, 0, 7, Dw2Inval, Dw2Inval
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r8w, Reg16, RegRex, 0, Dw2Inval, Dw2Inval
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r9w, Reg16, RegRex, 1, Dw2Inval, Dw2Inval
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r10w, Reg16, RegRex, 2, Dw2Inval, Dw2Inval
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r11w, Reg16, RegRex, 3, Dw2Inval, Dw2Inval
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r12w, Reg16, RegRex, 4, Dw2Inval, Dw2Inval
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r13w, Reg16, RegRex, 5, Dw2Inval, Dw2Inval
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r14w, Reg16, RegRex, 6, Dw2Inval, Dw2Inval
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r15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval
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2007-06-28 14:29:56 +00:00
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// 32 bit regs
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2008-02-13 10:14:40 +00:00
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eax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Inval
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ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval
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edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval
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ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval
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esp, Reg32, 0, 4, 4, Dw2Inval
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ebp, Reg32|BaseIndex, 0, 5, 5, Dw2Inval
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esi, Reg32|BaseIndex, 0, 6, 6, Dw2Inval
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edi, Reg32|BaseIndex, 0, 7, 7, Dw2Inval
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r8d, Reg32|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
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r9d, Reg32|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
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r10d, Reg32|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval
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r11d, Reg32|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval
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r12d, Reg32|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
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r13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
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r14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
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r15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
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rax, Reg64|BaseIndex|Acc|Qword, 0, 0, Dw2Inval, 0
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rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2
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rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1
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rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3
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rsp, Reg64, 0, 4, Dw2Inval, 7
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rbp, Reg64|BaseIndex, 0, 5, Dw2Inval, 6
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rsi, Reg64|BaseIndex, 0, 6, Dw2Inval, 4
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rdi, Reg64|BaseIndex, 0, 7, Dw2Inval, 5
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r8, Reg64|BaseIndex, RegRex, 0, Dw2Inval, 8
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r9, Reg64|BaseIndex, RegRex, 1, Dw2Inval, 9
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r10, Reg64|BaseIndex, RegRex, 2, Dw2Inval, 10
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r11, Reg64|BaseIndex, RegRex, 3, Dw2Inval, 11
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r12, Reg64|BaseIndex, RegRex, 4, Dw2Inval, 12
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r13, Reg64|BaseIndex, RegRex, 5, Dw2Inval, 13
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r14, Reg64|BaseIndex, RegRex, 6, Dw2Inval, 14
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r15, Reg64|BaseIndex, RegRex, 7, Dw2Inval, 15
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2007-06-29 20:07:53 +00:00
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// Segment registers.
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2008-02-13 10:14:40 +00:00
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es, SReg2, 0, 0, 40, 50
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cs, SReg2, 0, 1, 41, 51
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ss, SReg2, 0, 2, 42, 52
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ds, SReg2, 0, 3, 43, 53
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fs, SReg3, 0, 4, 44, 54
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gs, SReg3, 0, 5, 45, 55
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2008-02-13 13:41:26 +00:00
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flat, SReg3, 0, RegFlat, Dw2Inval, Dw2Inval
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2007-06-28 14:29:56 +00:00
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// Control registers.
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2008-02-13 10:14:40 +00:00
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cr0, Control, 0, 0, Dw2Inval, Dw2Inval
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cr1, Control, 0, 1, Dw2Inval, Dw2Inval
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cr2, Control, 0, 2, Dw2Inval, Dw2Inval
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cr3, Control, 0, 3, Dw2Inval, Dw2Inval
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cr4, Control, 0, 4, Dw2Inval, Dw2Inval
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cr5, Control, 0, 5, Dw2Inval, Dw2Inval
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cr6, Control, 0, 6, Dw2Inval, Dw2Inval
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cr7, Control, 0, 7, Dw2Inval, Dw2Inval
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cr8, Control, RegRex, 0, Dw2Inval, Dw2Inval
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cr9, Control, RegRex, 1, Dw2Inval, Dw2Inval
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cr10, Control, RegRex, 2, Dw2Inval, Dw2Inval
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cr11, Control, RegRex, 3, Dw2Inval, Dw2Inval
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cr12, Control, RegRex, 4, Dw2Inval, Dw2Inval
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cr13, Control, RegRex, 5, Dw2Inval, Dw2Inval
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cr14, Control, RegRex, 6, Dw2Inval, Dw2Inval
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cr15, Control, RegRex, 7, Dw2Inval, Dw2Inval
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2007-06-28 14:29:56 +00:00
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// Debug registers.
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2008-02-13 10:14:40 +00:00
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db0, Debug, 0, 0, Dw2Inval, Dw2Inval
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db1, Debug, 0, 1, Dw2Inval, Dw2Inval
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db2, Debug, 0, 2, Dw2Inval, Dw2Inval
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db3, Debug, 0, 3, Dw2Inval, Dw2Inval
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db4, Debug, 0, 4, Dw2Inval, Dw2Inval
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db5, Debug, 0, 5, Dw2Inval, Dw2Inval
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db6, Debug, 0, 6, Dw2Inval, Dw2Inval
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db7, Debug, 0, 7, Dw2Inval, Dw2Inval
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db8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
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db9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
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db10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
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db11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
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db12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
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db13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
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db14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
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db15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
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dr0, Debug, 0, 0, Dw2Inval, Dw2Inval
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dr1, Debug, 0, 1, Dw2Inval, Dw2Inval
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dr2, Debug, 0, 2, Dw2Inval, Dw2Inval
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dr3, Debug, 0, 3, Dw2Inval, Dw2Inval
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dr4, Debug, 0, 4, Dw2Inval, Dw2Inval
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dr5, Debug, 0, 5, Dw2Inval, Dw2Inval
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dr6, Debug, 0, 6, Dw2Inval, Dw2Inval
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dr7, Debug, 0, 7, Dw2Inval, Dw2Inval
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dr8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
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dr9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
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dr10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
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dr11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
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dr12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
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dr13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
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dr14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
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dr15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
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2007-06-28 14:29:56 +00:00
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// Test registers.
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2008-02-13 10:14:40 +00:00
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tr0, Test, 0, 0, Dw2Inval, Dw2Inval
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tr1, Test, 0, 1, Dw2Inval, Dw2Inval
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tr2, Test, 0, 2, Dw2Inval, Dw2Inval
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tr3, Test, 0, 3, Dw2Inval, Dw2Inval
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tr4, Test, 0, 4, Dw2Inval, Dw2Inval
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tr5, Test, 0, 5, Dw2Inval, Dw2Inval
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tr6, Test, 0, 6, Dw2Inval, Dw2Inval
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tr7, Test, 0, 7, Dw2Inval, Dw2Inval
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2007-06-28 14:29:56 +00:00
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// MMX and simd registers.
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2008-02-13 10:14:40 +00:00
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mm0, RegMMX, 0, 0, 29, 41
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mm1, RegMMX, 0, 1, 30, 42
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mm2, RegMMX, 0, 2, 31, 43
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mm3, RegMMX, 0, 3, 32, 44
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mm4, RegMMX, 0, 4, 33, 45
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mm5, RegMMX, 0, 5, 34, 46
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mm6, RegMMX, 0, 6, 35, 47
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mm7, RegMMX, 0, 7, 36, 48
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xmm0, RegXMM, 0, 0, 21, 17
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xmm1, RegXMM, 0, 1, 22, 18
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xmm2, RegXMM, 0, 2, 23, 19
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xmm3, RegXMM, 0, 3, 24, 20
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xmm4, RegXMM, 0, 4, 25, 21
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xmm5, RegXMM, 0, 5, 26, 22
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xmm6, RegXMM, 0, 6, 27, 23
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xmm7, RegXMM, 0, 7, 28, 24
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xmm8, RegXMM, RegRex, 0, Dw2Inval, 25
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xmm9, RegXMM, RegRex, 1, Dw2Inval, 26
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xmm10, RegXMM, RegRex, 2, Dw2Inval, 27
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xmm11, RegXMM, RegRex, 3, Dw2Inval, 28
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xmm12, RegXMM, RegRex, 4, Dw2Inval, 29
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xmm13, RegXMM, RegRex, 5, Dw2Inval, 30
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xmm14, RegXMM, RegRex, 6, Dw2Inval, 31
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xmm15, RegXMM, RegRex, 7, Dw2Inval, 32
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binutils/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (dwarf_regnames_i386): Add AVX registers.
(dwarf_regnames_x86_64): Likewise.
gas/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
Document -msse2avx, .avx, .aes, .clmul and .fma.
* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
(vex_prefix): Likewise.
(sse2avx): Likewise.
(CPU_FLAGS_ARCH_MATCH): Likewise.
(CPU_FLAGS_64BIT_MATCH): Likewise.
(CPU_FLAGS_32BIT_MATCH): Likewise.
(CPU_FLAGS_PERFECT_MATCH): Likewise.
(regymm): Likewise.
(vex_imm4): Likewise.
(fits_in_imm4): Likewise.
(build_vex_prefix): Likewise.
(VEX_check_operands): Likewise.
(bad_implicit_operand): Likewise.
(OPTION_MSSE2AVX): Likewise.
(T_YMMWORD): Likewise.
(_i386_insn): Add vex.
(cpu_arch): Add .avx, .aes, .clmul and .fma.
(cpu_flags_match): Changed to take a pointer to const template.
Enable encoding SSE instructions with VEX prefix for -msse2avx.
(match_mem_size): Also check ymmword.
(operand_type_match): Clear ymmword.
(md_begin): Allow '_' in mnemonic.
(type_names): Add OPERAND_TYPE_VEX_IMM4.
(process_immext): Update assert.
(md_assemble): Don't call process_immext if sse2avx and immext
are true. Call build_vex_prefix if vex is true.
(parse_insn): Updated for cpu_flags_match.
(swap_operands): Handle 5 operands.
(match_template): Handle 5 operands. Updated for cpu_flags_match.
Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
(check_byte_reg): Check regymm.
(process_operands): Duplicate the destination register for
-msse2avx if needed.
(build_modrm_byte): Updated for instructions with VEX encoding.
(output_insn): Output VEX prefix if needed.
(md_longopts): Add msse2avx.
(md_parse_option): Handle OPTION_MSSE2AVX.
(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
(intel_e09): Support YMMWORD.
(intel_e11): Likewise.
(intel_get_token): Likewise.
gas/testsuite/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
x86-64-avx-intel and x86-64-inval-avx.
* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/i386/aes.d: New.
* gas/i386/aes.s: Likewise.
* gas/i386/aes-intel.d: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx.s: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/i386.exp: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/sse2avx.s: Likewise.
* gas/i386/x86-64-aes.d: Likewise.
* gas/i386/x86-64-aes.s: Likewise.
* gas/i386/x86-64-aes-intel.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/rexw.s: Add AVX tests.
* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
* gas/cfi/cfi-i386.d: Updated.
* gas/cfi/cfi-x86_64.d: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/rexw.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
include/opcode/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (MAX_OPERANDS): Set to 5.
(MAX_MNEM_SIZE): Changed to 20.
opcodes/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_register): New.
(OP_E_memory): Likewise.
(OP_VEX): Likewise.
(OP_EX_Vex): Likewise.
(OP_EX_VexW): Likewise.
(OP_XMM_Vex): Likewise.
(OP_XMM_VexW): Likewise.
(OP_REG_VexI4): Likewise.
(PCLMUL_Fixup): Likewise.
(VEXI4_Fixup): Likewise.
(VZERO_Fixup): Likewise.
(VCMP_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(rex_original): Likewise.
(rex_ignored): Likewise.
(Mxmm): Likewise.
(XMM): Likewise.
(EXxmm): Likewise.
(EXxmmq): Likewise.
(EXymmq): Likewise.
(Vex): Likewise.
(Vex128): Likewise.
(Vex256): Likewise.
(VexI4): Likewise.
(EXdVex): Likewise.
(EXqVex): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(XMVex): Likewise.
(XMVexW): Likewise.
(XMVexI4): Likewise.
(PCLMUL): Likewise.
(VZERO): Likewise.
(VCMP): Likewise.
(VPERMIL2): Likewise.
(xmm_mode): Likewise.
(xmmq_mode): Likewise.
(ymmq_mode): Likewise.
(vex_mode): Likewise.
(vex128_mode): Likewise.
(vex256_mode): Likewise.
(USE_VEX_C4_TABLE): Likewise.
(USE_VEX_C5_TABLE): Likewise.
(USE_VEX_LEN_TABLE): Likewise.
(VEX_C4_TABLE): Likewise.
(VEX_C5_TABLE): Likewise.
(VEX_LEN_TABLE): Likewise.
(REG_VEX_XX): Likewise.
(MOD_VEX_XXX): Likewise.
(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
(PREFIX_0F3A44): Likewise.
(PREFIX_0F3ADF): Likewise.
(PREFIX_VEX_XXX): Likewise.
(VEX_OF): Likewise.
(VEX_OF38): Likewise.
(VEX_OF3A): Likewise.
(VEX_LEN_XXX): Likewise.
(vex): Likewise.
(need_vex): Likewise.
(need_vex_reg): Likewise.
(vex_i4_done): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(OP_REG_VexI4): Likewise.
(vex_cmp_op): Likewise.
(pclmul_op): Likewise.
(vpermil2_op): Likewise.
(m_mode): Updated.
(es_reg): Likewise.
(PREFIX_0F38F0): Likewise.
(PREFIX_0F3A60): Likewise.
(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
and PREFIX_VEX_XXX entries.
(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
PREFIX_0F3ADF.
(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
Add MOD_VEX_XXX entries.
(ckprefix): Initialize rex_original and rex_ignored. Store the
REX byte in rex_original.
(get_valid_dis386): Handle the implicit prefix in VEX prefix
bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
calling get_valid_dis386. Use rex_original and rex_ignored when
printing out REX.
(putop): Handle "XY".
(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
ymmq_mode.
(OP_E_extended): Updated to use OP_E_register and
OP_E_memory.
(OP_XMM): Handle VEX.
(OP_EX): Likewise.
(XMM_Fixup): Likewise.
(CMP_Fixup): Use ARRAY_SIZE.
* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
CPU_FMA_FLAGS and CPU_AVX_FLAGS.
(operand_type_init): Add OPERAND_TYPE_REGYMM and
OPERAND_TYPE_VEX_IMM4.
(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
VexImmExt and SSE2AVX.
(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
* i386-opc.h (CpuAVX): New.
(CpuAES): Likewise.
(CpuCLMUL): Likewise.
(CpuFMA): Likewise.
(Vex): Likewise.
(Vex256): Likewise.
(VexNDS): Likewise.
(VexNDD): Likewise.
(VexW0): Likewise.
(VexW1): Likewise.
(Vex0F): Likewise.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(Vex3Sources): Likewise.
(VexImmExt): Likewise.
(SSE2AVX): Likewise.
(RegYMM): Likewise.
(Ymmword): Likewise.
(Vex_Imm4): Likewise.
(Implicit1stXmm0): Likewise.
(CpuXsave): Updated.
(CpuLM): Likewise.
(ByteOkIntel): Likewise.
(OldGcc): Likewise.
(Control): Likewise.
(Unspecified): Likewise.
(OTMax): Likewise.
(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
vex3sources, veximmext and sse2avx.
(i386_operand_type): Add regymm, ymmword and vex_imm4.
* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-04-03 14:03:21 +00:00
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// AVX registers.
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2008-08-01 14:21:30 +00:00
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ymm0, RegYMM, 0, 0, Dw2Inval, Dw2Inval
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ymm1, RegYMM, 0, 1, Dw2Inval, Dw2Inval
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ymm2, RegYMM, 0, 2, Dw2Inval, Dw2Inval
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ymm3, RegYMM, 0, 3, Dw2Inval, Dw2Inval
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ymm4, RegYMM, 0, 4, Dw2Inval, Dw2Inval
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ymm5, RegYMM, 0, 5, Dw2Inval, Dw2Inval
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ymm6, RegYMM, 0, 6, Dw2Inval, Dw2Inval
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ymm7, RegYMM, 0, 7, Dw2Inval, Dw2Inval
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ymm8, RegYMM, RegRex, 0, Dw2Inval, Dw2Inval
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ymm9, RegYMM, RegRex, 1, Dw2Inval, Dw2Inval
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ymm10, RegYMM, RegRex, 2, Dw2Inval, Dw2Inval
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ymm11, RegYMM, RegRex, 3, Dw2Inval, Dw2Inval
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ymm12, RegYMM, RegRex, 4, Dw2Inval, Dw2Inval
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ymm13, RegYMM, RegRex, 5, Dw2Inval, Dw2Inval
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ymm14, RegYMM, RegRex, 6, Dw2Inval, Dw2Inval
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ymm15, RegYMM, RegRex, 7, Dw2Inval, Dw2Inval
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2007-09-26 13:40:59 +00:00
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// No type will make these registers rejected for all purposes except
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// for addressing. This saves creating one extra type for RIP/EIP.
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2008-02-13 10:14:40 +00:00
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rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16
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eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval
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2007-09-20 17:38:38 +00:00
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// No type will make these registers rejected for all purposes except
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// for addressing.
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2013-03-02 01:57:48 +00:00
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riz, BaseIndex, RegRex64, RegRiz, Dw2Inval, Dw2Inval
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2008-02-13 10:14:40 +00:00
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eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval
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2007-06-28 14:29:56 +00:00
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// fp regs.
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2008-02-13 10:14:40 +00:00
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st(0), FloatReg|FloatAcc, 0, 0, 11, 33
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st(1), FloatReg, 0, 1, 12, 34
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st(2), FloatReg, 0, 2, 13, 35
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st(3), FloatReg, 0, 3, 14, 36
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st(4), FloatReg, 0, 4, 15, 37
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st(5), FloatReg, 0, 5, 16, 38
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st(6), FloatReg, 0, 6, 17, 39
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st(7), FloatReg, 0, 7, 18, 40
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// Pseudo-register names only used in .cfi_* directives
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eflags, 0, 0, 0, 9, 49
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rflags, 0, 0, 0, Dw2Inval, 49
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fs.base, 0, 0, 0, Dw2Inval, 58
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gs.base, 0, 0, 0, Dw2Inval, 59
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tr, 0, 0, 0, 48, 62
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ldtr, 0, 0, 0, 49, 63
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// st0...7 for backward compatibility
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st0, 0, 0, 0, 11, 33
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st1, 0, 0, 1, 12, 34
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st2, 0, 0, 2, 13, 35
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st3, 0, 0, 3, 14, 36
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st4, 0, 0, 4, 15, 37
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st5, 0, 0, 5, 16, 38
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st6, 0, 0, 6, 17, 39
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st7, 0, 0, 7, 18, 40
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fcw, 0, 0, 0, 37, 65
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fsw, 0, 0, 0, 38, 66
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mxcsr, 0, 0, 0, 39, 64
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