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Mon Jun 8 12:15:52 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
* i386.h (REPNE): Rename to REPNE_PREFIX_OPCODE. (REPE): Rename to REPE_PREFIX_OPCODE. (i386_regtab_end): Remove. (i386_prefixtab, i386_prefixtab_end): Remove. (i386_optab): Use NULL as sentinel rather than "" to suit rewrite of md_begin. (MAX_OPCODE_SIZE): Define. (i386_optab_end): Remove. (sl_Suf): Define. (sl_FP): Use sl_Suf. * i386.h (i386_optab): Allow 16 bit displacement for `mov mem,acc'. Combine 16 and 32 bit forms of various insns. Allow 16 bit form of ljmp. Add IsPrefix modifier to prefixes. Add addr32, data32, dword, and adword prefixes. (i386_regtab): Add BaseIndex modifier to valid 16 bit base/index regs.
This commit is contained in:
Ian Lance Taylor
parent
3f59a76366
commit
038915c98c
@ -1,3 +1,23 @@
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Mon Jun 8 12:15:52 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
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* i386.h (REPNE): Rename to REPNE_PREFIX_OPCODE.
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(REPE): Rename to REPE_PREFIX_OPCODE.
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(i386_regtab_end): Remove.
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(i386_prefixtab, i386_prefixtab_end): Remove.
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(i386_optab): Use NULL as sentinel rather than "" to suit rewrite
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of md_begin.
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(MAX_OPCODE_SIZE): Define.
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(i386_optab_end): Remove.
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(sl_Suf): Define.
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(sl_FP): Use sl_Suf.
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* i386.h (i386_optab): Allow 16 bit displacement for `mov
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mem,acc'. Combine 16 and 32 bit forms of various insns. Allow 16
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bit form of ljmp. Add IsPrefix modifier to prefixes. Add addr32,
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data32, dword, and adword prefixes.
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(i386_regtab): Add BaseIndex modifier to valid 16 bit base/index
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regs.
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Fri Jun 5 23:42:43 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
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* i386.h (i386_regtab): Remove BaseIndex modifier from esp.
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@ -50,10 +50,11 @@ static const template i386_optab[] = {
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#define bw_Suf (No_lSuf|No_sSuf)
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#define bl_Suf (No_wSuf|No_sSuf)
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#define wl_Suf (No_bSuf|No_sSuf)
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#define sl_Suf (No_bSuf|No_wSuf)
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#define bwl_Suf No_sSuf
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#define FP (NoSuf|IgnoreDataSize)
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#define l_FP (l_Suf|IgnoreDataSize)
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#define sl_FP (No_bSuf|No_wSuf|IgnoreDataSize)
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#define sl_FP (sl_Suf|IgnoreDataSize)
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#if UNIXWARE_COMPAT
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#define FloatDR FloatD
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#else
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@ -62,7 +63,7 @@ static const template i386_optab[] = {
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/* move instructions */
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#define MOV_AX_DISP32 0xa0
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{ "mov", 2, 0xa0, X, bwl_Suf|D|W, { Disp32, Acc, 0 } },
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{ "mov", 2, 0xa0, X, bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } },
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{ "mov", 2, 0x88, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0 } },
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{ "mov", 2, 0xb0, X, bwl_Suf|W|ShortForm, { Imm, Reg, 0 } },
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{ "mov", 2, 0xc6, X, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0 } },
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@ -219,8 +220,8 @@ static const template i386_optab[] = {
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/* conversion insns */
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/* conversion: intel naming */
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{"cbw", 0, 0x98, X, NoSuf|Data16, { 0, 0, 0} },
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{"cwd", 0, 0x99, X, NoSuf|Data16, { 0, 0, 0} },
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{"cwde", 0, 0x98, X, NoSuf|Data32, { 0, 0, 0} },
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{"cwd", 0, 0x99, X, NoSuf|Data16, { 0, 0, 0} },
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{"cdq", 0, 0x99, X, NoSuf|Data32, { 0, 0, 0} },
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/* att naming */
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{"cbtw", 0, 0x98, X, NoSuf|Data16, { 0, 0, 0} },
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@ -296,31 +297,23 @@ static const template i386_optab[] = {
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{"sar", 1, 0xd0, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
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/* control transfer instructions */
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{"call", 1, 0xe8, X, NoSuf|JumpDword, { Disp32, 0, 0} },
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{"call", 1, 0xff, 2, NoSuf|Modrm|Data32, { WordReg|WordMem|JumpAbsolute, 0, 0} },
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{"callw", 1, 0xff, 2, NoSuf|Modrm|Data16, { WordReg|WordMem|JumpAbsolute, 0, 0} },
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{"lcall", 2, 0x9a, X, NoSuf|JumpInterSegment, { Imm16, Imm32, 0} },
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{"lcall", 1, 0xff, 3, NoSuf|Modrm|Data32, { WordMem, 0, 0} },
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{"lcallw", 1, 0xff, 3, NoSuf|Modrm|Data16, { WordMem, 0, 0} },
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{"call", 1, 0xe8, X, wl_Suf|JumpDword, { Disp16|Disp32, 0, 0} },
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{"call", 1, 0xff, 2, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} },
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{"lcall", 2, 0x9a, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
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{"lcall", 1, 0xff, 3, wl_Suf|Modrm, { WordMem, 0, 0} },
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#define JUMP_PC_RELATIVE 0xeb
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{"jmp", 1, 0xeb, X, NoSuf|Jump, { Disp, 0, 0} },
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{"jmp", 1, 0xff, 4, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} },
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{"ljmp", 2, 0xea, X, NoSuf|JumpInterSegment, { Imm16, Imm32, 0} },
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{"ljmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
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{"ljmp", 1, 0xff, 5, wl_Suf|Modrm, { WordMem, 0, 0} },
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{"ret", 0, 0xc3, X, l_Suf|Data32, { 0, 0, 0} },
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{"ret", 1, 0xc2, X, l_Suf|Data32, { Imm16, 0, 0} },
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{"retw", 0, 0xc3, X, NoSuf|Data16, { 0, 0, 0} },
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{"retw", 1, 0xc2, X, NoSuf|Data16, { Imm16, 0, 0} },
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{"lret", 0, 0xcb, X, l_Suf|Data32, { 0, 0, 0} },
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{"lret", 1, 0xca, X, l_Suf|Data32, { Imm16, 0, 0} },
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{"lretw", 0, 0xcb, X, NoSuf|Data16, { 0, 0, 0} },
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{"lretw", 1, 0xca, X, NoSuf|Data16, { Imm16, 0, 0} },
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{"enter", 2, 0xc8, X, l_Suf|Data32, { Imm16, Imm8, 0} },
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{"leave", 0, 0xc9, X, l_Suf|Data32, { 0, 0, 0} },
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{"enterw", 2, 0xc8, X, NoSuf|Data16, { Imm16, Imm8, 0} },
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{"leavew", 0, 0xc9, X, NoSuf|Data16, { 0, 0, 0} },
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{"ret", 0, 0xc3, X, wl_Suf, { 0, 0, 0} },
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{"ret", 1, 0xc2, X, wl_Suf, { Imm16, 0, 0} },
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{"lret", 0, 0xcb, X, wl_Suf, { 0, 0, 0} },
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{"lret", 1, 0xca, X, wl_Suf, { Imm16, 0, 0} },
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{"enter", 2, 0xc8, X, wl_Suf, { Imm16, Imm8, 0} },
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{"leave", 0, 0xc9, X, wl_Suf, { 0, 0, 0} },
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/* conditional jumps */
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{"jo", 1, 0x70, X, NoSuf|Jump, { Disp, 0, 0} },
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@ -454,15 +447,13 @@ static const template i386_optab[] = {
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{"int", 1, 0xcd, X, NoSuf, { Imm8, 0, 0} },
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{"int3", 0, 0xcc, X, NoSuf, { 0, 0, 0} },
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{"into", 0, 0xce, X, NoSuf, { 0, 0, 0} },
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{"iret", 0, 0xcf, X, l_Suf|Data32, { 0, 0, 0} },
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{"iretw", 0, 0xcf, X, NoSuf|Data16, { 0, 0, 0} },
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{"iret", 0, 0xcf, X, wl_Suf, { 0, 0, 0} },
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/* i386sl, i486sl, later 486, and Pentium */
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{"rsm", 0, 0x0faa, X, NoSuf, { 0, 0, 0} },
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{"bound", 2, 0x62, X, wl_Suf|Modrm, { WordReg, WordMem, 0} },
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{"hlt", 0, 0xf4, X, NoSuf, { 0, 0, 0} },
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{"wait", 0, 0x9b, X, NoSuf, { 0, 0, 0} },
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/* nop is actually 'xchgl %eax, %eax' */
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{"nop", 0, 0x90, X, NoSuf, { 0, 0, 0} },
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@ -694,17 +685,14 @@ static const template i386_optab[] = {
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{"fstsw", 0, 0xdfe0, X, FP|FWait, { 0, 0, 0} },
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{"fnclex", 0, 0xdbe2, X, FP, { 0, 0, 0} },
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{"fclex", 0, 0xdbe2, X, FP|FWait, { 0, 0, 0} },
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{"fnstenv",1, 0xd9, 6, NoSuf|Modrm|Data32, { LLongMem, 0, 0} },
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{"fstenv", 1, 0xd9, 6, NoSuf|FWait|Modrm|Data32, { LLongMem, 0, 0} },
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{"fldenv", 1, 0xd9, 4, NoSuf|Modrm|Data32, { LLongMem, 0, 0} },
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{"fnsave", 1, 0xdd, 6, NoSuf|Modrm, { LLongMem, 0, 0} },
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{"fsave", 1, 0xdd, 6, NoSuf|FWait|Modrm, { LLongMem, 0, 0} },
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{"frstor", 1, 0xdd, 4, NoSuf|Modrm, { LLongMem, 0, 0} },
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/* Short forms of fldenv, fstenv use data size prefix.
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FIXME: Are these the right names? */
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{"fnstenvs",1, 0xd9, 6, NoSuf|Modrm|Data16, { LLongMem, 0, 0} },
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{"fstenvs", 1, 0xd9, 6, NoSuf|FWait|Modrm|Data16, { LLongMem, 0, 0} },
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{"fldenvs", 1, 0xd9, 4, NoSuf|Modrm|Data16, { LLongMem, 0, 0} },
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FIXME: Are these the right suffixes? */
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{"fnstenv",1, 0xd9, 6, sl_Suf|Modrm, { LLongMem, 0, 0} },
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{"fstenv", 1, 0xd9, 6, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
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{"fldenv", 1, 0xd9, 4, sl_Suf|Modrm, { LLongMem, 0, 0} },
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{"fnsave", 1, 0xdd, 6, sl_Suf|Modrm, { LLongMem, 0, 0} },
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{"fsave", 1, 0xdd, 6, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
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{"frstor", 1, 0xdd, 4, sl_Suf|Modrm, { LLongMem, 0, 0} },
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{"ffree", 1, 0xddc0, X, FP|ShortForm, { FloatReg, 0, 0} },
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/* P6:free st(i), pop st */
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@ -715,24 +703,39 @@ static const template i386_optab[] = {
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/*
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opcode prefixes; we allow them as seperate insns too
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(see prefix table below)
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*/
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{"aword", 0, 0x67, X, NoSuf, { 0, 0, 0} },
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{"addr16", 0, 0x67, X, NoSuf, { 0, 0, 0} },
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{"word", 0, 0x66, X, NoSuf, { 0, 0, 0} },
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{"data16", 0, 0x66, X, NoSuf, { 0, 0, 0} },
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{"lock", 0, 0xf0, X, NoSuf, { 0, 0, 0} },
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{"cs", 0, 0x2e, X, NoSuf, { 0, 0, 0} },
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{"ds", 0, 0x3e, X, NoSuf, { 0, 0, 0} },
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{"es", 0, 0x26, X, NoSuf, { 0, 0, 0} },
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{"fs", 0, 0x64, X, NoSuf, { 0, 0, 0} },
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{"gs", 0, 0x65, X, NoSuf, { 0, 0, 0} },
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{"ss", 0, 0x36, X, NoSuf, { 0, 0, 0} },
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{"rep", 0, 0xf3, X, NoSuf, { 0, 0, 0} },
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{"repe", 0, 0xf3, X, NoSuf, { 0, 0, 0} },
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{"repz", 0, 0xf3, X, NoSuf, { 0, 0, 0} },
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{"repne", 0, 0xf2, X, NoSuf, { 0, 0, 0} },
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{"repnz", 0, 0xf2, X, NoSuf, { 0, 0, 0} },
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#define ADDR_PREFIX_OPCODE 0x67
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{"addr16", 0, 0x67, X, NoSuf|IsPrefix, { 0, 0, 0} },
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{"addr32", 0, 0x67, X, NoSuf|IsPrefix, { 0, 0, 0} },
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{"aword", 0, 0x67, X, NoSuf|IsPrefix, { 0, 0, 0} },
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{"adword", 0, 0x67, X, NoSuf|IsPrefix, { 0, 0, 0} },
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#define DATA_PREFIX_OPCODE 0x66
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{"data16", 0, 0x66, X, NoSuf|IsPrefix, { 0, 0, 0} },
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{"data32", 0, 0x66, X, NoSuf|IsPrefix, { 0, 0, 0} },
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{"word", 0, 0x66, X, NoSuf|IsPrefix, { 0, 0, 0} },
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{"dword", 0, 0x66, X, NoSuf|IsPrefix, { 0, 0, 0} },
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#define LOCK_PREFIX_OPCODE 0xf0
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{"lock", 0, 0xf0, X, NoSuf|IsPrefix, { 0, 0, 0} },
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{"wait", 0, 0x9b, X, NoSuf|IsPrefix, { 0, 0, 0} },
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#define CS_PREFIX_OPCODE 0x2e
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{"cs", 0, 0x2e, X, NoSuf|IsPrefix, { 0, 0, 0} },
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#define DS_PREFIX_OPCODE 0x3e
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{"ds", 0, 0x3e, X, NoSuf|IsPrefix, { 0, 0, 0} },
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#define ES_PREFIX_OPCODE 0x26
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{"es", 0, 0x26, X, NoSuf|IsPrefix, { 0, 0, 0} },
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#define FS_PREFIX_OPCODE 0x64
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{"fs", 0, 0x64, X, NoSuf|IsPrefix, { 0, 0, 0} },
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#define GS_PREFIX_OPCODE 0x65
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{"gs", 0, 0x65, X, NoSuf|IsPrefix, { 0, 0, 0} },
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#define SS_PREFIX_OPCODE 0x36
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{"ss", 0, 0x36, X, NoSuf|IsPrefix, { 0, 0, 0} },
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#define REPNE_PREFIX_OPCODE 0xf2
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#define REPE_PREFIX_OPCODE 0xf3
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{"rep", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} },
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{"repe", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} },
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{"repz", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} },
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{"repne", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} },
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{"repnz", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} },
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/* 486 extensions */
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@ -848,7 +851,7 @@ static const template i386_optab[] = {
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{"punpckldq",2, 0x0f62, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"pxor", 2, 0x0fef, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
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{"", 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */
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{NULL, 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */
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};
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#undef X
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#undef ReverseModrm
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@ -859,13 +862,14 @@ static const template i386_optab[] = {
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#undef bw_Suf
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#undef bl_Suf
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#undef wl_Suf
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#undef sl_Suf
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#undef bwl_Suf
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#undef FP
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#undef l_FP
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#undef sl_FP
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static const template *const i386_optab_end
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= i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]);
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#define MAX_OPCODE_SIZE 16 /* for parsing opcodes from input */
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/* 386 register table */
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@ -883,11 +887,11 @@ static const reg_entry i386_regtab[] = {
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{"ax", Reg16|Acc, 0},
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{"cx", Reg16, 1},
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{"dx", Reg16|InOutPortReg, 2},
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{"bx", Reg16, 3},
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{"bx", Reg16|BaseIndex, 3},
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{"sp", Reg16, 4},
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{"bp", Reg16, 5},
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{"si", Reg16, 6},
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{"di", Reg16, 7},
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{"bp", Reg16|BaseIndex, 5},
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{"si", Reg16|BaseIndex, 6},
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{"di", Reg16|BaseIndex, 7},
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/* 32 bit regs */
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{"eax", Reg32|BaseIndex|Acc, 0},
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{"ecx", Reg32|BaseIndex, 1},
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@ -950,9 +954,6 @@ static const reg_entry i386_regtab[] = {
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#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
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static const reg_entry *const i386_regtab_end
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= i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]);
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/* segment stuff */
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static const seg_entry cs = { "cs", 0x2e };
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static const seg_entry ds = { "ds", 0x3e };
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@ -961,38 +962,4 @@ static const seg_entry es = { "es", 0x26 };
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static const seg_entry fs = { "fs", 0x64 };
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static const seg_entry gs = { "gs", 0x65 };
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static const prefix_entry i386_prefixtab[] = {
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#define ADDR_PREFIX_OPCODE 0x67
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{ "addr16", 0x67 }, /* address size prefix ==> 16bit addressing
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useful when loop isns should use %cx. */
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#define DATA_PREFIX_OPCODE 0x66
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{ "data16", 0x66 }, /* operand size prefix */
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#define LOCK_PREFIX_OPCODE 0xf0
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{ "lock", 0xf0 }, /* bus lock prefix */
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{ "wait", FWAIT_OPCODE }, /* wait for coprocessor, not really a prefix */
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#define CS_PREFIX_OPCODE 0x2e
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{ "cs", 0x2e }, /* segment overrides ... */
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#define DS_PREFIX_OPCODE 0x3e
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{ "ds", 0x3e },
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#define ES_PREFIX_OPCODE 0x26
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{ "es", 0x26 },
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#define FS_PREFIX_OPCODE 0x64
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{ "fs", 0x64 },
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#define GS_PREFIX_OPCODE 0x65
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{ "gs", 0x65 },
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#define SS_PREFIX_OPCODE 0x36
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{ "ss", 0x36 },
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/* REPE & REPNE used to detect rep/repne with a non-string instruction */
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#define REPNE 0xf2
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#define REPE 0xf3
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{ "rep", 0xf3 }, /* repeat string instructions */
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{ "repe", 0xf3 },
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{ "repz", 0xf3 },
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{ "repne", 0xf2 },
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{ "repnz", 0xf2 }
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};
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static const prefix_entry *const i386_prefixtab_end
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= i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]);
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/* end of i386-opcode.h */
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