darlinghq/darling-gdb
1
0
Fork 0
mirror of https://github.com/darlinghq/darling-gdb.git synced 2025-02-21 18:11:31 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Initial revision

Browse Source
This commit is contained in:
K. Richard Pixley 1991-05-19 00:19:54 +00:00
parent 912e0732be
commit 089aacdb56
16 changed files with 9489 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

301
include/a29k-opcode.h Executable file
View File

@ -0,0 +1,301 @@
/* Table of opcodes for the AMD 29000
Copyright (C) 1990, 1991 Free Software Foundation, Inc.
This file is part of GDB and GAS.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 1, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
/* $Id$ */
struct a29k_opcode {
/* Name of the instruction. */
char *name;
/* Opcode word */
unsigned long opcode;
/* A string of characters which describe the operands.
Valid characters are:
, Itself. The character appears in the assembly code.
a RA. The register number is in bits 8-15 of the instruction.
b RB. The register number is in bits 0-7 of the instruction.
c RC. The register number is in bits 16-23 of the instruction.
i An immediate operand is in bits 0-7 of the instruction.
x Bits 0-7 and 16-23 of the instruction are bits 0-7 and 8-15
(respectively) of the immediate operand.
h Same as x but the instruction contains bits 16-31 of the
immediate operand.
X Same as x but bits 16-31 of the signed immediate operand
are set to 1 (thus the operand is always negative).
P,A Bits 0-7 and 16-23 of the instruction are bits 2-9 and 10-17
(respectively) of the immediate operand.
P=PC-relative, sign-extended to 32 bits.
A=Absolute, zero-extended to 32 bits.
e CE bit (bit 23) for a load/store instruction.
n Control field (bits 16-22) for a load/store instruction.
v Immediate operand in bits 16-23 of the instruction.
(used for trap numbers).
s SA. Special-purpose register number in bits 8-15
of the instruction.
u UI--bit 7 of the instruction.
r RND--bits 4-6 of the instruction.
d FD--bits 2-3 of the instruction.
f FS--bits 0-1 of the instruction.
Extensions for 29050:
d FMT--bits 2-3 of the instruction (not really new).
f ACN--bits 0-1 of the instruction (not really new).
F FUNC--Special function in bits 18-21 of the instruction.
C ACN--bits 16-17 specifying the accumlator register. */
char *args;
};
static const struct a29k_opcode a29k_opcodes[] =
{
{ "add", 0x14000000, "c,a,b" },
{ "add", 0x15000000, "c,a,i" },
{ "addc", 0x1c000000, "c,a,b" },
{ "addc", 0x1d000000, "c,a,i" },
{ "addcs", 0x18000000, "c,a,b" },
{ "addcs", 0x19000000, "c,a,i" },
{ "addcu", 0x1a000000, "c,a,b" },
{ "addcu", 0x1b000000, "c,a,i" },
{ "adds", 0x10000000, "c,a,b" },
{ "adds", 0x11000000, "c,a,i" },
{ "addu", 0x12000000, "c,a,b" },
{ "addu", 0x13000000, "c,a,i" },
{ "and", 0x90000000, "c,a,b" },
{ "and", 0x91000000, "c,a,i" },
{ "andn", 0x9c000000, "c,a,b" },
{ "andn", 0x9d000000, "c,a,i" },
{ "aseq", 0x70000000, "v,a,b" },
{ "aseq", 0x71000000, "v,a,i" },
{ "asge", 0x5c000000, "v,a,b" },
{ "asge", 0x5d000000, "v,a,i" },
{ "asgeu", 0x5e000000, "v,a,b" },
{ "asgeu", 0x5f000000, "v,a,i" },
{ "asgt", 0x58000000, "v,a,b" },
{ "asgt", 0x59000000, "v,a,i" },
{ "asgtu", 0x5a000000, "v,a,b" },
{ "asgtu", 0x5b000000, "v,a,i" },
{ "asle", 0x54000000, "v,a,b" },
{ "asle", 0x55000000, "v,a,i" },
{ "asleu", 0x56000000, "v,a,b" },
{ "asleu", 0x57000000, "v,a,i" },
{ "aslt", 0x50000000, "v,a,b" },
{ "aslt", 0x51000000, "v,a,i" },
{ "asltu", 0x52000000, "v,a,b" },
{ "asltu", 0x53000000, "v,a,i" },
{ "asneq", 0x72000000, "v,a,b" },
{ "asneq", 0x73000000, "v,a,i" },
{ "call", 0xa8000000, "a,P" },
{ "call", 0xa9000000, "a,A" },
{ "calli", 0xc8000000, "a,b" },
{ "class", 0xe6000000, "c,a,f" },
{ "clz", 0x08000000, "c,b" },
{ "clz", 0x09000000, "c,i" },
{ "const", 0x03000000, "a,x" },
{ "consth", 0x02000000, "a,h" },
{ "consthz", 0x05000000, "a,h" },
{ "constn", 0x01000000, "a,X" },
{ "convert", 0xe4000000, "c,a,u,r,d,f" },
{ "cpbyte", 0x2e000000, "c,a,b" },
{ "cpbyte", 0x2f000000, "c,a,i" },
{ "cpeq", 0x60000000, "c,a,b" },
{ "cpeq", 0x61000000, "c,a,i" },
{ "cpge", 0x4c000000, "c,a,b" },
{ "cpge", 0x4d000000, "c,a,i" },
{ "cpgeu", 0x4e000000, "c,a,b" },
{ "cpgeu", 0x4f000000, "c,a,i" },
{ "cpgt", 0x48000000, "c,a,b" },
{ "cpgt", 0x49000000, "c,a,i" },
{ "cpgtu", 0x4a000000, "c,a,b" },
{ "cpgtu", 0x4b000000, "c,a,i" },
{ "cple", 0x44000000, "c,a,b" },
{ "cple", 0x45000000, "c,a,i" },
{ "cpleu", 0x46000000, "c,a,b" },
{ "cpleu", 0x47000000, "c,a,i" },
{ "cplt", 0x40000000, "c,a,b" },
{ "cplt", 0x41000000, "c,a,i" },
{ "cpltu", 0x42000000, "c,a,b" },
{ "cpltu", 0x43000000, "c,a,i" },
{ "cpneq", 0x62000000, "c,a,b" },
{ "cpneq", 0x63000000, "c,a,i" },
{ "dadd", 0xf1000000, "c,a,b" },
{ "ddiv", 0xf7000000, "c,a,b" },
{ "deq", 0xeb000000, "c,a,b" },
{ "dge", 0xef000000, "c,a,b" },
{ "dgt", 0xed000000, "c,a,b" },
{ "div", 0x6a000000, "c,a,b" },
{ "div", 0x6b000000, "c,a,i" },
{ "div0", 0x68000000, "c,b" },
{ "div0", 0x69000000, "c,i" },
{ "divide", 0xe1000000, "c,a,b" },
{ "dividu", 0xe3000000, "c,a,b" },
{ "divl", 0x6c000000, "c,a,b" },
{ "divl", 0x6d000000, "c,a,i" },
{ "divrem", 0x6e000000, "c,a,b" },
{ "divrem", 0x6f000000, "c,a,i" },
{ "dmac", 0xd9000000, "F,C,a,b" },
{ "dmsm", 0xdb000000, "c,a,b" },
{ "dmul", 0xf5000000, "c,a,b" },
{ "dsub", 0xf3000000, "c,a,b" },
{ "emulate", 0xd7000000, "v,a,b" },
{ "exbyte", 0x0a000000, "c,a,b" },
{ "exbyte", 0x0b000000, "c,a,i" },
{ "exhw", 0x7c000000, "c,a,b" },
{ "exhw", 0x7d000000, "c,a,i" },
{ "exhws", 0x7e000000, "c,a" },
{ "extract", 0x7a000000, "c,a,b" },
{ "extract", 0x7b000000, "c,a,i" },
{ "fadd", 0xf0000000, "c,a,b" },
{ "fdiv", 0xf6000000, "c,a,b" },
{ "fdmul", 0xf9000000, "c,a,b" },
{ "feq", 0xea000000, "c,a,b" },
{ "fge", 0xee000000, "c,a,b" },
{ "fgt", 0xec000000, "c,a,b" },
{ "fmac", 0xd8000000, "F,C,a,b" },
{ "fmsm", 0xda000000, "c,a,b" },
{ "fmul", 0xf4000000, "c,a,b" },
{ "fsub", 0xf2000000, "c,a,b" },
{ "halt", 0x89000000, "" },
{ "inbyte", 0x0c000000, "c,a,b" },
{ "inbyte", 0x0d000000, "c,a,i" },
{ "inhw", 0x78000000, "c,a,b" },
{ "inhw", 0x79000000, "c,a,i" },
{ "inv", 0x9f000000, "" },
{ "iret", 0x88000000, "" },
{ "iretinv", 0x8c000000, "" },
{ "jmp", 0xa0000000, "P" },
{ "jmp", 0xa1000000, "A" },
{ "jmpf", 0xa4000000, "a,P" },
{ "jmpf", 0xa5000000, "a,A" },
{ "jmpfdec", 0xb4000000, "a,P" },
{ "jmpfdec", 0xb5000000, "a,A" },
{ "jmpfi", 0xc4000000, "a,b" },
{ "jmpi", 0xc0000000, "b" },
{ "jmpt", 0xac000000, "a,P" },
{ "jmpt", 0xad000000, "a,A" },
{ "jmpti", 0xcc000000, "a,b" },
{ "load", 0x16000000, "e,n,a,b" },
{ "load", 0x17000000, "e,n,a,i" },
{ "loadl", 0x06000000, "e,n,a,b" },
{ "loadl", 0x07000000, "e,n,a,i" },
{ "loadm", 0x36000000, "e,n,a,b" },
{ "loadm", 0x37000000, "e,n,a,i" },
{ "loadset", 0x26000000, "e,n,a,b" },
{ "loadset", 0x27000000, "e,n,a,i" },
{ "mfacc", 0xe9000100, "c,d,f" },
{ "mfsr", 0xc6000000, "c,s" },
{ "mftlb", 0xb6000000, "c,a" },
{ "mtacc", 0xe8010000, "c,d,f" },
{ "mtsr", 0xce000000, "s,b" },
{ "mtsrim", 0x04000000, "s,x" },
{ "mttlb", 0xbe000000, "a,b" },
{ "mul", 0x64000000, "c,a,b" },
{ "mul", 0x65000000, "c,a,i" },
{ "mull", 0x66000000, "c,a,b" },
{ "mull", 0x67000000, "c,a,i" },
{ "multiplu", 0xe2000000, "c,a,b" },
{ "multiply", 0xe0000000, "c,a,b" },
{ "multm", 0xde000000, "c,a,b" },
{ "multmu", 0xdf000000, "c,a,b" },
{ "mulu", 0x74000000, "c,a,b" },
{ "mulu", 0x75000000, "c,a,i" },
{ "nand", 0x9a000000, "c,a,b" },
{ "nand", 0x9b000000, "c,a,i" },
{ "nop", 0x70400101, "" },
{ "nor", 0x98000000, "c,a,b" },
{ "nor", 0x99000000, "c,a,i" },
{ "or", 0x92000000, "c,a,b" },
{ "or", 0x93000000, "c,a,i" },
{ "orn", 0xaa000000, "c,a,b" },
{ "orn", 0xab000000, "c,a,i" },
/* The description of "setip" in Chapter 8 ("instruction set") of the user's
manual claims that these are absolute register numbers. But section
7.2.1 explains that they are not. The latter is correct, so print
these normally ("lr0", "lr5", etc.). */
{ "setip", 0x9e000000, "c,a,b" },
{ "sll", 0x80000000, "c,a,b" },
{ "sll", 0x81000000, "c,a,i" },
{ "sqrt", 0xe5000000, "c,a,f" },
{ "sra", 0x86000000, "c,a,b" },
{ "sra", 0x87000000, "c,a,i" },
{ "srl", 0x82000000, "c,a,b" },
{ "srl", 0x83000000, "c,a,i" },
{ "store", 0x1e000000, "e,n,a,b" },
{ "store", 0x1f000000, "e,n,a,i" },
{ "storel", 0x0e000000, "e,n,a,b" },
{ "storel", 0x0f000000, "e,n,a,i" },
{ "storem", 0x3e000000, "e,n,a,b" },
{ "storem", 0x3f000000, "e,n,a,i" },
{ "sub", 0x24000000, "c,a,b" },
{ "sub", 0x25000000, "c,a,i" },
{ "subc", 0x2c000000, "c,a,b" },
{ "subc", 0x2d000000, "c,a,i" },
{ "subcs", 0x28000000, "c,a,b" },
{ "subcs", 0x29000000, "c,a,i" },
{ "subcu", 0x2a000000, "c,a,b" },
{ "subcu", 0x2b000000, "c,a,i" },
{ "subr", 0x34000000, "c,a,b" },
{ "subr", 0x35000000, "c,a,i" },
{ "subrc", 0x3c000000, "c,a,b" },
{ "subrc", 0x3d000000, "c,a,i" },
{ "subrcs", 0x38000000, "c,a,b" },
{ "subrcs", 0x39000000, "c,a,i" },
{ "subrcu", 0x3a000000, "c,a,b" },
{ "subrcu", 0x3b000000, "c,a,i" },
{ "subrs", 0x30000000, "c,a,b" },
{ "subrs", 0x31000000, "c,a,i" },
{ "subru", 0x32000000, "c,a,b" },
{ "subru", 0x33000000, "c,a,i" },
{ "subs", 0x20000000, "c,a,b" },
{ "subs", 0x21000000, "c,a,i" },
{ "subu", 0x22000000, "c,a,b" },
{ "subu", 0x23000000, "c,a,i" },
{ "xnor", 0x96000000, "c,a,b" },
{ "xnor", 0x97000000, "c,a,i" },
{ "xor", 0x94000000, "c,a,b" },
{ "xor", 0x95000000, "c,a,i" },
{ "", 0x0, "" } /* Dummy entry, not included in NUM_OPCODES. This
lets code examine entry i+1 without checking
if we've run off the end of the table. */
};
const unsigned int num_opcodes = (((sizeof a29k_opcodes) / (sizeof a29k_opcodes[0])) - 1);
/*
* $Log$
* Revision 1.1 1991/05/19 00:19:33 rich
* Initial revision
*
* Revision 1.1.1.1 1991/04/04 18:15:23 rich
* new gas main line
*
* Revision 1.1 1991/04/04 18:15:23 rich
* Initial revision
*
* Revision 1.2 1991/03/30 17:13:19 rich
* num_opcodes now unsigned. Also, added rcsid and log.
*
*
*/
/* end of a29k-opcode.h */

294
include/arm-opcode.h Executable file
View File

@ -0,0 +1,294 @@
/* ARM opcode list.
Copyright (C) 1989, Free Software Foundation, Inc.
This file is part of GDB and GAS.
GDB and GAS are free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 1, or (at your option)
any later version.
GDB and GAS are distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GDB or GAS; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
/* types of instruction (encoded in bits 26 and 27 of the instruction) */
#define TYPE_ARITHMETIC 0
#define TYPE_LDR_STR 1
#define TYPE_BLOCK_BRANCH 2
#define TYPE_SWI 3
/* bit 25 decides whether an instruction is a block move or a branch */
#define SUBTYPE_BLOCK 0
#define SUBTYPE_BRANCH 1
/* codes to distinguish the arithmetic instructions */
#define OPCODE_AND 0
#define OPCODE_EOR 1
#define OPCODE_SUB 2
#define OPCODE_RSB 3
#define OPCODE_ADD 4
#define OPCODE_ADC 5
#define OPCODE_SBC 6
#define OPCODE_RSC 7
#define OPCODE_TST 8
#define OPCODE_TEQ 9
#define OPCODE_CMP 10
#define OPCODE_CMN 11
#define OPCODE_ORR 12
#define OPCODE_MOV 13
#define OPCODE_BIC 14
#define OPCODE_MVN 15
/* condition codes */
#define COND_EQ 0
#define COND_NE 1
#define COND_CS 2
#define COND_CC 3
#define COND_MI 4
#define COND_PL 5
#define COND_VS 6
#define COND_VC 7
#define COND_HI 8
#define COND_LS 9
#define COND_GE 10
#define COND_LT 11
#define COND_GT 12
#define COND_LE 13
#define COND_AL 14
#define COND_NV 15
/* Describes the format of an ARM machine instruction */
struct generic_fmt {
unsigned rest :25; /* the rest of the instruction */
unsigned subtype :1; /* used to decide between block and branch */
unsigned type :2; /* one of TYPE_* */
unsigned cond :4; /* one of COND_* defined above */
};
struct arith_fmt {
unsigned operand2 :12; /* #nn or rn or rn shift #m or rn shift rm */
unsigned dest :4; /* place where the answer goes */
unsigned operand1 :4; /* first operand to instruction */
unsigned set :1; /* == 1 means set processor flags */
unsigned opcode :4; /* one of OPCODE_* defined above */
unsigned immed :1; /* operand2 is an immediate value */
unsigned type :2; /* == TYPE_ARITHMETIC */
unsigned cond :4; /* one of COND_* defined above */
};
struct ldr_str_fmt {
unsigned offset :12; /* #nn or rn or rn shift #m */
unsigned reg :4; /* destination for LDR, source for STR */
unsigned base :4; /* base register */
unsigned is_load :1; /* == 1 for LDR */
unsigned writeback :1; /* == 1 means write back (base+offset) into base */
unsigned byte :1; /* == 1 means byte access else word */
unsigned up :1; /* == 1 means add offset else subtract it */
unsigned pre_index :1; /* == 1 means [a,b] form else [a],b form */
unsigned immed :1; /* == 0 means immediate offset */
unsigned type :2; /* == TYPE_LDR_STR */
unsigned cond :4; /* one of COND_* defined above */
};
struct block_fmt {
unsigned mask :16; /* register mask */
unsigned base :4; /* register used as base of move */
unsigned is_load :1; /* == 1 for LDM */
unsigned writeback :1; /* == 1 means update base after move */
unsigned set :1; /* == 1 means set flags in pc if included in mask */
unsigned increment :1; /* == 1 means increment base register */
unsigned before :1; /* == 1 means inc/dec before each move */
unsigned is_block :1; /* == SUBTYPE_BLOCK */
unsigned type :2; /* == TYPE_BLOCK_BRANCH */
unsigned cond :4; /* one of COND_* defined above */
};
struct branch_fmt {
unsigned dest :24; /* destination of the branch */
unsigned link :1; /* branch with link (function call) */
unsigned is_branch :1; /* == SUBTYPE_BRANCH */
unsigned type :2; /* == TYPE_BLOCK_BRANCH */
unsigned cond :4; /* one of COND_* defined above */
};
#define ROUND_N 0
#define ROUND_P 1
#define ROUND_M 2
#define ROUND_Z 3
#define FLOAT2_MVF 0
#define FLOAT2_MNF 1
#define FLOAT2_ABS 2
#define FLOAT2_RND 3
#define FLOAT2_SQT 4
#define FLOAT2_LOG 5
#define FLOAT2_LGN 6
#define FLOAT2_EXP 7
#define FLOAT2_SIN 8
#define FLOAT2_COS 9
#define FLOAT2_TAN 10
#define FLOAT2_ASN 11
#define FLOAT2_ACS 12
#define FLOAT2_ATN 13
#define FLOAT3_ADF 0
#define FLOAT3_MUF 1
#define FLOAT3_SUF 2
#define FLOAT3_RSF 3
#define FLOAT3_DVF 4
#define FLOAT3_RDF 5
#define FLOAT3_POW 6
#define FLOAT3_RPW 7
#define FLOAT3_RMF 8
#define FLOAT3_FML 9
#define FLOAT3_FDV 10
#define FLOAT3_FRD 11
#define FLOAT3_POL 12
struct float2_fmt {
unsigned operand2 :3; /* second operand */
unsigned immed :1; /* == 1 if second operand is a constant */
unsigned pad1 :1; /* == 0 */
unsigned rounding :2; /* ROUND_* */
unsigned is_double :1; /* == 1 if precision is double (only if not extended) */
unsigned pad2 :4; /* == 1 */
unsigned dest :3; /* destination */
unsigned is_2_op :1; /* == 1 if 2 operand ins */
unsigned operand1 :3; /* first operand (only of is_2_op == 0) */
unsigned is_extended :1; /* == 1 if precision is extended */
unsigned opcode :4; /* FLOAT2_* or FLOAT3_* depending on is_2_op */
unsigned must_be_2 :2; /* == 2 */
unsigned type :2; /* == TYPE_SWI */
unsigned cond :4; /* COND_* */
};
struct swi_fmt {
unsigned argument :24; /* argument to SWI (syscall number) */
unsigned must_be_3 :2; /* == 3 */
unsigned type :2; /* == TYPE_SWI */
unsigned cond :4; /* one of COND_* defined above */
};
union insn_fmt {
struct generic_fmt generic;
struct arith_fmt arith;
struct ldr_str_fmt ldr_str;
struct block_fmt block;
struct branch_fmt branch;
struct swi_fmt swi;
unsigned long ins;
};
struct opcode {
unsigned long value, mask; /* recognise instruction if (op&mask)==value */
char *assembler; /* how to disassemble this instruction */
};
/* format of the assembler string :
%% %
%<bitfield>d print the bitfield in decimal
%<bitfield>x print the bitfield in hex
%<bitfield>r print as an ARM register
%<bitfield>f print a floating point constant if >7 else an fp register
%c print condition code (always bits 28-31)
%P print floating point precision in arithmetic insn
%Q print floating point precision in ldf/stf insn
%R print floating point rounding mode
%<bitnum>'c print specified char iff bit is one
%<bitnum>`c print specified char iff bit is zero
%<bitnum>?ab print a if bit is one else print b
%p print 'p' iff bits 12-15 are 15
%o print operand2 (immediate or register + shift)
%a print address for ldr/str instruction
%b print branch destination
%A print address for ldc/stc/ldf/stf instruction
%m print register mask for ldm/stm instruction
*/
static struct opcode opcodes[] = {
/* ARM instructions */
0x00000090, 0x0fe000f0, "mul%20's %12-15r, %16-19r, %0-3r",
0x00200090, 0x0fe000f0, "mla%20's %12-15r, %16-19r, %0-3r, %8-11r",
0x00000000, 0x0de00000, "and%c%20's %12-15r, %16-19r, %o",
0x00200000, 0x0de00000, "eor%c%20's %12-15r, %16-19r, %o",
0x00400000, 0x0de00000, "sub%c%20's %12-15r, %16-19r, %o",
0x00600000, 0x0de00000, "rsb%c%20's %12-15r, %16-19r, %o",
0x00800000, 0x0de00000, "add%c%20's %12-15r, %16-19r, %o",
0x00a00000, 0x0de00000, "adc%c%20's %12-15r, %16-19r, %o",
0x00c00000, 0x0de00000, "sbc%c%20's %12-15r, %16-19r, %o",
0x00e00000, 0x0de00000, "rsc%c%20's %12-15r, %16-19r, %o",
0x01000000, 0x0de00000, "tst%c%p %16-19r, %o",
0x01200000, 0x0de00000, "teq%c%p %16-19r, %o",
0x01400000, 0x0de00000, "cmp%c%p %16-19r, %o",
0x01600000, 0x0de00000, "cmn%c%p %16-19r, %o",
0x01800000, 0x0de00000, "orr%c%20's %12-15r, %16-19r, %o",
0x01a00000, 0x0de00000, "mov%c%20's %12-15r, %o",
0x01c00000, 0x0de00000, "bic%c%20's %12-15r, %16-19r, %o",
0x01e00000, 0x0de00000, "mvn%c%20's %12-15r, %o",
0x04000000, 0x0c100000, "str%c%22'b %12-15r, %a",
0x04100000, 0x0c100000, "ldr%c%22'b %12-15r, %a",
0x08000000, 0x0e100000, "stm%c%23?id%24?ba %16-19r%22`!, %m",
0x08100000, 0x0e100000, "ldm%c%23?id%24?ba %16-19r%22`!, %m%22'^",
0x0a000000, 0x0e000000, "b%c%24'l %b",
0x0f000000, 0x0f000000, "swi%c %0-23x",
/* Floating point coprocessor instructions */
0x0e000100, 0x0ff08f10, "adf%c%P%R %12-14f, %16-18f, %0-3f",
0x0e100100, 0x0ff08f10, "muf%c%P%R %12-14f, %16-18f, %0-3f",
0x0e200100, 0x0ff08f10, "suf%c%P%R %12-14f, %16-18f, %0-3f",
0x0e300100, 0x0ff08f10, "rsf%c%P%R %12-14f, %16-18f, %0-3f",
0x0e400100, 0x0ff08f10, "dvf%c%P%R %12-14f, %16-18f, %0-3f",
0x0e500100, 0x0ff08f10, "rdf%c%P%R %12-14f, %16-18f, %0-3f",
0x0e600100, 0x0ff08f10, "pow%c%P%R %12-14f, %16-18f, %0-3f",
0x0e700100, 0x0ff08f10, "rpw%c%P%R %12-14f, %16-18f, %0-3f",
0x0e800100, 0x0ff08f10, "rmf%c%P%R %12-14f, %16-18f, %0-3f",
0x0e900100, 0x0ff08f10, "fml%c%P%R %12-14f, %16-18f, %0-3f",
0x0ea00100, 0x0ff08f10, "fdv%c%P%R %12-14f, %16-18f, %0-3f",
0x0eb00100, 0x0ff08f10, "frd%c%P%R %12-14f, %16-18f, %0-3f",
0x0ec00100, 0x0ff08f10, "pol%c%P%R %12-14f, %16-18f, %0-3f",
0x0e008100, 0x0ff08f10, "mvf%c%P%R %12-14f, %0-3f",
0x0e108100, 0x0ff08f10, "mnf%c%P%R %12-14f, %0-3f",
0x0e208100, 0x0ff08f10, "abs%c%P%R %12-14f, %0-3f",
0x0e308100, 0x0ff08f10, "rnd%c%P%R %12-14f, %0-3f",
0x0e408100, 0x0ff08f10, "sqt%c%P%R %12-14f, %0-3f",
0x0e508100, 0x0ff08f10, "log%c%P%R %12-14f, %0-3f",
0x0e608100, 0x0ff08f10, "lgn%c%P%R %12-14f, %0-3f",
0x0e708100, 0x0ff08f10, "exp%c%P%R %12-14f, %0-3f",
0x0e808100, 0x0ff08f10, "sin%c%P%R %12-14f, %0-3f",
0x0e908100, 0x0ff08f10, "cos%c%P%R %12-14f, %0-3f",
0x0ea08100, 0x0ff08f10, "tan%c%P%R %12-14f, %0-3f",
0x0eb08100, 0x0ff08f10, "asn%c%P%R %12-14f, %0-3f",
0x0ec08100, 0x0ff08f10, "acs%c%P%R %12-14f, %0-3f",
0x0ed08100, 0x0ff08f10, "atn%c%P%R %12-14f, %0-3f",
0x0e000110, 0x0ff00f1f, "flt%c%P%R %16-18f, %12-15r",
0x0e100110, 0x0fff0f98, "fix%c%R %12-15r, %0-2f",
0x0e200110, 0x0fff0fff, "wfs%c %12-15r",
0x0e300110, 0x0fff0fff, "rfs%c %12-15r",
0x0e400110, 0x0fff0fff, "wfc%c %12-15r",
0x0e500110, 0x0fff0fff, "rfc%c %12-15r",
0x0e90f110, 0x0ff8fff0, "cmf%c %16-18f, %0-3f",
0x0eb0f110, 0x0ff8fff0, "cnf%c %16-18f, %0-3f",
0x0ed0f110, 0x0ff8fff0, "cmfe%c %16-18f, %0-3f",
0x0ef0f110, 0x0ff8fff0, "cnfe%c %16-18f, %0-3f",
0x0c000100, 0x0e100f00, "stf%c%Q %12-14f, %A",
0x0c100100, 0x0e100f00, "ldf%c%Q %12-14f, %A",
/* Generic coprocessor instructions */
0x0e000000, 0x0f000010, "cdp%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}",
0x0e000010, 0x0f100010, "mrc%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}",
0x0e100010, 0x0f100010, "mcr%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}",
0x0c000000, 0x0e100000, "stc%c%22`l %8-11d, cr%12-15d, %A",
0x0c100000, 0x0e100000, "ldc%c%22`l %8-11d, cr%12-15d, %A",
/* the rest */
0x00000000, 0x00000000, "undefined instruction %0-31x",
};
#define N_OPCODES (sizeof opcodes / sizeof opcodes[0])

1677
include/convx-opcode.h Executable file
View File

File diff suppressed because it is too large Load Diff

800
include/i386-opcode.h Executable file
View File

@ -0,0 +1,800 @@
/* i386-opcode.h -- Intel 80386 opcode table
Copyright (C) 1989, 1991, Free Software Foundation.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 1, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
/* $Id$ */
static const template i386_optab[] = {
#define _ None
/* move instructions */
{ "mov", 2, 0xa0, _, DW|NoModrm, Disp32, Acc, 0 },
{ "mov", 2, 0x88, _, DW|Modrm, Reg, Reg|Mem, 0 },
{ "mov", 2, 0xb0, _, ShortFormW, Imm, Reg, 0 },
{ "mov", 2, 0xc6, _, W|Modrm, Imm, Reg|Mem, 0 },
{ "mov", 2, 0x8c, _, D|Modrm, SReg3|SReg2, Reg16|Mem16, 0 },
/* move to/from control debug registers */
{ "mov", 2, 0x0f20, _, D|Modrm, Control, Reg32, 0},
{ "mov", 2, 0x0f21, _, D|Modrm, Debug, Reg32, 0},
{ "mov", 2, 0x0f24, _, D|Modrm, Test, Reg32, 0},
/* move with sign extend */
/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
conflict with the "movs" string move instruction. Thus,
{"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16|Reg32, 0},
is not kosher; we must seperate the two instructions. */
{"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg32, 0},
{"movsbw", 2, 0x660fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16, 0},
{"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, Reg16|Mem, Reg32, 0},
/* move with zero extend */
{"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16|Reg32, 0},
{"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, Reg16|Mem, Reg32, 0},
/* push instructions */
{"push", 1, 0x50, _, ShortForm, WordReg,0,0 },
{"push", 1, 0xff, 0x6, Modrm, WordReg|WordMem, 0, 0 },
{"push", 1, 0x6a, _, NoModrm, Imm8S, 0, 0},
{"push", 1, 0x68, _, NoModrm, Imm32, 0, 0},
{"push", 1, 0x06, _, Seg2ShortForm, SReg2,0,0 },
{"push", 1, 0x0fa0, _, Seg3ShortForm, SReg3,0,0 },
/* push all */
{"pusha", 0, 0x60, _, NoModrm, 0, 0, 0 },
/* pop instructions */
{"pop", 1, 0x58, _, ShortForm, WordReg,0,0 },
{"pop", 1, 0x8f, 0x0, Modrm, WordReg|WordMem, 0, 0 },
#define POP_SEG_SHORT 0x7
{"pop", 1, 0x07, _, Seg2ShortForm, SReg2,0,0 },
{"pop", 1, 0x0fa1, _, Seg3ShortForm, SReg3,0,0 },
/* pop all */
{"popa", 0, 0x61, _, NoModrm, 0, 0, 0 },
/* xchg exchange instructions
xchg commutes: we allow both operand orders */
{"xchg", 2, 0x90, _, ShortForm, WordReg, Acc, 0 },
{"xchg", 2, 0x90, _, ShortForm, Acc, WordReg, 0 },
{"xchg", 2, 0x86, _, W|Modrm, Reg, Reg|Mem, 0 },
{"xchg", 2, 0x86, _, W|Modrm, Reg|Mem, Reg, 0 },
/* in/out from ports */
{"in", 2, 0xe4, _, W|NoModrm, Imm8, Acc, 0 },
{"in", 2, 0xec, _, W|NoModrm, InOutPortReg, Acc, 0 },
{"out", 2, 0xe6, _, W|NoModrm, Acc, Imm8, 0 },
{"out", 2, 0xee, _, W|NoModrm, Acc, InOutPortReg, 0 },
/* load effective address */
{"lea", 2, 0x8d, _, Modrm, WordMem, WordReg, 0 },
/* load segment registers from memory */
{"lds", 2, 0xc5, _, Modrm, Mem, Reg32, 0},
{"les", 2, 0xc4, _, Modrm, Mem, Reg32, 0},
{"lfs", 2, 0x0fb4, _, Modrm, Mem, Reg32, 0},
{"lgs", 2, 0x0fb5, _, Modrm, Mem, Reg32, 0},
{"lss", 2, 0x0fb2, _, Modrm, Mem, Reg32, 0},
/* flags register instructions */
{"clc", 0, 0xf8, _, NoModrm, 0, 0, 0},
{"cld", 0, 0xfc, _, NoModrm, 0, 0, 0},
{"cli", 0, 0xfa, _, NoModrm, 0, 0, 0},
{"clts", 0, 0x0f06, _, NoModrm, 0, 0, 0},
{"cmc", 0, 0xf5, _, NoModrm, 0, 0, 0},
{"lahf", 0, 0x9f, _, NoModrm, 0, 0, 0},
{"sahf", 0, 0x9e, _, NoModrm, 0, 0, 0},
{"pushf", 0, 0x9c, _, NoModrm, 0, 0, 0},
{"popf", 0, 0x9d, _, NoModrm, 0, 0, 0},
{"stc", 0, 0xf9, _, NoModrm, 0, 0, 0},
{"std", 0, 0xfd, _, NoModrm, 0, 0, 0},
{"sti", 0, 0xfb, _, NoModrm, 0, 0, 0},
{"add", 2, 0x0, _, DW|Modrm, Reg, Reg|Mem, 0},
{"add", 2, 0x83, 0, Modrm, Imm8S, WordReg|WordMem, 0},
{"add", 2, 0x4, _, W|NoModrm, Imm, Acc, 0},
{"add", 2, 0x80, 0, W|Modrm, Imm, Reg|Mem, 0},
{"inc", 1, 0x40, _, ShortForm, WordReg, 0, 0},
{"inc", 1, 0xfe, 0, W|Modrm, Reg|Mem, 0, 0},
{"sub", 2, 0x28, _, DW|Modrm, Reg, Reg|Mem, 0},
{"sub", 2, 0x83, 5, Modrm, Imm8S, WordReg|WordMem, 0},
{"sub", 2, 0x2c, _, W|NoModrm, Imm, Acc, 0},
{"sub", 2, 0x80, 5, W|Modrm, Imm, Reg|Mem, 0},
{"dec", 1, 0x48, _, ShortForm, WordReg, 0, 0},
{"dec", 1, 0xfe, 1, W|Modrm, Reg|Mem, 0, 0},
{"sbb", 2, 0x18, _, DW|Modrm, Reg, Reg|Mem, 0},
{"sbb", 2, 0x83, 3, Modrm, Imm8S, WordReg|WordMem, 0},
{"sbb", 2, 0x1c, _, W|NoModrm, Imm, Acc, 0},
{"sbb", 2, 0x80, 3, W|Modrm, Imm, Reg|Mem, 0},
{"cmp", 2, 0x38, _, DW|Modrm, Reg, Reg|Mem, 0},
{"cmp", 2, 0x83, 7, Modrm, Imm8S, WordReg|WordMem, 0},
{"cmp", 2, 0x3c, _, W|NoModrm, Imm, Acc, 0},
{"cmp", 2, 0x80, 7, W|Modrm, Imm, Reg|Mem, 0},
{"test", 2, 0x84, _, W|Modrm, Reg|Mem, Reg, 0},
{"test", 2, 0x84, _, W|Modrm, Reg, Reg|Mem, 0},
{"test", 2, 0xa8, _, W|NoModrm, Imm, Acc, 0},
{"test", 2, 0xf6, 0, W|Modrm, Imm, Reg|Mem, 0},
{"and", 2, 0x20, _, DW|Modrm, Reg, Reg|Mem, 0},
{"and", 2, 0x83, 4, Modrm, Imm8S, WordReg|WordMem, 0},
{"and", 2, 0x24, _, W|NoModrm, Imm, Acc, 0},
{"and", 2, 0x80, 4, W|Modrm, Imm, Reg|Mem, 0},
{"or", 2, 0x08, _, DW|Modrm, Reg, Reg|Mem, 0},
{"or", 2, 0x83, 1, Modrm, Imm8S, WordReg|WordMem, 0},
{"or", 2, 0x0c, _, W|NoModrm, Imm, Acc, 0},
{"or", 2, 0x80, 1, W|Modrm, Imm, Reg|Mem, 0},
{"xor", 2, 0x30, _, DW|Modrm, Reg, Reg|Mem, 0},
{"xor", 2, 0x83, 6, Modrm, Imm8S, WordReg|WordMem, 0},
{"xor", 2, 0x34, _, W|NoModrm, Imm, Acc, 0},
{"xor", 2, 0x80, 6, W|Modrm, Imm, Reg|Mem, 0},
{"adc", 2, 0x10, _, DW|Modrm, Reg, Reg|Mem, 0},
{"adc", 2, 0x83, 2, Modrm, Imm8S, WordReg|WordMem, 0},
{"adc", 2, 0x14, _, W|NoModrm, Imm, Acc, 0},
{"adc", 2, 0x80, 2, W|Modrm, Imm, Reg|Mem, 0},
{"neg", 1, 0xf6, 3, W|Modrm, Reg|Mem, 0, 0},
{"not", 1, 0xf6, 2, W|Modrm, Reg|Mem, 0, 0},
{"aaa", 0, 0x37, _, NoModrm, 0, 0, 0},
{"aas", 0, 0x3f, _, NoModrm, 0, 0, 0},
{"daa", 0, 0x27, _, NoModrm, 0, 0, 0},
{"das", 0, 0x2f, _, NoModrm, 0, 0, 0},
{"aad", 0, 0xd50a, _, NoModrm, 0, 0, 0},
{"aam", 0, 0xd40a, _, NoModrm, 0, 0, 0},
/* conversion insns */
/* conversion: intel naming */
{"cbw", 0, 0x6698, _, NoModrm, 0, 0, 0},
{"cwd", 0, 0x6699, _, NoModrm, 0, 0, 0},
{"cwde", 0, 0x98, _, NoModrm, 0, 0, 0},
{"cdq", 0, 0x99, _, NoModrm, 0, 0, 0},
/* att naming */
{"cbtw", 0, 0x6698, _, NoModrm, 0, 0, 0},
{"cwtl", 0, 0x98, _, NoModrm, 0, 0, 0},
{"cwtd", 0, 0x6699, _, NoModrm, 0, 0, 0},
{"cltd", 0, 0x99, _, NoModrm, 0, 0, 0},
/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
expanding 64-bit multiplies, and *cannot* be selected to accomplish
'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
These multiplies can only be selected with single opearnd forms. */
{"mul", 1, 0xf6, 4, W|Modrm, Reg|Mem, 0, 0},
{"imul", 1, 0xf6, 5, W|Modrm, Reg|Mem, 0, 0},
/* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields.
These instructions are exceptions: 'imul $2, %eax, %ecx' would put
'%eax' in the reg field and '%ecx' in the regmem field if we did not
switch them. */
{"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0},
{"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, Imm8S, WordReg|Mem, WordReg},
{"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, Imm16|Imm32, WordReg|Mem, WordReg},
/*
imul with 2 operands mimicks imul with 3 by puting register both
in i.rm.reg & i.rm.regmem fields
*/
{"imul", 2, 0x6b, _, Modrm|imulKludge, Imm8S, WordReg, 0},
{"imul", 2, 0x69, _, Modrm|imulKludge, Imm16|Imm32, WordReg, 0},
{"div", 1, 0xf6, 6, W|Modrm, Reg|Mem, 0, 0},
{"div", 2, 0xf6, 6, W|Modrm, Reg|Mem, Acc, 0},
{"idiv", 1, 0xf6, 7, W|Modrm, Reg|Mem, 0, 0},
{"idiv", 2, 0xf6, 7, W|Modrm, Reg|Mem, Acc, 0},
{"rol", 2, 0xd0, 0, W|Modrm, Imm1, Reg|Mem, 0},
{"rol", 2, 0xc0, 0, W|Modrm, Imm8, Reg|Mem, 0},
{"rol", 2, 0xd2, 0, W|Modrm, ShiftCount, Reg|Mem, 0},
{"rol", 1, 0xd0, 0, W|Modrm, Reg|Mem, 0, 0},
{"ror", 2, 0xd0, 1, W|Modrm, Imm1, Reg|Mem, 0},
{"ror", 2, 0xc0, 1, W|Modrm, Imm8, Reg|Mem, 0},
{"ror", 2, 0xd2, 1, W|Modrm, ShiftCount, Reg|Mem, 0},
{"ror", 1, 0xd0, 1, W|Modrm, Reg|Mem, 0, 0},
{"rcl", 2, 0xd0, 2, W|Modrm, Imm1, Reg|Mem, 0},
{"rcl", 2, 0xc0, 2, W|Modrm, Imm8, Reg|Mem, 0},
{"rcl", 2, 0xd2, 2, W|Modrm, ShiftCount, Reg|Mem, 0},
{"rcl", 1, 0xd0, 2, W|Modrm, Reg|Mem, 0, 0},
{"rcr", 2, 0xd0, 3, W|Modrm, Imm1, Reg|Mem, 0},
{"rcr", 2, 0xc0, 3, W|Modrm, Imm8, Reg|Mem, 0},
{"rcr", 2, 0xd2, 3, W|Modrm, ShiftCount, Reg|Mem, 0},
{"rcr", 1, 0xd0, 3, W|Modrm, Reg|Mem, 0, 0},
{"sal", 2, 0xd0, 4, W|Modrm, Imm1, Reg|Mem, 0},
{"sal", 2, 0xc0, 4, W|Modrm, Imm8, Reg|Mem, 0},
{"sal", 2, 0xd2, 4, W|Modrm, ShiftCount, Reg|Mem, 0},
{"sal", 1, 0xd0, 4, W|Modrm, Reg|Mem, 0, 0},
{"shl", 2, 0xd0, 4, W|Modrm, Imm1, Reg|Mem, 0},
{"shl", 2, 0xc0, 4, W|Modrm, Imm8, Reg|Mem, 0},
{"shl", 2, 0xd2, 4, W|Modrm, ShiftCount, Reg|Mem, 0},
{"shl", 1, 0xd0, 4, W|Modrm, Reg|Mem, 0, 0},
{"shld", 3, 0x0fa4, _, Modrm, Imm8, WordReg, WordReg|Mem},
{"shld", 3, 0x0fa5, _, Modrm, ShiftCount, WordReg, WordReg|Mem},
{"shr", 2, 0xd0, 5, W|Modrm, Imm1, Reg|Mem, 0},
{"shr", 2, 0xc0, 5, W|Modrm, Imm8, Reg|Mem, 0},
{"shr", 2, 0xd2, 5, W|Modrm, ShiftCount, Reg|Mem, 0},
{"shr", 1, 0xd0, 5, W|Modrm, Reg|Mem, 0, 0},
{"shrd", 3, 0x0fac, _, Modrm, Imm8, WordReg, WordReg|Mem},
{"shrd", 3, 0x0fad, _, Modrm, ShiftCount, WordReg, WordReg|Mem},
{"sar", 2, 0xd0, 7, W|Modrm, Imm1, Reg|Mem, 0},
{"sar", 2, 0xc0, 7, W|Modrm, Imm8, Reg|Mem, 0},
{"sar", 2, 0xd2, 7, W|Modrm, ShiftCount, Reg|Mem, 0},
{"sar", 1, 0xd0, 7, W|Modrm, Reg|Mem, 0, 0},
/* control transfer instructions */
#define CALL_PC_RELATIVE 0xe8
{"call", 1, 0xe8, _, JumpDword, Disp32, 0, 0},
{"call", 1, 0xff, 2, Modrm, Reg|Mem|JumpAbsolute, 0, 0},
#define CALL_FAR_IMMEDIATE 0x9a
{"lcall", 2, 0x9a, _, JumpInterSegment, Imm16, Abs32, 0},
{"lcall", 1, 0xff, 3, Modrm, Mem, 0, 0},
#define JUMP_PC_RELATIVE 0xeb
{"jmp", 1, 0xeb, _, Jump, Disp, 0, 0},
{"jmp", 1, 0xff, 4, Modrm, Reg32|Mem|JumpAbsolute, 0, 0},
#define JUMP_FAR_IMMEDIATE 0xea
{"ljmp", 2, 0xea, _, JumpInterSegment, Imm16, Imm32, 0},
{"ljmp", 1, 0xff, 5, Modrm, Mem, 0, 0},
{"ret", 0, 0xc3, _, NoModrm, 0, 0, 0},
{"ret", 1, 0xc2, _, NoModrm, Imm16, 0, 0},
{"lret", 0, 0xcb, _, NoModrm, 0, 0, 0},
{"lret", 1, 0xca, _, NoModrm, Imm16, 0, 0},
{"enter", 2, 0xc8, _, NoModrm, Imm16, Imm8, 0},
{"leave", 0, 0xc9, _, NoModrm, 0, 0, 0},
/* conditional jumps */
{"jo", 1, 0x70, _, Jump, Disp, 0, 0},
{"jno", 1, 0x71, _, Jump, Disp, 0, 0},
{"jb", 1, 0x72, _, Jump, Disp, 0, 0},
{"jc", 1, 0x72, _, Jump, Disp, 0, 0},
{"jnae", 1, 0x72, _, Jump, Disp, 0, 0},
{"jnb", 1, 0x73, _, Jump, Disp, 0, 0},
{"jnc", 1, 0x73, _, Jump, Disp, 0, 0},
{"jae", 1, 0x73, _, Jump, Disp, 0, 0},
{"je", 1, 0x74, _, Jump, Disp, 0, 0},
{"jz", 1, 0x74, _, Jump, Disp, 0, 0},
{"jne", 1, 0x75, _, Jump, Disp, 0, 0},
{"jnz", 1, 0x75, _, Jump, Disp, 0, 0},
{"jbe", 1, 0x76, _, Jump, Disp, 0, 0},
{"jna", 1, 0x76, _, Jump, Disp, 0, 0},
{"jnbe", 1, 0x77, _, Jump, Disp, 0, 0},
{"ja", 1, 0x77, _, Jump, Disp, 0, 0},
{"js", 1, 0x78, _, Jump, Disp, 0, 0},
{"jns", 1, 0x79, _, Jump, Disp, 0, 0},
{"jp", 1, 0x7a, _, Jump, Disp, 0, 0},
{"jpe", 1, 0x7a, _, Jump, Disp, 0, 0},
{"jnp", 1, 0x7b, _, Jump, Disp, 0, 0},
{"jpo", 1, 0x7b, _, Jump, Disp, 0, 0},
{"jl", 1, 0x7c, _, Jump, Disp, 0, 0},
{"jnge", 1, 0x7c, _, Jump, Disp, 0, 0},
{"jnl", 1, 0x7d, _, Jump, Disp, 0, 0},
{"jge", 1, 0x7d, _, Jump, Disp, 0, 0},
{"jle", 1, 0x7e, _, Jump, Disp, 0, 0},
{"jng", 1, 0x7e, _, Jump, Disp, 0, 0},
{"jnle", 1, 0x7f, _, Jump, Disp, 0, 0},
{"jg", 1, 0x7f, _, Jump, Disp, 0, 0},
/* these turn into pseudo operations when disp is larger than 8 bits */
#define IS_JUMP_ON_CX_ZERO(o) \
(o == 0x67e3)
#define IS_JUMP_ON_ECX_ZERO(o) \
(o == 0xe3)
{"jcxz", 1, 0x67e3, _, JumpByte, Disp, 0, 0},
{"jecxz", 1, 0xe3, _, JumpByte, Disp, 0, 0},
#define IS_LOOP_ECX_TIMES(o) \
(o == 0xe2 || o == 0xe1 || o == 0xe0)
{"loop", 1, 0xe2, _, JumpByte, Disp, 0, 0},
{"loopz", 1, 0xe1, _, JumpByte, Disp, 0, 0},
{"loope", 1, 0xe1, _, JumpByte, Disp, 0, 0},
{"loopnz", 1, 0xe0, _, JumpByte, Disp, 0, 0},
{"loopne", 1, 0xe0, _, JumpByte, Disp, 0, 0},
/* set byte on flag instructions */
{"seto", 1, 0x0f90, 0, Modrm, Reg8|Mem, 0, 0},
{"setno", 1, 0x0f91, 0, Modrm, Reg8|Mem, 0, 0},
{"setb", 1, 0x0f92, 0, Modrm, Reg8|Mem, 0, 0},
{"setnae", 1, 0x0f92, 0, Modrm, Reg8|Mem, 0, 0},
{"setnb", 1, 0x0f93, 0, Modrm, Reg8|Mem, 0, 0},
{"setae", 1, 0x0f93, 0, Modrm, Reg8|Mem, 0, 0},
{"sete", 1, 0x0f94, 0, Modrm, Reg8|Mem, 0, 0},
{"setz", 1, 0x0f94, 0, Modrm, Reg8|Mem, 0, 0},
{"setne", 1, 0x0f95, 0, Modrm, Reg8|Mem, 0, 0},
{"setnz", 1, 0x0f95, 0, Modrm, Reg8|Mem, 0, 0},
{"setbe", 1, 0x0f96, 0, Modrm, Reg8|Mem, 0, 0},
{"setna", 1, 0x0f96, 0, Modrm, Reg8|Mem, 0, 0},
{"setnbe", 1, 0x0f97, 0, Modrm, Reg8|Mem, 0, 0},
{"seta", 1, 0x0f97, 0, Modrm, Reg8|Mem, 0, 0},
{"sets", 1, 0x0f98, 0, Modrm, Reg8|Mem, 0, 0},
{"setns", 1, 0x0f99, 0, Modrm, Reg8|Mem, 0, 0},
{"setp", 1, 0x0f9a, 0, Modrm, Reg8|Mem, 0, 0},
{"setpe", 1, 0x0f9a, 0, Modrm, Reg8|Mem, 0, 0},
{"setnp", 1, 0x0f9b, 0, Modrm, Reg8|Mem, 0, 0},
{"setpo", 1, 0x0f9b, 0, Modrm, Reg8|Mem, 0, 0},
{"setl", 1, 0x0f9c, 0, Modrm, Reg8|Mem, 0, 0},
{"setnge", 1, 0x0f9c, 0, Modrm, Reg8|Mem, 0, 0},
{"setnl", 1, 0x0f9d, 0, Modrm, Reg8|Mem, 0, 0},
{"setge", 1, 0x0f9d, 0, Modrm, Reg8|Mem, 0, 0},
{"setle", 1, 0x0f9e, 0, Modrm, Reg8|Mem, 0, 0},
{"setng", 1, 0x0f9e, 0, Modrm, Reg8|Mem, 0, 0},
{"setnle", 1, 0x0f9f, 0, Modrm, Reg8|Mem, 0, 0},
{"setg", 1, 0x0f9f, 0, Modrm, Reg8|Mem, 0, 0},
#define IS_STRING_INSTRUCTION(o) \
((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \
(o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \
(o) == 0xd7)
/* string manipulation */
{"cmps", 0, 0xa6, _, W|NoModrm, 0, 0, 0},
{"ins", 0, 0x6c, _, W|NoModrm, 0, 0, 0},
{"outs", 0, 0x6e, _, W|NoModrm, 0, 0, 0},
{"lods", 0, 0xac, _, W|NoModrm, 0, 0, 0},
{"movs", 0, 0xa4, _, W|NoModrm, 0, 0, 0},
{"scas", 0, 0xae, _, W|NoModrm, 0, 0, 0},
{"stos", 0, 0xaa, _, W|NoModrm, 0, 0, 0},
{"xlat", 0, 0xd7, _, NoModrm, 0, 0, 0},
/* bit manipulation */
{"bsf", 2, 0x0fbc, _, Modrm|ReverseRegRegmem, Reg|Mem, Reg, 0},
{"bsr", 2, 0x0fbd, _, Modrm|ReverseRegRegmem, Reg|Mem, Reg, 0},
{"bt", 2, 0x0fa3, _, Modrm, Reg, Reg|Mem, 0},
{"bt", 2, 0x0fba, 4, Modrm, Imm8, Reg|Mem, 0},
{"btc", 2, 0x0fbb, _, Modrm, Reg, Reg|Mem, 0},
{"btc", 2, 0x0fba, 7, Modrm, Imm8, Reg|Mem, 0},
{"btr", 2, 0x0fb3, _, Modrm, Reg, Reg|Mem, 0},
{"btr", 2, 0x0fba, 6, Modrm, Imm8, Reg|Mem, 0},
{"bts", 2, 0x0fab, _, Modrm, Reg, Reg|Mem, 0},
{"bts", 2, 0x0fba, 5, Modrm, Imm8, Reg|Mem, 0},
/* interrupts & op. sys insns */
/* See i386.c for conversion of 'int $3' into the special int 3 insn. */
#define INT_OPCODE 0xcd
#define INT3_OPCODE 0xcc
{"int", 1, 0xcd, _, NoModrm, Imm8, 0, 0},
{"int3", 0, 0xcc, _, NoModrm, 0, 0, 0},
{"into", 0, 0xce, _, NoModrm, 0, 0, 0},
{"iret", 0, 0xcf, _, NoModrm, 0, 0, 0},
{"boundl", 2, 0x62, _, Modrm, Reg32, Mem, 0},
{"boundw", 2, 0x6662, _, Modrm, Reg16, Mem, 0},
{"hlt", 0, 0xf4, _, NoModrm, 0, 0, 0},
{"wait", 0, 0x9b, _, NoModrm, 0, 0, 0},
/* nop is actually 'xchgl %eax, %eax' */
{"nop", 0, 0x90, _, NoModrm, 0, 0, 0},
/* protection control */
{"arpl", 2, 0x63, _, Modrm, Reg16, Reg16|Mem, 0},
{"lar", 2, 0x0f02, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0},
{"lgdt", 1, 0x0f01, 2, Modrm, Mem, 0, 0},
{"lidt", 1, 0x0f01, 3, Modrm, Mem, 0, 0},
{"lldt", 1, 0x0f00, 2, Modrm, WordReg|Mem, 0, 0},
{"lmsw", 1, 0x0f01, 6, Modrm, WordReg|Mem, 0, 0},
{"lsl", 2, 0x0f03, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0},
{"ltr", 1, 0x0f00, 3, Modrm, WordReg|Mem, 0, 0},
{"sgdt", 1, 0x0f01, 0, Modrm, Mem, 0, 0},
{"sidt", 1, 0x0f01, 1, Modrm, Mem, 0, 0},
{"sldt", 1, 0x0f00, 0, Modrm, WordReg|Mem, 0, 0},
{"smsw", 1, 0x0f01, 4, Modrm, WordReg|Mem, 0, 0},
{"str", 1, 0x0f00, 1, Modrm, Reg16|Mem, 0, 0},
{"verr", 1, 0x0f00, 4, Modrm, WordReg|Mem, 0, 0},
{"verw", 1, 0x0f00, 5, Modrm, WordReg|Mem, 0, 0},
/* floating point instructions */
/* load */
{"fld", 1, 0xd9c0, _, ShortForm, FloatReg, 0, 0}, /* register */
{"flds", 1, 0xd9, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem float */
{"fildl", 1, 0xdb, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem word */
{"fldl", 1, 0xdd, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem double */
{"fldl", 1, 0xd9c0, _, ShortForm, FloatReg, 0, 0}, /* register */
{"filds", 1, 0xdf, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem dword */
{"fildq", 1, 0xdf, 5, Modrm, Mem, 0, 0}, /* %st0 <-- mem qword */
{"fldt", 1, 0xdb, 5, Modrm, Mem, 0, 0}, /* %st0 <-- mem efloat */
{"fbld", 1, 0xdf, 4, Modrm, Mem, 0, 0}, /* %st0 <-- mem bcd */
/* store (no pop) */
{"fst", 1, 0xddd0, _, ShortForm, FloatReg, 0, 0}, /* register */
{"fsts", 1, 0xd9, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem float */
{"fistl", 1, 0xdb, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem dword */
{"fstl", 1, 0xdd, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem double */
{"fstl", 1, 0xddd0, _, ShortForm, FloatReg, 0, 0}, /* register */
{"fists", 1, 0xdf, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem word */
/* store (with pop) */
{"fstp", 1, 0xddd8, _, ShortForm, FloatReg, 0, 0}, /* register */
{"fstps", 1, 0xd9, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem float */
{"fistpl", 1, 0xdb, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem word */
{"fstpl", 1, 0xdd, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem double */
{"fstpl", 1, 0xddd8, _, ShortForm, FloatReg, 0, 0}, /* register */
{"fistps", 1, 0xdf, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem dword */
{"fistpq", 1, 0xdf, 7, Modrm, Mem, 0, 0}, /* %st0 --> mem qword */
{"fstpt", 1, 0xdb, 7, Modrm, Mem, 0, 0}, /* %st0 --> mem efloat */
{"fbstp", 1, 0xdf, 6, Modrm, Mem, 0, 0}, /* %st0 --> mem bcd */
/* exchange %st<n> with %st0 */
{"fxch", 1, 0xd9c8, _, ShortForm, FloatReg, 0, 0},
/* comparison (without pop) */
{"fcom", 1, 0xd8d0, _, ShortForm, FloatReg, 0, 0},
{"fcoms", 1, 0xd8, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem float */
{"ficoml", 1, 0xda, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem word */
{"fcoml", 1, 0xdc, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem double */
{"fcoml", 1, 0xd8d0, _, ShortForm, FloatReg, 0, 0},
{"ficoms", 1, 0xde, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem dword */
/* comparison (with pop) */
{"fcomp", 1, 0xd8d8, _, ShortForm, FloatReg, 0, 0},
{"fcomps", 1, 0xd8, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem float */
{"ficompl", 1, 0xda, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem word */
{"fcompl", 1, 0xdc, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem double */
{"fcompl", 1, 0xd8d8, _, ShortForm, FloatReg, 0, 0},
{"ficomps", 1, 0xde, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem dword */
{"fcompp", 0, 0xded9, _, NoModrm, 0, 0, 0}, /* compare %st0, %st1 & pop twice */
/* unordered comparison (with pop) */
{"fucom", 1, 0xdde0, _, ShortForm, FloatReg, 0, 0},
{"fucomp", 1, 0xdde8, _, ShortForm, FloatReg, 0, 0},
{"fucompp", 0, 0xdae9, _, NoModrm, 0, 0, 0}, /* ucompare %st0, %st1 & pop twice */
{"ftst", 0, 0xd9e4, _, NoModrm, 0, 0, 0}, /* test %st0 */
{"fxam", 0, 0xd9e5, _, NoModrm, 0, 0, 0}, /* examine %st0 */
/* load constants into %st0 */
{"fld1", 0, 0xd9e8, _, NoModrm, 0, 0, 0}, /* %st0 <-- 1.0 */
{"fldl2t", 0, 0xd9e9, _, NoModrm, 0, 0, 0}, /* %st0 <-- log2(10) */
{"fldl2e", 0, 0xd9ea, _, NoModrm, 0, 0, 0}, /* %st0 <-- log2(e) */
{"fldpi", 0, 0xd9eb, _, NoModrm, 0, 0, 0}, /* %st0 <-- pi */
{"fldlg2", 0, 0xd9ec, _, NoModrm, 0, 0, 0}, /* %st0 <-- log10(2) */
{"fldln2", 0, 0xd9ed, _, NoModrm, 0, 0, 0}, /* %st0 <-- ln(2) */
{"fldz", 0, 0xd9ee, _, NoModrm, 0, 0, 0}, /* %st0 <-- 0.0 */
/* arithmetic */
/* add */
{"fadd", 1, 0xd8c0, _, ShortForm, FloatReg, 0, 0},
{"fadd", 2, 0xd8c0, _, ShortForm|FloatD, FloatReg, FloatAcc, 0},
{"fadd", 0, 0xdcc1, _, NoModrm, 0, 0, 0}, /* alias for fadd %st, %st(1) */
{"faddp", 1, 0xdac0, _, ShortForm, FloatReg, 0, 0},
{"faddp", 2, 0xdac0, _, ShortForm|FloatD, FloatReg, FloatAcc, 0},
{"faddp", 0, 0xdec1, _, NoModrm, 0, 0, 0}, /* alias for faddp %st, %st(1) */
{"fadds", 1, 0xd8, 0, Modrm, Mem, 0, 0},
{"fiaddl", 1, 0xda, 0, Modrm, Mem, 0, 0},
{"faddl", 1, 0xdc, 0, Modrm, Mem, 0, 0},
{"fiadds", 1, 0xde, 0, Modrm, Mem, 0, 0},
/* sub */
/* Note: intel has decided that certain of these operations are reversed
in assembler syntax. */
{"fsub", 1, 0xd8e0, _, ShortForm, FloatReg, 0, 0},
{"fsub", 2, 0xd8e0, _, ShortForm, FloatReg, FloatAcc, 0},
#ifdef NON_BROKEN_OPCODES
{"fsub", 2, 0xdce8, _, ShortForm, FloatAcc, FloatReg, 0},
#else
{"fsub", 2, 0xdce0, _, ShortForm, FloatAcc, FloatReg, 0},
#endif
{"fsub", 0, 0xdce1, _, NoModrm, 0, 0, 0},
{"fsubp", 1, 0xdae0, _, ShortForm, FloatReg, 0, 0},
{"fsubp", 2, 0xdae0, _, ShortForm, FloatReg, FloatAcc, 0},
#ifdef NON_BROKEN_OPCODES
{"fsubp", 2, 0xdee8, _, ShortForm, FloatAcc, FloatReg, 0},
#else
{"fsubp", 2, 0xdee0, _, ShortForm, FloatAcc, FloatReg, 0},
#endif
{"fsubp", 0, 0xdee1, _, NoModrm, 0, 0, 0},
{"fsubs", 1, 0xd8, 4, Modrm, Mem, 0, 0},
{"fisubl", 1, 0xda, 4, Modrm, Mem, 0, 0},
{"fsubl", 1, 0xdc, 4, Modrm, Mem, 0, 0},
{"fisubs", 1, 0xde, 4, Modrm, Mem, 0, 0},
/* sub reverse */
{"fsubr", 1, 0xd8e8, _, ShortForm, FloatReg, 0, 0},
{"fsubr", 2, 0xd8e8, _, ShortForm, FloatReg, FloatAcc, 0},
#ifdef NON_BROKEN_OPCODES
{"fsubr", 2, 0xdce0, _, ShortForm, FloatAcc, FloatReg, 0},
#else
{"fsubr", 2, 0xdce8, _, ShortForm, FloatAcc, FloatReg, 0},
#endif
{"fsubr", 0, 0xdce9, _, NoModrm, 0, 0, 0},
{"fsubrp", 1, 0xdae8, _, ShortForm, FloatReg, 0, 0},
{"fsubrp", 2, 0xdae8, _, ShortForm, FloatReg, FloatAcc, 0},
#ifdef NON_BROKEN_OPCODES
{"fsubrp", 2, 0xdee0, _, ShortForm, FloatAcc, FloatReg, 0},
#else
{"fsubrp", 2, 0xdee8, _, ShortForm, FloatAcc, FloatReg, 0},
#endif
{"fsubrp", 0, 0xdee9, _, NoModrm, 0, 0, 0},
{"fsubrs", 1, 0xd8, 5, Modrm, Mem, 0, 0},
{"fisubrl", 1, 0xda, 5, Modrm, Mem, 0, 0},
{"fsubrl", 1, 0xdc, 5, Modrm, Mem, 0, 0},
{"fisubrs", 1, 0xde, 5, Modrm, Mem, 0, 0},
/* mul */
{"fmul", 1, 0xd8c8, _, ShortForm, FloatReg, 0, 0},
{"fmul", 2, 0xd8c8, _, ShortForm|FloatD, FloatReg, FloatAcc, 0},
{"fmul", 0, 0xdcc9, _, NoModrm, 0, 0, 0},
{"fmulp", 1, 0xdac8, _, ShortForm, FloatReg, 0, 0},
{"fmulp", 2, 0xdac8, _, ShortForm|FloatD, FloatReg, FloatAcc, 0},
{"fmulp", 0, 0xdec9, _, NoModrm, 0, 0, 0},
{"fmuls", 1, 0xd8, 1, Modrm, Mem, 0, 0},
{"fimull", 1, 0xda, 1, Modrm, Mem, 0, 0},
{"fmull", 1, 0xdc, 1, Modrm, Mem, 0, 0},
{"fimuls", 1, 0xde, 1, Modrm, Mem, 0, 0},
/* div */
/* Note: intel has decided that certain of these operations are reversed
in assembler syntax. */
{"fdiv", 1, 0xd8f0, _, ShortForm, FloatReg, 0, 0},
{"fdiv", 2, 0xd8f0, _, ShortForm, FloatReg, FloatAcc, 0},
#ifdef NON_BROKEN_OPCODES
{"fdiv", 2, 0xdcf8, _, ShortForm, FloatAcc, FloatReg, 0},
#else
{"fdiv", 2, 0xdcf0, _, ShortForm, FloatAcc, FloatReg, 0},
#endif
{"fdiv", 0, 0xdcf1, _, NoModrm, 0, 0, 0},
{"fdivp", 1, 0xdaf0, _, ShortForm, FloatReg, 0, 0},
{"fdivp", 2, 0xdaf0, _, ShortForm, FloatReg, FloatAcc, 0},
#ifdef NON_BROKEN_OPCODES
{"fdivp", 2, 0xdef8, _, ShortForm, FloatAcc, FloatReg, 0},
#else
{"fdivp", 2, 0xdef0, _, ShortForm, FloatAcc, FloatReg, 0},
#endif
{"fdivp", 0, 0xdef1, _, NoModrm, 0, 0, 0},
{"fdivs", 1, 0xd8, 6, Modrm, Mem, 0, 0},
{"fidivl", 1, 0xda, 6, Modrm, Mem, 0, 0},
{"fdivl", 1, 0xdc, 6, Modrm, Mem, 0, 0},
{"fidivs", 1, 0xde, 6, Modrm, Mem, 0, 0},
/* div reverse */
{"fdivr", 1, 0xd8f8, _, ShortForm, FloatReg, 0, 0},
{"fdivr", 2, 0xd8f8, _, ShortForm, FloatReg, FloatAcc, 0},
#ifdef NON_BROKEN_OPCODES
{"fdivr", 2, 0xdcf0, _, ShortForm, FloatAcc, FloatReg, 0},
#else
{"fdivr", 2, 0xdcf8, _, ShortForm, FloatAcc, FloatReg, 0},
#endif
{"fdivr", 0, 0xdcf9, _, NoModrm, 0, 0, 0},
{"fdivrp", 1, 0xdaf8, _, ShortForm, FloatReg, 0, 0},
{"fdivrp", 2, 0xdaf8, _, ShortForm, FloatReg, FloatAcc, 0},
#ifdef NON_BROKEN_OPCODES
{"fdivrp", 2, 0xdef0, _, ShortForm, FloatAcc, FloatReg, 0},
#else
{"fdivrp", 2, 0xdef8, _, ShortForm, FloatAcc, FloatReg, 0},
#endif
{"fdivrp", 0, 0xdef9, _, NoModrm, 0, 0, 0},
{"fdivrs", 1, 0xd8, 7, Modrm, Mem, 0, 0},
{"fidivrl", 1, 0xda, 7, Modrm, Mem, 0, 0},
{"fdivrl", 1, 0xdc, 7, Modrm, Mem, 0, 0},
{"fidivrs", 1, 0xde, 7, Modrm, Mem, 0, 0},
{"f2xm1", 0, 0xd9f0, _, NoModrm, 0, 0, 0},
{"fyl2x", 0, 0xd9f1, _, NoModrm, 0, 0, 0},
{"fptan", 0, 0xd9f2, _, NoModrm, 0, 0, 0},
{"fpatan", 0, 0xd9f3, _, NoModrm, 0, 0, 0},
{"fxtract", 0, 0xd9f4, _, NoModrm, 0, 0, 0},
{"fprem1", 0, 0xd9f5, _, NoModrm, 0, 0, 0},
{"fdecstp", 0, 0xd9f6, _, NoModrm, 0, 0, 0},
{"fincstp", 0, 0xd9f7, _, NoModrm, 0, 0, 0},
{"fprem", 0, 0xd9f8, _, NoModrm, 0, 0, 0},
{"fyl2xp1", 0, 0xd9f9, _, NoModrm, 0, 0, 0},
{"fsqrt", 0, 0xd9fa, _, NoModrm, 0, 0, 0},
{"fsincos", 0, 0xd9fb, _, NoModrm, 0, 0, 0},
{"frndint", 0, 0xd9fc, _, NoModrm, 0, 0, 0},
{"fscale", 0, 0xd9fd, _, NoModrm, 0, 0, 0},
{"fsin", 0, 0xd9fe, _, NoModrm, 0, 0, 0},
{"fcos", 0, 0xd9ff, _, NoModrm, 0, 0, 0},
{"fchs", 0, 0xd9e0, _, NoModrm, 0, 0, 0},
{"fabs", 0, 0xd9e1, _, NoModrm, 0, 0, 0},
/* processor control */
{"fninit", 0, 0xdbe3, _, NoModrm, 0, 0, 0},
{"finit", 0, 0xdbe3, _, NoModrm, 0, 0, 0},
{"fldcw", 1, 0xd9, 5, Modrm, Mem, 0, 0},
{"fnstcw", 1, 0xd9, 7, Modrm, Mem, 0, 0},
{"fstcw", 1, 0xd9, 7, Modrm, Mem, 0, 0},
{"fnstsw", 1, 0xdfe0, _, NoModrm, Acc, 0, 0},
{"fnstsw", 1, 0xdd, 7, Modrm, Mem, 0, 0},
{"fnstsw", 0, 0xdfe0, _, NoModrm, 0, 0, 0},
{"fstsw", 1, 0xdfe0, _, NoModrm, Acc, 0, 0},
{"fstsw", 1, 0xdd, 7, Modrm, Mem, 0, 0},
{"fstsw", 0, 0xdfe0, _, NoModrm, 0, 0, 0},
{"fnclex", 0, 0xdbe2, _, NoModrm, 0, 0, 0},
{"fclex", 0, 0xdbe2, _, NoModrm, 0, 0, 0},
/*
We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor
instructions; i'm not sure how to add them or how they are different.
My 386/387 book offers no details about this.
*/
{"fnstenv", 1, 0xd9, 6, Modrm, Mem, 0, 0},
{"fstenv", 1, 0xd9, 6, Modrm, Mem, 0, 0},
{"fldenv", 1, 0xd9, 4, Modrm, Mem, 0, 0},
{"fnsave", 1, 0xdd, 6, Modrm, Mem, 0, 0},
{"fsave", 1, 0xdd, 6, Modrm, Mem, 0, 0},
{"frstor", 1, 0xdd, 4, Modrm, Mem, 0, 0},
{"ffree", 1, 0xddc0, _, ShortForm, FloatReg, 0, 0},
{"fnop", 0, 0xd9d0, _, NoModrm, 0, 0, 0},
{"fwait", 0, 0x9b, _, NoModrm, 0, 0, 0},
/*
opcode prefixes; we allow them as seperate insns too
(see prefix table below)
*/
{"aword", 0, 0x67, _, NoModrm, 0, 0, 0},
{"word", 0, 0x66, _, NoModrm, 0, 0, 0},
{"lock", 0, 0xf0, _, NoModrm, 0, 0, 0},
{"cs", 0, 0x2e, _, NoModrm, 0, 0, 0},
{"ds", 0, 0x3e, _, NoModrm, 0, 0, 0},
{"es", 0, 0x26, _, NoModrm, 0, 0, 0},
{"fs", 0, 0x64, _, NoModrm, 0, 0, 0},
{"gs", 0, 0x65, _, NoModrm, 0, 0, 0},
{"ss", 0, 0x36, _, NoModrm, 0, 0, 0},
{"rep", 0, 0xf3, _, NoModrm, 0, 0, 0},
{"repe", 0, 0xf3, _, NoModrm, 0, 0, 0},
{ "repne", 0, 0xf2, _, NoModrm, 0, 0, 0},
{"", 0, 0, 0, 0, 0, 0, 0} /* sentinal */
};
#undef _
static const template *i386_optab_end
= i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]);
/* 386 register table */
static const reg_entry i386_regtab[] = {
/* 8 bit regs */
{"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2},
{"bl", Reg8, 3},
{"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7},
/* 16 bit regs */
{"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3},
{"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7},
/* 32 bit regs */
{"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3},
{"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7},
/* segment registers */
{"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2},
{"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5},
/* control registers */
{"cr0", Control, 0}, {"cr2", Control, 2}, {"cr3", Control, 3},
/* debug registers */
{"db0", Debug, 0}, {"db1", Debug, 1}, {"db2", Debug, 2},
{"db3", Debug, 3}, {"db6", Debug, 6}, {"db7", Debug, 7},
/* test registers */
{"tr6", Test, 6}, {"tr7", Test, 7},
/* float registers */
{"st(0)", FloatReg|FloatAcc, 0},
{"st", FloatReg|FloatAcc, 0},
{"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2},
{"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5},
{"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7}
};
#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
static const reg_entry *i386_regtab_end
= i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]);
/* segment stuff */
static const seg_entry cs = { "cs", 0x2e };
static const seg_entry ds = { "ds", 0x3e };
static const seg_entry ss = { "ss", 0x36 };
static const seg_entry es = { "es", 0x26 };
static const seg_entry fs = { "fs", 0x64 };
static const seg_entry gs = { "gs", 0x65 };
static const seg_entry null = { "", 0x0 };
/*
This table is used to store the default segment register implied by all
possible memory addressing modes.
It is indexed by the mode & modrm entries of the modrm byte as follows:
index = (mode<<3) | modrm;
*/
static const seg_entry *one_byte_segment_defaults[] = {
/* mode 0 */
&ds, &ds, &ds, &ds, &null, &ds, &ds, &ds,
/* mode 1 */
&ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
/* mode 2 */
&ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
/* mode 3 --- not a memory reference; never referenced */
};
static const seg_entry *two_byte_segment_defaults[] = {
/* mode 0 */
&ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
/* mode 1 */
&ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
/* mode 2 */
&ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
/* mode 3 --- not a memory reference; never referenced */
};
static const prefix_entry i386_prefixtab[] = {
{ "addr16", 0x67 }, /* address size prefix ==> 16bit addressing
* (How is this useful?) */
#define WORD_PREFIX_OPCODE 0x66
{ "data16", 0x66 }, /* operand size prefix */
{ "lock", 0xf0 }, /* bus lock prefix */
{ "wait", 0x9b }, /* wait for coprocessor */
{ "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */
{ "es", 0x26 }, { "fs", 0x64 },
{ "gs", 0x65 }, { "ss", 0x36 },
/* REPE & REPNE used to detect rep/repne with a non-string instruction */
#define REPNE 0xf2
#define REPE 0xf3
{ "rep", 0xf3 }, { "repe", 0xf3 }, /* repeat string instructions */
{ "repne", 0xf2 }
};
static const prefix_entry *i386_prefixtab_end
= i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]);
/* end of i386-opcode.h */

491
include/i860-opcode.h Executable file
View File

@ -0,0 +1,491 @@
/* Table of opcodes for the i860.
Copyright (C) 1989 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
GAS/GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 1, or (at your option)
any later version.
GAS/GDB is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS or GDB; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
#if !defined(__STDC__) && !defined(const)
#define const
#endif
/*
* Structure of an opcode table entry.
*/
struct i860_opcode
{
const char *name;
unsigned long match; /* Bits that must be set. */
unsigned long lose; /* Bits that must not be set. */
const char *args;
/* Nonzero if this is a possible expand-instruction. */
char expand;
};
enum expand_type
{
E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY
};
/*
All i860 opcodes are 32 bits, except for the pseudoinstructions
and the operations utilizing a 32-bit address expression, an
unsigned 32-bit constant, or a signed 32-bit constant.
These opcodes are expanded into a two-instruction sequence for
any situation where the immediate operand does not fit in 32 bits.
In the case of the add and subtract operations the expansion is
to a three-instruction sequence (ex: orh, or, adds). In cases
where the address is to be relocated, the instruction is
expanded to handle the worse case, this could be optimized at
the final link if the actual address were known.
The pseudoinstructions are: mov, fmov, pmov, nop, and fnop.
These instructions are implemented as a one or two instruction
sequence of other operations.
The match component is a mask saying which bits must match a
particular opcode in order for an instruction to be an instance
of that opcode.
The args component is a string containing one character
for each operand of the instruction.
Kinds of operands:
# Number used by optimizer. It is ignored.
1 src1 integer register.
2 src2 integer register.
d dest register.
c ctrlreg control register.
i 16 bit immediate.
I 16 bit immediate, aligned.
5 5 bit immediate.
l lbroff 26 bit PC relative immediate.
r sbroff 16 bit PC relative immediate.
s split 16 bit immediate.
S split 16 bit immediate, aligned.
e src1 floating point register.
f src2 floating point register.
g dest floating point register.
*/
/* The order of the opcodes in this table is significant:
* The assembler requires that all instances of the same mnemonic must be
consecutive. If they aren't, the assembler will bomb at runtime.
* The disassembler should not care about the order of the opcodes. */
static struct i860_opcode i860_opcodes[] =
{
/* REG-Format Instructions */
{ "ld.c", 0x30000000, 0xcc000000, "c,d", 0 }, /* ld.c csrc2,idest */
{ "ld.b", 0x00000000, 0xfc000000, "1(2),d", 0 }, /* ld.b isrc1(isrc2),idest */
{ "ld.b", 0x04000000, 0xf8000000, "I(2),d", E_ADDR }, /* ld.b #const(isrc2),idest */
{ "ld.s", 0x10000000, 0xec000001, "1(2),d", 0 }, /* ld.s isrc1(isrc2),idest */
{ "ld.s", 0x14000001, 0xe8000000, "I(2),d", E_ADDR }, /* ld.s #const(isrc2),idest */
{ "ld.l", 0x10000001, 0xec000000, "1(2),d", 0 }, /* ld.l isrc1(isrc2),idest */
{ "ld.l", 0x14000001, 0xe8000000, "I(2),d", E_ADDR }, /* ld.l #const(isrc2),idest */
{ "st.c", 0x38000000, 0xc4000000, "1,c", 0 }, /* st.c isrc1ni,csrc2 */
{ "st.b", 0x0c000000, 0xf0000000, "1,S(2)", E_ADDR }, /* st.b isrc1ni,#const(isrc2) */
{ "st.s", 0x1c000000, 0xe0000000, "1,S(2)", E_ADDR }, /* st.s isrc1ni,#const(isrc2) */
{ "st.l", 0x1c000001, 0xe0000000, "1,S(2)", E_ADDR }, /* st.l isrc1ni,#const(isrc2) */
{ "ixfr", 0x08000000, 0xf4000000, "1,g", 0 }, /* ixfr isrc1ni,fdest */
{ "fld.l", 0x20000002, 0xdc000001, "1(2),g", 0 }, /* fld.l isrc1(isrc2),fdest */
{ "fld.l", 0x24000002, 0xd8000001, "i(2),g", E_ADDR }, /* fld.l #const(isrc2),fdest */
{ "fld.l", 0x20000003, 0xdc000000, "1(2)++,g", 0 }, /* fld.l isrc1(isrc2)++,fdest */
{ "fld.l", 0x24000003, 0xd8000000, "i(2)++,g", E_ADDR }, /* fld.l #const(isrc2)++,fdest */
{ "fld.d", 0x20000000, 0xdc000007, "1(2),g", 0 }, /* fld.d isrc1(isrc2),fdest */
{ "fld.d", 0x24000000, 0xd8000007, "i(2),g", E_ADDR }, /* fld.d #const(isrc2),fdest */
{ "fld.d", 0x20000001, 0xdc000006, "1(2)++,g", 0 }, /* fld.d isrc1(isrc2)++,fdest */
{ "fld.d", 0x24000001, 0xd8000006, "i(2)++,g", E_ADDR }, /* fld.d #const(isrc2)++,fdest */
{ "fld.q", 0x20000004, 0xdc000003, "1(2),g", 0 }, /* fld.q isrc1(isrc2),fdest */
{ "fld.q", 0x24000004, 0xd8000003, "i(2),g", E_ADDR }, /* fld.q #const(isrc2),fdest */
{ "fld.q", 0x20000005, 0xdc000002, "1(2)++,g", 0 }, /* fld.q isrc1(isrc2)++,fdest */
{ "fld.q", 0x24000005, 0xd8000002, "i(2)++,g", E_ADDR }, /* fld.q #const(isrc2)++,fdest */
{ "pfld.l", 0x60000000, 0x9c000003, "1(2),g", 0 }, /* pfld.l isrc1(isrc2),fdest */
{ "pfld.l", 0x64000000, 0x98000003, "i(2),g", E_ADDR }, /* pfld.l #const(isrc2),fdest */
{ "pfld.l", 0x60000001, 0x9c000002, "1(2)++,g", 0 }, /* pfld.l isrc1(isrc2)++,fdest */
{ "pfld.l", 0x64000001, 0x98000002, "i(2)++,g", E_ADDR }, /* pfld.l #const(isrc2)++,fdest */
{ "pfld.d", 0x60000000, 0x9c000007, "1(2),g", 0 }, /* pfld.d isrc1(isrc2),fdest */
{ "pfld.d", 0x64000000, 0x98000007, "i(2),g", E_ADDR }, /* pfld.d #const(isrc2),fdest */
{ "pfld.d", 0x60000001, 0x9c000006, "1(2)++,g", 0 }, /* pfld.d isrc1(isrc2)++,fdest */
{ "pfld.d", 0x64000001, 0x98000006, "i(2)++,g", E_ADDR }, /* pfld.d #const(isrc2)++,fdest */
{ "fst.l", 0x28000002, 0xd4000001, "g,1(2)", 0 }, /* fst.l fdest,isrc1(isrc2) */
{ "fst.l", 0x2c000002, 0xd0000001, "g,i(2)", E_ADDR }, /* fst.l fdest,#const(isrc2) */
{ "fst.l", 0x28000003, 0xd4000000, "g,1(2)++", 0 }, /* fst.l fdest,isrc1(isrc2)++ */
{ "fst.l", 0x2c000003, 0xd0000000, "g,i(2)++", E_ADDR }, /* fst.l fdest,#const(isrc2)++ */
{ "fst.d", 0x28000000, 0xd4000007, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */
{ "fst.d", 0x2c000000, 0xd0000007, "g,i(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */
{ "fst.d", 0x28000001, 0xd4000006, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */
{ "fst.d", 0x2c000001, 0xd0000006, "g,i(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */
{ "pst.d", 0x3c000000, 0xc0000007, "g,i(2)", E_ADDR }, /* pst.d fdest,#const(isrc2) */
{ "pst.d", 0x3c000001, 0xc0000006, "g,i(2)++", E_ADDR }, /* pst.d fdest,#const(isrc2)++ */
{ "addu", 0x80000000, 0x7c000000, "1,2,d", 0 }, /* addu isrc1,isrc2,idest */
{ "addu", 0x84000000, 0x78000000, "i,2,d", E_S32 }, /* addu #const,isrc2,idest */
{ "adds", 0x90000000, 0x6c000000, "1,2,d", 0 }, /* adds isrc1,isrc2,idest */
{ "adds", 0x94000000, 0x68000000, "i,2,d", E_S32 }, /* adds #const,isrc2,idest */
{ "subu", 0x88000000, 0x74000000, "1,2,d", 0 }, /* subu isrc1,isrc2,idest */
{ "subu", 0x8c000000, 0x70000000, "i,2,d", E_S32 }, /* subu #const,isrc2,idest */
{ "subs", 0x98000000, 0x64000000, "1,2,d", 0 }, /* subs isrc1,isrc2,idest */
{ "subs", 0x9c000000, 0x60000000, "i,2,d", E_S32 }, /* subs #const,isrc2,idest */
{ "shl", 0xa0000000, 0x5c000000, "1,2,d", 0 }, /* shl isrc1,isrc2,idest */
{ "shl", 0xa4000000, 0x58000000, "i,2,d", 0 }, /* shl #const,isrc2,idest */
{ "shr", 0xa8000000, 0x54000000, "1,2,d", 0 }, /* shr isrc1,isrc2,idest */
{ "shr", 0xac000000, 0x50000000, "i,2,d", 0 }, /* shr #const,isrc2,idest */
{ "shrd", 0xb0000000, 0x4c000000, "1,2,d", 0 }, /* shrd isrc1,isrc2,idest */
{ "shra", 0xb8000000, 0x44000000, "1,2,d", 0 }, /* shra isrc1,isrc2,idest */
{ "shra", 0xbc000000, 0x40000000, "i,2,d", 0 }, /* shra #const,isrc2,idest */
{ "mov", 0xa0000000, 0x5c00f800, "2,d", 0 }, /* shl r0,isrc2,idest */
{ "mov", 0x94000000, 0x69e00000, "i,d", E_MOV }, /* adds #const,r0,idest */
{ "nop", 0xa0000000, 0x5ffff800, "", 0 }, /* shl r0,r0,r0 */
{ "fnop", 0xb0000000, 0x4ffff800, "", 0 }, /* shrd r0,r0,r0 */
{ "trap", 0x44000000, 0xb8000000, "1,2,d", 0 }, /* trap isrc1ni,isrc2,idest */
{ "flush", 0x34000000, 0xc81f0001, "i(2)", E_ADDR }, /* flush #const(isrc2) */
{ "flush", 0x34000001, 0xc81f0000, "i(2)++", E_ADDR }, /* flush #const(isrc2)++ */
{ "and", 0xc0000000, 0x3c000000, "1,2,d", 0 }, /* and isrc1,isrc2,idest */
{ "and", 0xc4000000, 0x38000000, "i,2,d", E_AND }, /* and #const,isrc2,idest */
{ "andh", 0xc8000000, 0x34000000, "1,2,d", 0 }, /* andh isrc1,isrc2,idest */
{ "andh", 0xcc000000, 0x30000000, "i,2,d", 0 }, /* andh #const,isrc2,idest */
{ "andnot", 0xd0000000, 0x2c000000, "1,2,d", 0 }, /* andnot isrc1,isrc2,idest */
{ "andnot", 0xd4000000, 0x28000000, "i,2,d", E_U32 }, /* andnot #const,isrc2,idest */
{ "andnoth", 0xd8000000, 0x24000000, "1,2,d", 0 }, /* andnoth isrc1,isrc2,idest */
{ "andnoth", 0xdc000000, 0x20000000, "i,2,d", 0 }, /* andnoth #const,isrc2,idest */
{ "or", 0xe0000000, 0x1c000000, "1,2,d", 0 }, /* or isrc1,isrc2,idest */
{ "or", 0xe4000000, 0x18000000, "i,2,d", E_U32 }, /* or #const,isrc2,idest */
{ "orh", 0xe8000000, 0x14000000, "1,2,d", 0 }, /* orh isrc1,isrc2,idest */
{ "orh", 0xec000000, 0x10000000, "i,2,d", 0 }, /* orh #const,isrc2,idest */
{ "xor", 0xf0000000, 0x0c000000, "1,2,d", 0 }, /* xor isrc1,isrc2,idest */
{ "xor", 0xf4000000, 0x08000000, "i,2,d", E_U32 }, /* xor #const,isrc2,idest */
{ "xorh", 0xf8000000, 0x04000000, "1,2,d", 0 }, /* xorh isrc1,isrc2,idest */
{ "xorh", 0xfc000000, 0x00000000, "i,2,d", 0 }, /* xorh #const,isrc2,idest */
{ "bte", 0x58000000, 0xa4000000, "1,2,s", 0 }, /* bte isrc1s,isrc2,sbroff */
{ "bte", 0x5c000000, 0xa0000000, "5,2,s", 0 }, /* bte #const5,isrc2,sbroff */
{ "btne", 0x50000000, 0xac000000, "1,2,s", 0 }, /* btne isrc1s,isrc2,sbroff */
{ "btne", 0x54000000, 0xa8000000, "5,2,s", 0 }, /* btne #const5,isrc2,sbroff */
{ "bla", 0xb4000000, 0x48000000, "1,2,s", E_DELAY }, /* bla isrc1s,isrc2,sbroff */
{ "bri", 0x40000000, 0xbc000000, "1", E_DELAY }, /* bri isrc1ni */
/* Core Escape Instruction Format */
{ "lock", 0x4c000001, 0xb000001e, "", 0 }, /* lock set BL in dirbase */
{ "calli", 0x4c000002, 0xb000001d, "1", E_DELAY }, /* calli isrc1ni */
{ "intovr", 0x4c000004, 0xb000001b, "", 0 }, /* intovr trap on integer overflow */
{ "unlock", 0x4c000007, 0xb0000018, "", 0 }, /* unlock clear BL in dirbase */
/* CTRL-Format Instructions */
{ "br", 0x68000000, 0x94000000, "l", E_DELAY }, /* br lbroff */
{ "call", 0x6c000000, 0x90000000, "l", E_DELAY }, /* call lbroff */
{ "bc", 0x70000000, 0x8c000000, "l", 0 }, /* bc lbroff */
{ "bc.t", 0x74000000, 0x88000000, "l", E_DELAY }, /* bc.t lbroff */
{ "bnc", 0x78000000, 0x84000000, "l", 0 }, /* bnc lbroff */
{ "bnc.t", 0x7c000000, 0x80000000, "l", E_DELAY }, /* bnc.t lbroff */
/* Floating Point Escape Instruction Format - pfam.p fsrc1,fsrc2,fdest */
{ "r2p1.ss", 0x48000400, 0xb40003ff, "e,f,g", 0 },
{ "r2p1.sd", 0x48000480, 0xb400037f, "e,f,g", 0 },
{ "r2p1.dd", 0x48000580, 0xb400027f, "e,f,g", 0 },
{ "r2pt.ss", 0x48000401, 0xb40003fe, "e,f,g", 0 },
{ "r2pt.sd", 0x48000481, 0xb400037e, "e,f,g", 0 },
{ "r2pt.dd", 0x48000581, 0xb400027e, "e,f,g", 0 },
{ "r2ap1.ss", 0x48000402, 0xb40003fd, "e,f,g", 0 },
{ "r2ap1.sd", 0x48000482, 0xb400037d, "e,f,g", 0 },
{ "r2ap1.dd", 0x48000582, 0xb400027d, "e,f,g", 0 },
{ "r2apt.ss", 0x48000403, 0xb40003fc, "e,f,g", 0 },
{ "r2apt.sd", 0x48000483, 0xb400037c, "e,f,g", 0 },
{ "r2apt.dd", 0x48000583, 0xb400027c, "e,f,g", 0 },
{ "i2p1.ss", 0x48000404, 0xb40003fb, "e,f,g", 0 },
{ "i2p1.sd", 0x48000484, 0xb400037b, "e,f,g", 0 },
{ "i2p1.dd", 0x48000584, 0xb400027b, "e,f,g", 0 },
{ "i2pt.ss", 0x48000405, 0xb40003fa, "e,f,g", 0 },
{ "i2pt.sd", 0x48000485, 0xb400037a, "e,f,g", 0 },
{ "i2pt.dd", 0x48000585, 0xb400027a, "e,f,g", 0 },
{ "i2ap1.ss", 0x48000406, 0xb40003f9, "e,f,g", 0 },
{ "i2ap1.sd", 0x48000486, 0xb4000379, "e,f,g", 0 },
{ "i2ap1.dd", 0x48000586, 0xb4000279, "e,f,g", 0 },
{ "i2apt.ss", 0x48000407, 0xb40003f8, "e,f,g", 0 },
{ "i2apt.sd", 0x48000487, 0xb4000378, "e,f,g", 0 },
{ "i2apt.dd", 0x48000587, 0xb4000278, "e,f,g", 0 },
{ "rat1p2.ss", 0x48000408, 0xb40003f7, "e,f,g", 0 },
{ "rat1p2.sd", 0x48000488, 0xb4000377, "e,f,g", 0 },
{ "rat1p2.dd", 0x48000588, 0xb4000277, "e,f,g", 0 },
{ "m12apm.ss", 0x48000409, 0xb40003f6, "e,f,g", 0 },
{ "m12apm.sd", 0x48000489, 0xb4000376, "e,f,g", 0 },
{ "m12apm.dd", 0x48000589, 0xb4000276, "e,f,g", 0 },
{ "ra1p2.ss", 0x4800040a, 0xb40003f5, "e,f,g", 0 },
{ "ra1p2.sd", 0x4800048a, 0xb4000375, "e,f,g", 0 },
{ "ra1p2.dd", 0x4800058a, 0xb4000275, "e,f,g", 0 },
{ "m12ttpa.ss", 0x4800040b, 0xb40003f4, "e,f,g", 0 },
{ "m12ttpa.sd", 0x4800048b, 0xb4000374, "e,f,g", 0 },
{ "m12ttpa.dd", 0x4800058b, 0xb4000274, "e,f,g", 0 },
{ "iat1p2.ss", 0x4800040c, 0xb40003f3, "e,f,g", 0 },
{ "iat1p2.sd", 0x4800048c, 0xb4000373, "e,f,g", 0 },
{ "iat1p2.dd", 0x4800058c, 0xb4000273, "e,f,g", 0 },
{ "m12tpm.ss", 0x4800040d, 0xb40003f2, "e,f,g", 0 },
{ "m12tpm.sd", 0x4800048d, 0xb4000372, "e,f,g", 0 },
{ "m12tpm.dd", 0x4800058d, 0xb4000272, "e,f,g", 0 },
{ "ia1p2.ss", 0x4800040e, 0xb40003f1, "e,f,g", 0 },
{ "ia1p2.sd", 0x4800048e, 0xb4000371, "e,f,g", 0 },
{ "ia1p2.dd", 0x4800058e, 0xb4000271, "e,f,g", 0 },
{ "m12tpa.ss", 0x4800040f, 0xb40003f0, "e,f,g", 0 },
{ "m12tpa.sd", 0x4800048f, 0xb4000370, "e,f,g", 0 },
{ "m12tpa.dd", 0x4800058f, 0xb4000270, "e,f,g", 0 },
/* Floating Point Escape Instruction Format - pfsm.p fsrc1,fsrc2,fdest */
{ "r2s1.ss", 0x48000410, 0xb40003ef, "e,f,g", 0 },
{ "r2s1.sd", 0x48000490, 0xb400036f, "e,f,g", 0 },
{ "r2s1.dd", 0x48000590, 0xb400026f, "e,f,g", 0 },
{ "r2st.ss", 0x48000411, 0xb40003ee, "e,f,g", 0 },
{ "r2st.sd", 0x48000491, 0xb400036e, "e,f,g", 0 },
{ "r2st.dd", 0x48000591, 0xb400026e, "e,f,g", 0 },
{ "r2as1.ss", 0x48000412, 0xb40003ed, "e,f,g", 0 },
{ "r2as1.sd", 0x48000492, 0xb400036d, "e,f,g", 0 },
{ "r2as1.dd", 0x48000592, 0xb400026d, "e,f,g", 0 },
{ "r2ast.ss", 0x48000413, 0xb40003ec, "e,f,g", 0 },
{ "r2ast.sd", 0x48000493, 0xb400036c, "e,f,g", 0 },
{ "r2ast.dd", 0x48000593, 0xb400026c, "e,f,g", 0 },
{ "i2s1.ss", 0x48000414, 0xb40003eb, "e,f,g", 0 },
{ "i2s1.sd", 0x48000494, 0xb400036b, "e,f,g", 0 },
{ "i2s1.dd", 0x48000594, 0xb400026b, "e,f,g", 0 },
{ "i2st.ss", 0x48000415, 0xb40003ea, "e,f,g", 0 },
{ "i2st.sd", 0x48000495, 0xb400036a, "e,f,g", 0 },
{ "i2st.dd", 0x48000595, 0xb400026a, "e,f,g", 0 },
{ "i2as1.ss", 0x48000416, 0xb40003e9, "e,f,g", 0 },
{ "i2as1.sd", 0x48000496, 0xb4000369, "e,f,g", 0 },
{ "i2as1.dd", 0x48000596, 0xb4000269, "e,f,g", 0 },
{ "i2ast.ss", 0x48000417, 0xb40003e8, "e,f,g", 0 },
{ "i2ast.sd", 0x48000497, 0xb4000368, "e,f,g", 0 },
{ "i2ast.dd", 0x48000597, 0xb4000268, "e,f,g", 0 },
{ "rat1s2.ss", 0x48000418, 0xb40003e7, "e,f,g", 0 },
{ "rat1s2.sd", 0x48000498, 0xb4000367, "e,f,g", 0 },
{ "rat1s2.dd", 0x48000598, 0xb4000267, "e,f,g", 0 },
{ "m12asm.ss", 0x48000419, 0xb40003e6, "e,f,g", 0 },
{ "m12asm.sd", 0x48000499, 0xb4000366, "e,f,g", 0 },
{ "m12asm.dd", 0x48000599, 0xb4000266, "e,f,g", 0 },
{ "ra1s2.ss", 0x4800041a, 0xb40003e5, "e,f,g", 0 },
{ "ra1s2.sd", 0x4800049a, 0xb4000365, "e,f,g", 0 },
{ "ra1s2.dd", 0x4800059a, 0xb4000265, "e,f,g", 0 },
{ "m12ttsa.ss", 0x4800041b, 0xb40003e4, "e,f,g", 0 },
{ "m12ttsa.sd", 0x4800049b, 0xb4000364, "e,f,g", 0 },
{ "m12ttsa.dd", 0x4800059b, 0xb4000264, "e,f,g", 0 },
{ "iat1s2.ss", 0x4800041c, 0xb40003e3, "e,f,g", 0 },
{ "iat1s2.sd", 0x4800049c, 0xb4000363, "e,f,g", 0 },
{ "iat1s2.dd", 0x4800059c, 0xb4000263, "e,f,g", 0 },
{ "m12tsm.ss", 0x4800041d, 0xb40003e2, "e,f,g", 0 },
{ "m12tsm.sd", 0x4800049d, 0xb4000362, "e,f,g", 0 },
{ "m12tsm.dd", 0x4800059d, 0xb4000262, "e,f,g", 0 },
{ "ia1s2.ss", 0x4800041e, 0xb40003e1, "e,f,g", 0 },
{ "ia1s2.sd", 0x4800049e, 0xb4000361, "e,f,g", 0 },
{ "ia1s2.dd", 0x4800059e, 0xb4000261, "e,f,g", 0 },
{ "m12tsa.ss", 0x4800041f, 0xb40003e0, "e,f,g", 0 },
{ "m12tsa.sd", 0x4800049f, 0xb4000360, "e,f,g", 0 },
{ "m12tsa.dd", 0x4800059f, 0xb4000260, "e,f,g", 0 },
/* Floating Point Escape Instruction Format - pfmam.p fsrc1,fsrc2,fdest */
{ "mr2p1.ss", 0x48000000, 0xb40007ff, "e,f,g", 0 },
{ "mr2p1.sd", 0x48000080, 0xb400077f, "e,f,g", 0 },
{ "mr2p1.dd", 0x48000180, 0xb400067f, "e,f,g", 0 },
{ "mr2pt.ss", 0x48000001, 0xb40007fe, "e,f,g", 0 },
{ "mr2pt.sd", 0x48000081, 0xb400077e, "e,f,g", 0 },
{ "mr2pt.dd", 0x48000181, 0xb400067e, "e,f,g", 0 },
{ "mr2mp1.ss", 0x48000002, 0xb40007fd, "e,f,g", 0 },
{ "mr2mp1.sd", 0x48000082, 0xb400077d, "e,f,g", 0 },
{ "mr2mp1.dd", 0x48000182, 0xb400067d, "e,f,g", 0 },
{ "mr2mpt.ss", 0x48000003, 0xb40007fc, "e,f,g", 0 },
{ "mr2mpt.sd", 0x48000083, 0xb400077c, "e,f,g", 0 },
{ "mr2mpt.dd", 0x48000183, 0xb400067c, "e,f,g", 0 },
{ "mi2p1.ss", 0x48000004, 0xb40007fb, "e,f,g", 0 },
{ "mi2p1.sd", 0x48000084, 0xb400077b, "e,f,g", 0 },
{ "mi2p1.dd", 0x48000184, 0xb400067b, "e,f,g", 0 },
{ "mi2pt.ss", 0x48000005, 0xb40007fa, "e,f,g", 0 },
{ "mi2pt.sd", 0x48000085, 0xb400077a, "e,f,g", 0 },
{ "mi2pt.dd", 0x48000185, 0xb400067a, "e,f,g", 0 },
{ "mi2mp1.ss", 0x48000006, 0xb40007f9, "e,f,g", 0 },
{ "mi2mp1.sd", 0x48000086, 0xb4000779, "e,f,g", 0 },
{ "mi2mp1.dd", 0x48000186, 0xb4000679, "e,f,g", 0 },
{ "mi2mpt.ss", 0x48000007, 0xb40007f8, "e,f,g", 0 },
{ "mi2mpt.sd", 0x48000087, 0xb4000778, "e,f,g", 0 },
{ "mi2mpt.dd", 0x48000187, 0xb4000678, "e,f,g", 0 },
{ "mrmt1p2.ss", 0x48000008, 0xb40007f7, "e,f,g", 0 },
{ "mrmt1p2.sd", 0x48000088, 0xb4000777, "e,f,g", 0 },
{ "mrmt1p2.dd", 0x48000188, 0xb4000677, "e,f,g", 0 },
{ "mm12mpm.ss", 0x48000009, 0xb40007f6, "e,f,g", 0 },
{ "mm12mpm.sd", 0x48000089, 0xb4000776, "e,f,g", 0 },
{ "mm12mpm.dd", 0x48000189, 0xb4000676, "e,f,g", 0 },
{ "mrm1p2.ss", 0x4800000a, 0xb40007f5, "e,f,g", 0 },
{ "mrm1p2.sd", 0x4800008a, 0xb4000775, "e,f,g", 0 },
{ "mrm1p2.dd", 0x4800018a, 0xb4000675, "e,f,g", 0 },
{ "mm12ttpm.ss",0x4800000b, 0xb40007f4, "e,f,g", 0 },
{ "mm12ttpm.sd",0x4800008b, 0xb4000774, "e,f,g", 0 },
{ "mm12ttpm.dd",0x4800018b, 0xb4000674, "e,f,g", 0 },
{ "mimt1p2.ss", 0x4800000c, 0xb40007f3, "e,f,g", 0 },
{ "mimt1p2.sd", 0x4800008c, 0xb4000773, "e,f,g", 0 },
{ "mimt1p2.dd", 0x4800018c, 0xb4000673, "e,f,g", 0 },
{ "mm12tpm.ss", 0x4800000d, 0xb40007f2, "e,f,g", 0 },
{ "mm12tpm.sd", 0x4800008d, 0xb4000772, "e,f,g", 0 },
{ "mm12tpm.dd", 0x4800018d, 0xb4000672, "e,f,g", 0 },
{ "mim1p2.ss", 0x4800000e, 0xb40007f1, "e,f,g", 0 },
{ "mim1p2.sd", 0x4800008e, 0xb4000771, "e,f,g", 0 },
{ "mim1p2.dd", 0x4800018e, 0xb4000671, "e,f,g", 0 },
/* Floating Point Escape Instruction Format - pfmsm.p fsrc1,fsrc2,fdest */
{ "mr2s1.ss", 0x48000010, 0xb40007ef, "e,f,g", 0 },
{ "mr2s1.sd", 0x48000090, 0xb400076f, "e,f,g", 0 },
{ "mr2s1.dd", 0x48000190, 0xb400066f, "e,f,g", 0 },
{ "mr2st.ss", 0x48000011, 0xb40007ee, "e,f,g", 0 },
{ "mr2st.sd", 0x48000091, 0xb400076e, "e,f,g", 0 },
{ "mr2st.dd", 0x48000191, 0xb400066e, "e,f,g", 0 },
{ "mr2ms1.ss", 0x48000012, 0xb40007ed, "e,f,g", 0 },
{ "mr2ms1.sd", 0x48000092, 0xb400076d, "e,f,g", 0 },
{ "mr2ms1.dd", 0x48000192, 0xb400066d, "e,f,g", 0 },
{ "mr2mst.ss", 0x48000013, 0xb40007ec, "e,f,g", 0 },
{ "mr2mst.sd", 0x48000093, 0xb400076c, "e,f,g", 0 },
{ "mr2mst.dd", 0x48000193, 0xb400066c, "e,f,g", 0 },
{ "mi2s1.ss", 0x48000014, 0xb40007eb, "e,f,g", 0 },
{ "mi2s1.sd", 0x48000094, 0xb400076b, "e,f,g", 0 },
{ "mi2s1.dd", 0x48000194, 0xb400066b, "e,f,g", 0 },
{ "mi2st.ss", 0x48000015, 0xb40007ea, "e,f,g", 0 },
{ "mi2st.sd", 0x48000095, 0xb400076a, "e,f,g", 0 },
{ "mi2st.dd", 0x48000195, 0xb400066a, "e,f,g", 0 },
{ "mi2ms1.ss", 0x48000016, 0xb40007e9, "e,f,g", 0 },
{ "mi2ms1.sd", 0x48000096, 0xb4000769, "e,f,g", 0 },
{ "mi2ms1.dd", 0x48000196, 0xb4000669, "e,f,g", 0 },
{ "mi2mst.ss", 0x48000017, 0xb40007e8, "e,f,g", 0 },
{ "mi2mst.sd", 0x48000097, 0xb4000768, "e,f,g", 0 },
{ "mi2mst.dd", 0x48000197, 0xb4000668, "e,f,g", 0 },
{ "mrmt1s2.ss", 0x48000018, 0xb40007e7, "e,f,g", 0 },
{ "mrmt1s2.sd", 0x48000098, 0xb4000767, "e,f,g", 0 },
{ "mrmt1s2.dd", 0x48000198, 0xb4000667, "e,f,g", 0 },
{ "mm12msm.ss", 0x48000019, 0xb40007e6, "e,f,g", 0 },
{ "mm12msm.sd", 0x48000099, 0xb4000766, "e,f,g", 0 },
{ "mm12msm.dd", 0x48000199, 0xb4000666, "e,f,g", 0 },
{ "mrm1s2.ss", 0x4800001a, 0xb40007e5, "e,f,g", 0 },
{ "mrm1s2.sd", 0x4800009a, 0xb4000765, "e,f,g", 0 },
{ "mrm1s2.dd", 0x4800019a, 0xb4000665, "e,f,g", 0 },
{ "mm12ttsm.ss",0x4800001b, 0xb40007e4, "e,f,g", 0 },
{ "mm12ttsm.sd",0x4800009b, 0xb4000764, "e,f,g", 0 },
{ "mm12ttsm.dd",0x4800019b, 0xb4000664, "e,f,g", 0 },
{ "mimt1s2.ss", 0x4800001c, 0xb40007e3, "e,f,g", 0 },
{ "mimt1s2.sd", 0x4800009c, 0xb4000763, "e,f,g", 0 },
{ "mimt1s2.dd", 0x4800019c, 0xb4000663, "e,f,g", 0 },
{ "mm12tsm.ss", 0x4800001d, 0xb40007e2, "e,f,g", 0 },
{ "mm12tsm.sd", 0x4800009d, 0xb4000762, "e,f,g", 0 },
{ "mm12tsm.dd", 0x4800019d, 0xb4000662, "e,f,g", 0 },
{ "mim1s2.ss", 0x4800001e, 0xb40007e1, "e,f,g", 0 },
{ "mim1s2.sd", 0x4800009e, 0xb4000761, "e,f,g", 0 },
{ "mim1s2.dd", 0x4800019e, 0xb4000661, "e,f,g", 0 },
{ "fmul.ss", 0x48000020, 0xb40007df, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
{ "fmul.sd", 0x480000a0, 0xb400075f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
{ "fmul.dd", 0x480001a0, 0xb400065f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
{ "pfmul.ss", 0x48000420, 0xb40003df, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */
{ "pfmul.sd", 0x480004a0, 0xb400035f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */
{ "pfmul.dd", 0x480005a0, 0xb400025f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */
{ "pfmul3.dd", 0x480005a4, 0xb400025b, "e,f,g", 0 }, /* pfmul3.p fsrc1,fsrc2,fdest */
{ "fmlow.dd", 0x480001a1, 0xb400065e, "e,f,g", 0 }, /* fmlow.dd fsrc1,fsrc2,fdest */
{ "frcp.ss", 0x48000022, 0xb40007dd, "f,g", 0 }, /* frcp.p fsrc2,fdest */
{ "frcp.sd", 0x480000a2, 0xb400075d, "f,g", 0 }, /* frcp.p fsrc2,fdest */
{ "frcp.dd", 0x480001a2, 0xb400065d, "f,g", 0 }, /* frcp.p fsrc2,fdest */
{ "frsqr.ss", 0x48000023, 0xb40007dc, "f,g", 0 }, /* frsqr.p fsrc2,fdest */
{ "frsqr.sd", 0x480000a3, 0xb400075c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */
{ "frsqr.dd", 0x480001a3, 0xb400065c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */
{ "fadd.ss", 0x48000030, 0xb40007cf, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */
{ "fadd.sd", 0x480000b0, 0xb400074f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */
{ "fadd.dd", 0x480001b0, 0xb400064f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */
{ "pfadd.ss", 0x48000430, 0xb40003cf, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */
{ "pfadd.sd", 0x480004b0, 0xb400034f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */
{ "pfadd.dd", 0x480005b0, 0xb400024f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */
{ "fsub.ss", 0x48000031, 0xb40007ce, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */
{ "fsub.sd", 0x480000b1, 0xb400074e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */
{ "fsub.dd", 0x480001b1, 0xb400064e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */
{ "pfsub.ss", 0x48000431, 0xb40003ce, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */
{ "pfsub.sd", 0x480004b1, 0xb400034e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */
{ "pfsub.dd", 0x480005b1, 0xb400024e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */
{ "fix.ss", 0x48000032, 0xb40007cd, "e,g", 0 }, /* fix.p fsrc1,fdest */
{ "fix.sd", 0x480000b2, 0xb400074d, "e,g", 0 }, /* fix.p fsrc1,fdest */
{ "fix.dd", 0x480001b2, 0xb400064d, "e,g", 0 }, /* fix.p fsrc1,fdest */
{ "pfix.ss", 0x48000432, 0xb40003cd, "e,g", 0 }, /* pfix.p fsrc1,fdest */
{ "pfix.sd", 0x480004b2, 0xb400034d, "e,g", 0 }, /* pfix.p fsrc1,fdest */
{ "pfix.dd", 0x480005b2, 0xb400024d, "e,g", 0 }, /* pfix.p fsrc1,fdest */
{ "famov.ss", 0x48000033, 0xb40007cc, "e,g", 0 }, /* famov.p fsrc1,fdest */
{ "famov.ds", 0x48000133, 0xb40006cc, "e,g", 0 }, /* famov.p fsrc1,fdest */
{ "famov.sd", 0x480000b3, 0xb400074c, "e,g", 0 }, /* famov.p fsrc1,fdest */
{ "famov.dd", 0x480001b3, 0xb400064c, "e,g", 0 }, /* famov.p fsrc1,fdest */
{ "pfamov.ss", 0x48000433, 0xb40003cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
{ "pfamov.ds", 0x48000533, 0xb40002cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
{ "pfamov.sd", 0x480004b3, 0xb400034c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
{ "pfamov.dd", 0x480005b3, 0xb400024c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
/* pfgt has R bit cleared; pfle has R bit set */
{ "pfgt.ss", 0x48000434, 0xb40003cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */
{ "pfgt.sd", 0x48000434, 0xb40003cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */
{ "pfgt.dd", 0x48000534, 0xb40002cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */
/* pfgt has R bit cleared; pfle has R bit set */
{ "pfle.ss", 0x480004b4, 0xb400034b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */
{ "pfle.sd", 0x480004b4, 0xb400034b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */
{ "pfle.dd", 0x480005b4, 0xb400024b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */
{ "ftrunc.ss", 0x4800003a, 0xb40007c5, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */
{ "ftrunc.sd", 0x480000ba, 0xb4000745, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */
{ "ftrunc.dd", 0x480001ba, 0xb4000645, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */
{ "pftrunc.ss", 0x4800043a, 0xb40003c5, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */
{ "pftrunc.sd", 0x480004ba, 0xb4000345, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */
{ "pftrunc.dd", 0x480005ba, 0xb4000245, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */
{ "fxfr", 0x48000040, 0xb40007bf, "e,d", 0 }, /* fxfr fsrc1,idest */
{ "fiadd.ss", 0x48000049, 0xb40007b6, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */
{ "fiadd.dd", 0x480001c9, 0xb4000636, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */
{ "pfiadd.ss", 0x48000449, 0xb40003b6, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */
{ "pfiadd.dd", 0x480005c9, 0xb4000236, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */
{ "fisub.ss", 0x4800004d, 0xb40007b2, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */
{ "fisub.dd", 0x480001cd, 0xb4000632, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */
{ "pfisub.ss", 0x4800044d, 0xb40003b2, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */
{ "pfisub.dd", 0x480005cd, 0xb4000232, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */
{ "fzchkl", 0x48000057, 0xb40007a8, "e,f,g", 0 }, /* fzchkl fsrc1,fsrc2,fdest */
{ "pfzchkl", 0x48000457, 0xb40003a8, "e,f,g", 0 }, /* pfzchkl fsrc1,fsrc2,fdest */
{ "fzchks", 0x4800005f, 0xb40007a0, "e,f,g", 0 }, /* fzchks fsrc1,fsrc2,fdest */
{ "pfzchks", 0x4800045f, 0xb40003a0, "e,f,g", 0 }, /* pfzchks fsrc1,fsrc2,fdest */
{ "faddp", 0x48000050, 0xb40007af, "e,f,g", 0 }, /* faddp fsrc1,fsrc2,fdest */
{ "pfaddp", 0x48000450, 0xb40003af, "e,f,g", 0 }, /* pfaddp fsrc1,fsrc2,fdest */
{ "faddz", 0x48000051, 0xb40007ae, "e,f,g", 0 }, /* faddz fsrc1,fsrc2,fdest */
{ "pfaddz", 0x48000451, 0xb40003ae, "e,f,g", 0 }, /* pfaddz fsrc1,fsrc2,fdest */
{ "form", 0x4800005a, 0xb40007a5, "e,g", 0 }, /* form fsrc1,fdest */
{ "pform", 0x4800045a, 0xb40003a5, "e,g", 0 }, /* pform fsrc1,fdest */
/* Floating point pseudo-instructions */
{ "fmov.ss", 0x48000049, 0xb7e007b6, "e,g", 0 }, /* fiadd.ss fsrc1,f0,fdest */
{ "fmov.dd", 0x480001c9, 0xb7e00636, "e,g", 0 }, /* fiadd.dd fsrc1,f0,fdest */
{ "fmov.sd", 0x480000b0, 0xb7e0074f, "e,g", 0 }, /* fadd.sd fsrc1,f0,fdest */
{ "fmov.ds", 0x48000130, 0xb7e006cf, "e,g", 0 }, /* fadd.ds fsrc1,f0,fdest */
{ "pfmov.ds", 0x48000530, 0xb73002cf, "e,g", 0 }, /* pfadd.ds fsrc1,f0,fdest */
{ "pfmov.dd", 0x480005c9, 0xb7e00236, "e,g", 0 }, /* pfiadd.dd fsrc1,f0,fdest */
};
#define NUMOPCODES ((sizeof i860_opcodes)/(sizeof i860_opcodes[0]))

434
include/i960-opcode.h Executable file
View File

@ -0,0 +1,434 @@
/* Basic 80960 instruction formats.
*
* The 'COJ' instructions are actually COBR instructions with the 'b' in
* the mnemonic replaced by a 'j'; they are ALWAYS "de-optimized" if necessary:
* if the displacement will not fit in 13 bits, the assembler will replace them
* with the corresponding compare and branch instructions.
*
* All of the 'MEMn' instructions are the same format; the 'n' in the name
* indicates the default index scale factor (the size of the datum operated on).
*
* The FBRA formats are not actually an instruction format. They are the
* "convenience directives" for branching on floating-point comparisons,
* each of which generates 2 instructions (a 'bno' and one other branch).
*
* The CALLJ format is not actually an instruction format. It indicates that
* the instruction generated (a CTRL-format 'call') should have its relocation
* specially flagged for link-time replacement with a 'bal' or 'calls' if
* appropriate.
*/
/* $Id$ */
#define CTRL 0
#define COBR 1
#define COJ 2
#define REG 3
#define MEM1 4
#define MEM2 5
#define MEM4 6
#define MEM8 7
#define MEM12 8
#define MEM16 9
#define FBRA 10
#define CALLJ 11
/* Masks for the mode bits in REG format instructions */
#define M1 0x0800
#define M2 0x1000
#define M3 0x2000
/* Generate the 12-bit opcode for a REG format instruction by placing the
* high 8 bits in instruction bits 24-31, the low 4 bits in instruction bits
* 7-10.
*/
#define REG_OPC(opc) ((opc & 0xff0) << 20) | ((opc & 0xf) << 7)
/* Generate a template for a REG format instruction: place the opcode bits
* in the appropriate fields and OR in mode bits for the operands that will not
* be used. I.e.,
* set m1=1, if src1 will not be used
* set m2=1, if src2 will not be used
* set m3=1, if dst will not be used
*
* Setting the "unused" mode bits to 1 speeds up instruction execution(!).
* The information is also useful to us because some 1-operand REG instructions
* use the src1 field, others the dst field; and some 2-operand REG instructions
* use src1/src2, others src1/dst. The set mode bits enable us to distinguish.
*/
#define R_0(opc) ( REG_OPC(opc) | M1 | M2 | M3 ) /* No operands */
#define R_1(opc) ( REG_OPC(opc) | M2 | M3 ) /* 1 operand: src1 */
#define R_1D(opc) ( REG_OPC(opc) | M1 | M2 ) /* 1 operand: dst */
#define R_2(opc) ( REG_OPC(opc) | M3 ) /* 2 ops: src1/src2 */
#define R_2D(opc) ( REG_OPC(opc) | M2 ) /* 2 ops: src1/dst */
#define R_3(opc) ( REG_OPC(opc) ) /* 3 operands */
/* DESCRIPTOR BYTES FOR REGISTER OPERANDS
*
* Interpret names as follows:
* R: global or local register only
* RS: global, local, or (if target allows) special-function register only
* RL: global or local register, or integer literal
* RSL: global, local, or (if target allows) special-function register;
* or integer literal
* F: global, local, or floating-point register
* FL: global, local, or floating-point register; or literal (including
* floating point)
*
* A number appended to a name indicates that registers must be aligned,
* as follows:
* 2: register number must be multiple of 2
* 4: register number must be multiple of 4
*/
#define SFR 0x10 /* Mask for the "sfr-OK" bit */
#define LIT 0x08 /* Mask for the "literal-OK" bit */
#define FP 0x04 /* Mask for "floating-point-OK" bit */
/* This macro ors the bits together. Note that 'align' is a mask
* for the low 0, 1, or 2 bits of the register number, as appropriate.
*/
#define OP(align,lit,fp,sfr) ( align | lit | fp | sfr )
#define R OP( 0, 0, 0, 0 )
#define RS OP( 0, 0, 0, SFR )
#define RL OP( 0, LIT, 0, 0 )
#define RSL OP( 0, LIT, 0, SFR )
#define F OP( 0, 0, FP, 0 )
#define FL OP( 0, LIT, FP, 0 )
#define R2 OP( 1, 0, 0, 0 )
#define RL2 OP( 1, LIT, 0, 0 )
#define F2 OP( 1, 0, FP, 0 )
#define FL2 OP( 1, LIT, FP, 0 )
#define R4 OP( 3, 0, 0, 0 )
#define RL4 OP( 3, LIT, 0, 0 )
#define F4 OP( 3, 0, FP, 0 )
#define FL4 OP( 3, LIT, FP, 0 )
#define M 0x7f /* Memory operand (MEMA & MEMB format instructions) */
/* Macros to extract info from the register operand descriptor byte 'od'.
*/
#define SFR_OK(od) (od & SFR) /* TRUE if sfr operand allowed */
#define LIT_OK(od) (od & LIT) /* TRUE if literal operand allowed */
#define FP_OK(od) (od & FP) /* TRUE if floating-point op allowed */
#define REG_ALIGN(od,n) ((od & 0x3 & n) == 0)
/* TRUE if reg #n is properly aligned */
#define MEMOP(od) (od == M) /* TRUE if operand is a memory operand*/
/* Description of a single i80960 instruction */
struct i960_opcode {
long opcode; /* 32 bits, constant fields filled in, rest zeroed */
char *name; /* Assembler mnemonic */
short iclass; /* Class: see #defines below */
char format; /* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ */
char num_ops; /* Number of operands */
char operand[3];/* Operand descriptors; same order as assembler instr */
};
/* Classes of 960 intructions:
* - each instruction falls into one class.
* - each target architecture supports one or more classes.
*
* EACH CONSTANT MUST CONTAIN 1 AND ONLY 1 SET BIT!: see targ_has_iclass().
*/
#define I_BASE 0x01 /* 80960 base instruction set */
#define I_CX 0x02 /* 80960Cx instruction */
#define I_DEC 0x04 /* Decimal instruction */
#define I_FP 0x08 /* Floating point instruction */
#define I_KX 0x10 /* 80960Kx instruction */
#define I_MIL 0x20 /* Military instruction */
#define I_CASIM 0x40 /* CA simulator instruction */
/******************************************************************************
*
* TABLE OF i960 INSTRUCTION DESCRIPTIONS
*
******************************************************************************/
const struct i960_opcode i960_opcodes[] = {
/* if a CTRL instruction has an operand, it's always a displacement */
{ 0x09000000, "callj", I_BASE, CALLJ, 1 },/*default=='call'*/
{ 0x08000000, "b", I_BASE, CTRL, 1 },
{ 0x09000000, "call", I_BASE, CTRL, 1 },
{ 0x0a000000, "ret", I_BASE, CTRL, 0 },
{ 0x0b000000, "bal", I_BASE, CTRL, 1 },
{ 0x10000000, "bno", I_BASE, CTRL, 1 },
{ 0x10000000, "bf", I_BASE, CTRL, 1 }, /* same as bno */
{ 0x10000000, "bru", I_BASE, CTRL, 1 }, /* same as bno */
{ 0x11000000, "bg", I_BASE, CTRL, 1 },
{ 0x11000000, "brg", I_BASE, CTRL, 1 }, /* same as bg */
{ 0x12000000, "be", I_BASE, CTRL, 1 },
{ 0x12000000, "bre", I_BASE, CTRL, 1 }, /* same as be */
{ 0x13000000, "bge", I_BASE, CTRL, 1 },
{ 0x13000000, "brge", I_BASE, CTRL, 1 }, /* same as bge */
{ 0x14000000, "bl", I_BASE, CTRL, 1 },
{ 0x14000000, "brl", I_BASE, CTRL, 1 }, /* same as bl */
{ 0x15000000, "bne", I_BASE, CTRL, 1 },
{ 0x15000000, "brlg", I_BASE, CTRL, 1 }, /* same as bne */
{ 0x16000000, "ble", I_BASE, CTRL, 1 },
{ 0x16000000, "brle", I_BASE, CTRL, 1 }, /* same as ble */
{ 0x17000000, "bo", I_BASE, CTRL, 1 },
{ 0x17000000, "bt", I_BASE, CTRL, 1 }, /* same as bo */
{ 0x17000000, "bro", I_BASE, CTRL, 1 }, /* same as bo */
{ 0x18000000, "faultno", I_BASE, CTRL, 0 },
{ 0x18000000, "faultf", I_BASE, CTRL, 0 }, /*same as faultno*/
{ 0x19000000, "faultg", I_BASE, CTRL, 0 },
{ 0x1a000000, "faulte", I_BASE, CTRL, 0 },
{ 0x1b000000, "faultge", I_BASE, CTRL, 0 },
{ 0x1c000000, "faultl", I_BASE, CTRL, 0 },
{ 0x1d000000, "faultne", I_BASE, CTRL, 0 },
{ 0x1e000000, "faultle", I_BASE, CTRL, 0 },
{ 0x1f000000, "faulto", I_BASE, CTRL, 0 },
{ 0x1f000000, "faultt", I_BASE, CTRL, 0 }, /* syn for faulto */
{ 0x01000000, "syscall", I_CASIM,CTRL, 0 },
/* If a COBR (or COJ) has 3 operands, the last one is always a
* displacement and does not appear explicitly in the table.
*/
{ 0x20000000, "testno", I_BASE, COBR, 1, R },
{ 0x21000000, "testg", I_BASE, COBR, 1, R },
{ 0x22000000, "teste", I_BASE, COBR, 1, R },
{ 0x23000000, "testge", I_BASE, COBR, 1, R },
{ 0x24000000, "testl", I_BASE, COBR, 1, R },
{ 0x25000000, "testne", I_BASE, COBR, 1, R },
{ 0x26000000, "testle", I_BASE, COBR, 1, R },
{ 0x27000000, "testo", I_BASE, COBR, 1, R },
{ 0x30000000, "bbc", I_BASE, COBR, 3, RL, RS },
{ 0x31000000, "cmpobg", I_BASE, COBR, 3, RL, RS },
{ 0x32000000, "cmpobe", I_BASE, COBR, 3, RL, RS },
{ 0x33000000, "cmpobge", I_BASE, COBR, 3, RL, RS },
{ 0x34000000, "cmpobl", I_BASE, COBR, 3, RL, RS },
{ 0x35000000, "cmpobne", I_BASE, COBR, 3, RL, RS },
{ 0x36000000, "cmpoble", I_BASE, COBR, 3, RL, RS },
{ 0x37000000, "bbs", I_BASE, COBR, 3, RL, RS },
{ 0x38000000, "cmpibno", I_BASE, COBR, 3, RL, RS },
{ 0x39000000, "cmpibg", I_BASE, COBR, 3, RL, RS },
{ 0x3a000000, "cmpibe", I_BASE, COBR, 3, RL, RS },
{ 0x3b000000, "cmpibge", I_BASE, COBR, 3, RL, RS },
{ 0x3c000000, "cmpibl", I_BASE, COBR, 3, RL, RS },
{ 0x3d000000, "cmpibne", I_BASE, COBR, 3, RL, RS },
{ 0x3e000000, "cmpible", I_BASE, COBR, 3, RL, RS },
{ 0x3f000000, "cmpibo", I_BASE, COBR, 3, RL, RS },
{ 0x31000000, "cmpojg", I_BASE, COJ, 3, RL, RS },
{ 0x32000000, "cmpoje", I_BASE, COJ, 3, RL, RS },
{ 0x33000000, "cmpojge", I_BASE, COJ, 3, RL, RS },
{ 0x34000000, "cmpojl", I_BASE, COJ, 3, RL, RS },
{ 0x35000000, "cmpojne", I_BASE, COJ, 3, RL, RS },
{ 0x36000000, "cmpojle", I_BASE, COJ, 3, RL, RS },
{ 0x38000000, "cmpijno", I_BASE, COJ, 3, RL, RS },
{ 0x39000000, "cmpijg", I_BASE, COJ, 3, RL, RS },
{ 0x3a000000, "cmpije", I_BASE, COJ, 3, RL, RS },
{ 0x3b000000, "cmpijge", I_BASE, COJ, 3, RL, RS },
{ 0x3c000000, "cmpijl", I_BASE, COJ, 3, RL, RS },
{ 0x3d000000, "cmpijne", I_BASE, COJ, 3, RL, RS },
{ 0x3e000000, "cmpijle", I_BASE, COJ, 3, RL, RS },
{ 0x3f000000, "cmpijo", I_BASE, COJ, 3, RL, RS },
{ 0x80000000, "ldob", I_BASE, MEM1, 2, M, R },
{ 0x82000000, "stob", I_BASE, MEM1, 2, R , M },
{ 0x84000000, "bx", I_BASE, MEM1, 1, M },
{ 0x85000000, "balx", I_BASE, MEM1, 2, M, R },
{ 0x86000000, "callx", I_BASE, MEM1, 1, M },
{ 0x88000000, "ldos", I_BASE, MEM2, 2, M, R },
{ 0x8a000000, "stos", I_BASE, MEM2, 2, R , M },
{ 0x8c000000, "lda", I_BASE, MEM1, 2, M, R },
{ 0x90000000, "ld", I_BASE, MEM4, 2, M, R },
{ 0x92000000, "st", I_BASE, MEM4, 2, R , M },
{ 0x98000000, "ldl", I_BASE, MEM8, 2, M, R2 },
{ 0x9a000000, "stl", I_BASE, MEM8, 2, R2 ,M },
{ 0xa0000000, "ldt", I_BASE, MEM12, 2, M, R4 },
{ 0xa2000000, "stt", I_BASE, MEM12, 2, R4 ,M },
{ 0xb0000000, "ldq", I_BASE, MEM16, 2, M, R4 },
{ 0xb2000000, "stq", I_BASE, MEM16, 2, R4 ,M },
{ 0xc0000000, "ldib", I_BASE, MEM1, 2, M, R },
{ 0xc2000000, "stib", I_BASE, MEM1, 2, R , M },
{ 0xc8000000, "ldis", I_BASE, MEM2, 2, M, R },
{ 0xca000000, "stis", I_BASE, MEM2, 2, R , M },
{ R_3(0x580), "notbit", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x581), "and", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x582), "andnot", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x583), "setbit", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x584), "notand", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x586), "xor", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x587), "or", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x588), "nor", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x589), "xnor", I_BASE, REG, 3, RSL,RSL,RS },
{ R_2D(0x58a), "not", I_BASE, REG, 2, RSL,RS },
{ R_3(0x58b), "ornot", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x58c), "clrbit", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x58d), "notor", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x58e), "nand", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x58f), "alterbit", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x590), "addo", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x591), "addi", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x592), "subo", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x593), "subi", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x598), "shro", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x59a), "shrdi", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x59b), "shri", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x59c), "shlo", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x59d), "rotate", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x59e), "shli", I_BASE, REG, 3, RSL,RSL,RS },
{ R_2(0x5a0), "cmpo", I_BASE, REG, 2, RSL,RSL },
{ R_2(0x5a1), "cmpi", I_BASE, REG, 2, RSL,RSL },
{ R_2(0x5a2), "concmpo", I_BASE, REG, 2, RSL,RSL },
{ R_2(0x5a3), "concmpi", I_BASE, REG, 2, RSL,RSL },
{ R_3(0x5a4), "cmpinco", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x5a5), "cmpinci", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x5a6), "cmpdeco", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x5a7), "cmpdeci", I_BASE, REG, 3, RSL,RSL,RS },
{ R_2(0x5ac), "scanbyte", I_BASE, REG, 2, RSL,RSL },
{ R_2(0x5ae), "chkbit", I_BASE, REG, 2, RSL,RSL },
{ R_3(0x5b0), "addc", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x5b2), "subc", I_BASE, REG, 3, RSL,RSL,RS },
{ R_2D(0x5cc), "mov", I_BASE, REG, 2, RSL,RS },
{ R_2D(0x5dc), "movl", I_BASE, REG, 2, RL2,R2 },
{ R_2D(0x5ec), "movt", I_BASE, REG, 2, RL4,R4 },
{ R_2D(0x5fc), "movq", I_BASE, REG, 2, RL4,R4 },
{ R_3(0x610), "atmod", I_BASE, REG, 3, RS, RSL,R },
{ R_3(0x612), "atadd", I_BASE, REG, 3, RS, RSL,RS },
{ R_2D(0x640), "spanbit", I_BASE, REG, 2, RSL,RS },
{ R_2D(0x641), "scanbit", I_BASE, REG, 2, RSL,RS },
{ R_3(0x645), "modac", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x650), "modify", I_BASE, REG, 3, RSL,RSL,R },
{ R_3(0x651), "extract", I_BASE, REG, 3, RSL,RSL,R },
{ R_3(0x654), "modtc", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x655), "modpc", I_BASE, REG, 3, RSL,RSL,R },
{ R_1(0x660), "calls", I_BASE, REG, 1, RSL },
{ R_0(0x66b), "mark", I_BASE, REG, 0, },
{ R_0(0x66c), "fmark", I_BASE, REG, 0, },
{ R_0(0x66d), "flushreg", I_BASE, REG, 0, },
{ R_0(0x66f), "syncf", I_BASE, REG, 0, },
{ R_3(0x670), "emul", I_BASE, REG, 3, RSL,RSL,R2 },
{ R_3(0x671), "ediv", I_BASE, REG, 3, RSL,RL2,RS },
{ R_2D(0x672), "cvtadr", I_CASIM,REG, 2, RL, R2 },
{ R_3(0x701), "mulo", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x708), "remo", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x70b), "divo", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x741), "muli", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x748), "remi", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x749), "modi", I_BASE, REG, 3, RSL,RSL,RS },
{ R_3(0x74b), "divi", I_BASE, REG, 3, RSL,RSL,RS },
/* Floating-point instructions */
{ R_2D(0x674), "cvtir", I_FP, REG, 2, RL, F },
{ R_2D(0x675), "cvtilr", I_FP, REG, 2, RL, F },
{ R_3(0x676), "scalerl", I_FP, REG, 3, RL, FL2,F2 },
{ R_3(0x677), "scaler", I_FP, REG, 3, RL, FL, F },
{ R_3(0x680), "atanr", I_FP, REG, 3, FL, FL, F },
{ R_3(0x681), "logepr", I_FP, REG, 3, FL, FL, F },
{ R_3(0x682), "logr", I_FP, REG, 3, FL, FL, F },
{ R_3(0x683), "remr", I_FP, REG, 3, FL, FL, F },
{ R_2(0x684), "cmpor", I_FP, REG, 2, FL, FL },
{ R_2(0x685), "cmpr", I_FP, REG, 2, FL, FL },
{ R_2D(0x688), "sqrtr", I_FP, REG, 2, FL, F },
{ R_2D(0x689), "expr", I_FP, REG, 2, FL, F },
{ R_2D(0x68a), "logbnr", I_FP, REG, 2, FL, F },
{ R_2D(0x68b), "roundr", I_FP, REG, 2, FL, F },
{ R_2D(0x68c), "sinr", I_FP, REG, 2, FL, F },
{ R_2D(0x68d), "cosr", I_FP, REG, 2, FL, F },
{ R_2D(0x68e), "tanr", I_FP, REG, 2, FL, F },
{ R_1(0x68f), "classr", I_FP, REG, 1, FL },
{ R_3(0x690), "atanrl", I_FP, REG, 3, FL2,FL2,F2 },
{ R_3(0x691), "logeprl", I_FP, REG, 3, FL2,FL2,F2 },
{ R_3(0x692), "logrl", I_FP, REG, 3, FL2,FL2,F2 },
{ R_3(0x693), "remrl", I_FP, REG, 3, FL2,FL2,F2 },
{ R_2(0x694), "cmporl", I_FP, REG, 2, FL2,FL2 },
{ R_2(0x695), "cmprl", I_FP, REG, 2, FL2,FL2 },
{ R_2D(0x698), "sqrtrl", I_FP, REG, 2, FL2,F2 },
{ R_2D(0x699), "exprl", I_FP, REG, 2, FL2,F2 },
{ R_2D(0x69a), "logbnrl", I_FP, REG, 2, FL2,F2 },
{ R_2D(0x69b), "roundrl", I_FP, REG, 2, FL2,F2 },
{ R_2D(0x69c), "sinrl", I_FP, REG, 2, FL2,F2 },
{ R_2D(0x69d), "cosrl", I_FP, REG, 2, FL2,F2 },
{ R_2D(0x69e), "tanrl", I_FP, REG, 2, FL2,F2 },
{ R_1(0x69f), "classrl", I_FP, REG, 1, FL2 },
{ R_2D(0x6c0), "cvtri", I_FP, REG, 2, FL, R },
{ R_2D(0x6c1), "cvtril", I_FP, REG, 2, FL, R2 },
{ R_2D(0x6c2), "cvtzri", I_FP, REG, 2, FL, R },
{ R_2D(0x6c3), "cvtzril", I_FP, REG, 2, FL, R2 },
{ R_2D(0x6c9), "movr", I_FP, REG, 2, FL, F },
{ R_2D(0x6d9), "movrl", I_FP, REG, 2, FL2,F2 },
{ R_2D(0x6e1), "movre", I_FP, REG, 2, FL4,F4 },
{ R_3(0x6e2), "cpysre", I_FP, REG, 3, FL4,FL4,F4 },
{ R_3(0x6e3), "cpyrsre", I_FP, REG, 3, FL4,FL4,F4 },
{ R_3(0x78b), "divr", I_FP, REG, 3, FL, FL, F },
{ R_3(0x78c), "mulr", I_FP, REG, 3, FL, FL, F },
{ R_3(0x78d), "subr", I_FP, REG, 3, FL, FL, F },
{ R_3(0x78f), "addr", I_FP, REG, 3, FL, FL, F },
{ R_3(0x79b), "divrl", I_FP, REG, 3, FL2,FL2,F2 },
{ R_3(0x79c), "mulrl", I_FP, REG, 3, FL2,FL2,F2 },
{ R_3(0x79d), "subrl", I_FP, REG, 3, FL2,FL2,F2 },
{ R_3(0x79f), "addrl", I_FP, REG, 3, FL2,FL2,F2 },
/* These are the floating point branch instructions. Each actually
* generates 2 branch instructions: the first a CTRL instruction with
* the indicated opcode, and the second a 'bno'.
*/
{ 0x12000000, "brue", I_FP, FBRA, 1 },
{ 0x11000000, "brug", I_FP, FBRA, 1 },
{ 0x13000000, "bruge", I_FP, FBRA, 1 },
{ 0x14000000, "brul", I_FP, FBRA, 1 },
{ 0x16000000, "brule", I_FP, FBRA, 1 },
{ 0x15000000, "brulg", I_FP, FBRA, 1 },
/* Decimal instructions */
{ R_3(0x642), "daddc", I_DEC, REG, 3, RSL,RSL,RS },
{ R_3(0x643), "dsubc", I_DEC, REG, 3, RSL,RSL,RS },
{ R_2D(0x644), "dmovt", I_DEC, REG, 2, RSL,RS },
/* KX extensions */
{ R_2(0x600), "synmov", I_KX, REG, 2, R, R },
{ R_2(0x601), "synmovl", I_KX, REG, 2, R, R },
{ R_2(0x602), "synmovq", I_KX, REG, 2, R, R },
{ R_2D(0x615), "synld", I_KX, REG, 2, R, R },
/* MC extensions */
{ R_3(0x603), "cmpstr", I_MIL, REG, 3, R, R, RL },
{ R_3(0x604), "movqstr", I_MIL, REG, 3, R, R, RL },
{ R_3(0x605), "movstr", I_MIL, REG, 3, R, R, RL },
{ R_2D(0x613), "inspacc", I_MIL, REG, 2, R, R },
{ R_2D(0x614), "ldphy", I_MIL, REG, 2, R, R },
{ R_3(0x617), "fill", I_MIL, REG, 3, R, RL, RL },
{ R_2D(0x646), "condrec", I_MIL, REG, 2, R, R },
{ R_2D(0x656), "receive", I_MIL, REG, 2, R, R },
{ R_3(0x662), "send", I_MIL, REG, 3, R, RL, R },
{ R_1(0x663), "sendserv", I_MIL, REG, 1, R },
{ R_1(0x664), "resumprcs", I_MIL, REG, 1, R },
{ R_1(0x665), "schedprcs", I_MIL, REG, 1, R },
{ R_0(0x666), "saveprcs", I_MIL, REG, 0, },
{ R_1(0x668), "condwait", I_MIL, REG, 1, R },
{ R_1(0x669), "wait", I_MIL, REG, 1, R },
{ R_1(0x66a), "signal", I_MIL, REG, 1, R },
{ R_1D(0x673), "ldtime", I_MIL, REG, 1, R2 },
/* CX extensions */
{ R_3(0x5d8), "eshro", I_CX, REG, 3, RSL,RSL,RS },
{ R_3(0x630), "sdma", I_CX, REG, 3, RSL,RSL,RL },
{ R_3(0x631), "udma", I_CX, REG, 0 },
{ R_3(0x659), "sysctl", I_CX, REG, 3, RSL,RSL,RL },
/* END OF TABLE */
{ 0, NULL, 0, 0 }
};
/* end of i960-opcode.h */

1717
include/m68k-opcode.h Executable file
View File

File diff suppressed because it is too large Load Diff

585
include/m88k-opcode.h Executable file
View File

@ -0,0 +1,585 @@
/* This file has been modified by Data General Corporation, November 1989. */
/*
* Disassembler Instruction Table
*
* The first field of the table is the opcode field. If an opcode
* is specified which has any non-opcode bits on, a system error
* will occur when the system attempts the install it into the
* instruction table. The second parameter is a pointer to the
* instruction mnemonic. Each operand is specified by offset, width,
* and type. The offset is the bit number of the least significant
* bit of the operand with bit 0 being the least significant bit of
* the instruction. The width is the number of bits used to specify
* the operand. The type specifies the output format to be used for
* the operand. The valid formats are: register, register indirect,
* hex constant, and bit field specification. The last field is a
* pointer to the next instruction in the linked list. These pointers
* are initialized by init_disasm().
*
* Structure Format
*
* struct INSTAB {
* UPINT opcode;
* char *mnemonic;
* struct OPSPEC op1,op2,op3;
* struct SIM_FLAGS flgs;
* struct INSTAB *next;
* }
*
* struct OPSPEC {
* UPINT offset:5;
* UPINT width:6;
* UPINT type:5;
* }
*
* Revision History
*
* Revision 1.0 11/08/85 Creation date
* 1.1 02/05/86 Updated instruction mnemonic table MD
* 1.2 06/16/86 Updated SIM_FLAGS for floating point
* 1.3 09/20/86 Updated for new encoding
* 05/11/89 R. Trawick adapted from Motorola disassembler
*/
#include <stdio.h>
/*
* This file contains the structures and constants needed to build the M88000
* simulator. It is the main include file, containing all the
* structures, macros and definitions except for the floating point
* instruction set.
*/
/*
* The following flag informs the Simulator as to what type of byte ordering
* will be used. For instance, a BOFLAG = 1 indicates a DEC VAX and IBM type
* of ordering shall be used.
*/
/* # define BOFLAG 1 /* BYTE ORDERING FLAG */
/* define the number of bits in the primary opcode field of the instruction,
* the destination field, the source 1 and source 2 fields.
*/
# define OP 8 /* size of opcode field */
# define DEST 6 /* size of destination */
# define SOURCE1 6 /* size of source1 */
# define SOURCE2 6 /* size of source2 */
# define REGs 32 /* number of registers */
# define WORD long
# define FLAG unsigned
# define STATE short
# define TRUE 1
# define FALSE 0
# define READ 0
# define WRITE 1
/* The next four equates define the priorities that the various classes
* of instructions have regarding writing results back into registers and
* signalling exceptions.
*/
# define PINT 0 /* Integer Priority */
# define PFLT 1 /* Floating Point Priority */
# define PMEM 2 /* Memory Priority */
# define NA 3 /* Not Applicable, instruction doesnt write to regs */
# define HIPRI 3 /* highest of these priorities */
/* The instruction registers are an artificial mechanism to speed up
* simulator execution. In the real processor, an instruction register
* is 32 bits wide. In the simulator, the 32 bit instruction is kept in
* a structure field called rawop, and the instruction is partially decoded,
* and split into various fields and flags which make up the other fields
* of the structure.
* The partial decode is done when the instructions are initially loaded
* into simulator memory. The simulator code memory is not an array of
* 32 bit words, but is an array of instruction register structures.
* Yes this wastes memory, but it executes much quicker.
*/
struct IR_FIELDS {
unsigned long op:OP,
dest: DEST,
src1: SOURCE1,
src2: SOURCE2;
int ltncy,
extime,
wb_pri; /* writeback priority */
unsigned short imm_flags:2,/* immediate size */
rs1_used:1, /* register source 1 used */
rs2_used:1, /* register source 2 used */
rsd_used:1, /* register source/dest. used */
c_flag:1, /* complement */
u_flag:1, /* upper half word */
n_flag:1, /* execute next */
wb_flag:1, /* uses writeback slot */
dest_64:1, /* dest size */
s1_64:1, /* source 1 size */
s2_64:1, /* source 2 size */
scale_flag:1, /* scaled register */
brk_flg:1;
};
struct mem_segs {
struct mem_wrd *seg; /* pointer (returned by calloc) to segment */
unsigned long baseaddr; /* base load address from file headers */
unsigned long endaddr; /* Ending address of segment */
int flags; /* segment control flags (none defined 12/5/86) */
};
#define MAXSEGS (10) /* max number of segment allowed */
#define MEMSEGSIZE (sizeof(struct mem_segs))/* size of mem_segs structure */
#define BRK_RD (0x01) /* break on memory read */
#define BRK_WR (0x02) /* break on memory write */
#define BRK_EXEC (0x04) /* break on execution */
#define BRK_CNT (0x08) /* break on terminal count */
struct mem_wrd {
struct IR_FIELDS opcode; /* simulator instruction break down */
union {
unsigned long l; /* memory element break down */
unsigned short s[2];
unsigned char c[4];
} mem;
};
#define MEMWRDSIZE (sizeof(struct mem_wrd)) /* size of each 32 bit memory model */
/* External declarations */
extern struct mem_segs memory[];
extern struct PROCESSOR m78000;
struct PROCESSOR {
unsigned WORD
ip, /* execute instruction pointer */
vbr, /* vector base register */
psr; /* processor status register */
WORD S1bus, /* source 1 */
S2bus, /* source 2 */
Dbus, /* destination */
DAbus, /* data address bus */
ALU,
Regs[REGs], /* data registers */
time_left[REGs], /* max clocks before reg is available */
wb_pri[REGs], /* writeback priority of reg */
SFU0_regs[REGs], /* integer unit control regs */
SFU1_regs[REGs], /* floating point control regs */
Scoreboard[REGs],
Vbr;
unsigned WORD scoreboard,
Psw,
Tpsw;
FLAG jump_pending:1; /* waiting for a jump instr. */
};
# define i26bit 1 /* size of immediate field */
# define i16bit 2
# define i10bit 3
/* Definitions for fields in psr */
# define mode 31
# define rbo 30
# define ser 29
# define carry 28
# define sf7m 11
# define sf6m 10
# define sf5m 9
# define sf4m 8
# define sf3m 7
# define sf2m 6
# define sf1m 5
# define mam 4
# define inm 3
# define exm 2
# define trm 1
# define ovfm 0
#define MODEMASK (1<<(mode-1))
# define SILENT 0 /* simulate without output to crt */
# define VERBOSE 1 /* simulate in verbose mode */
# define PR_INSTR 2 /* only print instructions */
# define RESET 16 /* reset phase */
# define PHASE1 0 /* data path phases */
# define PHASE2 1
/* the 1 clock operations */
# define ADDU 1
# define ADDC 2
# define ADDUC 3
# define ADD 4
# define SUBU ADD+1
# define SUBB ADD+2
# define SUBUB ADD+3
# define SUB ADD+4
# define AND ADD+5
# define OR ADD+6
# define XOR ADD+7
# define CMP ADD+8
/* the LOADS */
# define LDAB CMP+1
# define LDAH CMP+2
# define LDA CMP+3
# define LDAD CMP+4
# define LDB LDAD+1
# define LDH LDAD+2
# define LD LDAD+3
# define LDD LDAD+4
# define LDBU LDAD+5
# define LDHU LDAD+6
/* the STORES */
# define STB LDHU+1
# define STH LDHU+2
# define ST LDHU+3
# define STD LDHU+4
/* the exchange */
# define XMEMBU LDHU+5
# define XMEM LDHU+6
/* the branches */
# define JSR STD+1
# define BSR STD+2
# define BR STD+3
# define JMP STD+4
# define BB1 STD+5
# define BB0 STD+6
# define RTN STD+7
# define BCND STD+8
/* the TRAPS */
# define TB1 BCND+1
# define TB0 BCND+2
# define TCND BCND+3
# define RTE BCND+4
# define TBND BCND+5
/* the MISC instructions */
# define MUL TBND + 1
# define DIV MUL +2
# define DIVU MUL +3
# define MASK MUL +4
# define FF0 MUL +5
# define FF1 MUL +6
# define CLR MUL +7
# define SET MUL +8
# define EXT MUL +9
# define EXTU MUL +10
# define MAK MUL +11
# define ROT MUL +12
/* control register manipulations */
# define LDCR ROT +1
# define STCR ROT +2
# define XCR ROT +3
# define FLDCR ROT +4
# define FSTCR ROT +5
# define FXCR ROT +6
# define NOP XCR +1
/* floating point instructions */
# define FADD NOP +1
# define FSUB NOP +2
# define FMUL NOP +3
# define FDIV NOP +4
# define FSQRT NOP +5
# define FCMP NOP +6
# define FIP NOP +7
# define FLT NOP +8
# define INT NOP +9
# define NINT NOP +10
# define TRNC NOP +11
# define FLDC NOP +12
# define FSTC NOP +13
# define FXC NOP +14
# define UEXT(src,off,wid) ((((unsigned int)(src))>>(off)) & ((1<<(wid)) - 1))
# define SEXT(src,off,wid) (((((int)(src))<<(32-((off)+(wid)))) >>(32-(wid))) )
# define MAKE(src,off,wid) \
((((unsigned int)(src)) & ((1<<(wid)) - 1)) << (off))
# define opword(n) (unsigned long) (memaddr->mem.l)
/* Constants and Masks */
#define SFU0 0x80000000
#define SFU1 0x84000000
#define SFU7 0x9c000000
#define RRI10 0xf0000000
#define RRR 0xf4000000
#define SFUMASK 0xfc00ffe0
#define RRRMASK 0xfc00ffe0
#define RRI10MASK 0xfc00fc00
#define DEFMASK 0xfc000000
#define CTRL 0x0000f000
#define CTRLMASK 0xfc00f800
/* Operands types */
#define HEX 1
#define REG 2
#define IND 3
#define CONT 3
#define IND 3
#define BF 4
#define REGSC 5 /* scaled register */
#define CRREG 6 /* control register */
#define FCRREG 7 /* floating point control register */
#define PCREL 8
#define CONDMASK 9
/* Hashing Specification */
#define HASHVAL 79
/* Type definitions */
typedef unsigned int UINT;
/* Structure templates */
typedef struct {
unsigned int offset:5;
unsigned int width:6;
unsigned int type:5;
} OPSPEC;
struct SIM_FLAGS {
int ltncy, /* latency (max number of clocks needed to execute) */
extime, /* execution time (min number of clocks needed to execute) */
wb_pri; /* writeback slot priority */
unsigned long op:OP, /* simulator version of opcode */
imm_flags:2, /* 10,16 or 26 bit immediate flags */
rs1_used:1, /* register source 1 used */
rs2_used:1, /* register source 2 used */
rsd_used:1, /* register source/dest used */
c_flag:1, /* complement */
u_flag:1, /* upper half word */
n_flag:1, /* execute next */
wb_flag:1, /* uses writeback slot */
dest_64:1, /* double precision dest */
s1_64:1, /* double precision source 1 */
s2_64:1, /* double precision source 2 */
scale_flag:1; /* register is scaled */
};
typedef struct INSTRUCTAB {
unsigned int opcode;
char *mnemonic;
OPSPEC op1,op2,op3;
struct SIM_FLAGS flgs;
struct INSTRUCTAB *next;
} INSTAB;
/* Opcode Mnemonic Op 1 Spec Op 2 Spec Op 3 Spec Simflags Next */
static INSTAB instructions[] =
{0xf400c800,"jsr ",{0,5,REG} ,{0,0,0} ,{0,0,0} , {2,2,NA,JSR , 0,0,1,0,0,0,0,1,0,0,0,0}, NULL,
0xf400cc00,"jsr.n ",{0,5,REG} ,{0,0,0} ,{0,0,0} , {1,1,NA,JSR , 0,0,1,0,0,0,1,1,0,0,0,0}, NULL,
0xf400c000,"jmp ",{0,5,REG} ,{0,0,0} ,{0,0,0} , {2,2,NA,JMP , 0,0,1,0,0,0,0,1,0,0,0,0}, NULL,
0xf400c400,"jmp.n ",{0,5,REG} ,{0,0,0} ,{0,0,0} , {1,1,NA,JMP , 0,0,1,0,0,0,1,1,0,0,0,0}, NULL,
0xc8000000,"bsr ",{0,26,PCREL},{0,0,0} ,{0,0,0} , {2,2,NA,BSR , i26bit,0,0,0,0,0,0,1,0,0,0,0}, NULL,
0xcc000000,"bsr.n ",{0,26,PCREL},{0,0,0} ,{0,0,0} , {1,1,NA,BSR , i26bit,0,0,0,0,0,1,1,0,0,0,0}, NULL,
0xc0000000,"br ",{0,26,PCREL},{0,0,0} ,{0,0,0} , {2,2,NA,BR , i26bit,0,0,0,0,0,0,1,0,0,0,0}, NULL,
0xc4000000,"br.n ",{0,26,PCREL},{0,0,0} ,{0,0,0} , {1,1,NA,BR , i26bit,0,0,0,0,0,1,1,0,0,0,0}, NULL,
0xd0000000,"bb0 ",{21,5,HEX} ,{16,5,REG} ,{0,16,PCREL},{2,2,NA,BB0, i16bit,0,1,0,0,0,0,1,0,0,0,0}, NULL,
0xd4000000,"bb0.n ",{21,5,HEX} ,{16,5,REG} ,{0,16,PCREL},{1,1,NA,BB0, i16bit,0,1,0,0,0,1,1,0,0,0,0}, NULL,
0xd8000000,"bb1 ",{21,5,HEX},{16,5,REG} ,{0,16,PCREL},{2,2,NA,BB1, i16bit,0,1,0,0,0,0,1,0,0,0,0}, NULL,
0xdc000000,"bb1.n ",{21,5,HEX},{16,5,REG} ,{0,16,PCREL},{1,1,NA,BB1, i16bit,0,1,0,0,0,1,1,0,0,0,0}, NULL,
0xf000d000,"tb0 ",{21,5,HEX} ,{16,5,REG} ,{0,10,HEX}, {2,2,NA,TB0 , i10bit,0,1,0,0,0,0,1,0,0,0,0}, NULL,
0xf000d800,"tb1 ",{21,5,HEX} ,{16,5,REG} ,{0,10,HEX}, {2,2,NA,TB1 , i10bit,0,1,0,0,0,0,1,0,0,0,0}, NULL,
0xe8000000,"bcnd ",{21,5,CONDMASK},{16,5,REG},{0,16,PCREL},{2,2,NA,BCND, i16bit,0,1,0,0,0,0,1,0,0,0,0}, NULL,
0xec000000,"bcnd.n ",{21,5,CONDMASK},{16,5,REG},{0,16,PCREL},{1,1,NA,BCND, i16bit,0,1,0,0,0,1,1,0,0,0,0}, NULL,
0xf000e800,"tcnd ",{21,5,CONDMASK},{16,5,REG},{0,10,HEX}, {2,2,NA,TCND, i10bit,0,1,0,0,0,0,1,0,0,0,0}, NULL,
0xf8000000,"tbnd ",{16,5,REG} ,{0,16,HEX} ,{0,0,0} , {2,2,NA,TBND, i10bit,1,0,0,0,0,0,1,0,0,0,0}, NULL,
0xf400f800,"tbnd ",{16,5,REG} ,{0,5,REG} ,{0,0,0} , {2,2,NA,TBND, 0,1,1,0,0,0,0,1,0,0,0,0}, NULL,
0xf400fc00,"rte ",{0,0,0} ,{0,0,0} ,{0,0,0} , {2,2,NA,RTE , 0,0,0,0,0,0,0,1,0,0,0,0}, NULL,
0x1c000000,"ld.b ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {3,1,PMEM,LDB ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL,
0xf4001c00,"ld.b ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,LDB , 0,1,1,1,0,0,0,1,0,0,0,0}, NULL,
0x0c000000,"ld.bu ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {3,1,PMEM,LDBU, i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL,
0xf4000c00,"ld.bu ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,LDBU ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL,
0x18000000,"ld.h ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {3,1,PMEM,LDH ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL,
0xf4001800,"ld.h ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,LDH ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL,
0xf4001a00,"ld.h ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{3,1,PMEM,LDH ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL,
0x08000000,"ld.hu ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {3,1,PMEM,LDHU, i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL,
0xf4000800,"ld.hu ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,LDHU ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL,
0xf4000a00,"ld.hu ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{3,1,PMEM,LDHU ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL,
0x14000000,"ld ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {3,1,PMEM,LD ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL,
0xf4001400,"ld ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,LD ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL,
0xf4001600,"ld ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{3,1,PMEM,LD ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL,
0x10000000,"ld.d ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {3,1,PMEM,LDD ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL,
0xf4001000,"ld.d ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,LDD ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL,
0xf4001200,"ld.d ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{3,1,PMEM,LDD ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL,
0xf4001500,"ld.usr ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,LD ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL,
0xf4001700,"ld.usr ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{3,1,PMEM,LD ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL,
0x2c000000,"st.b ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,NA,STB ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL,
0xf4002c00,"st.b ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,NA,STB ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL,
0x28000000,"st.h ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,NA,STH ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL,
0xf4002800,"st.h ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,NA,STH ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL,
0xf4002a00,"st.h ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{1,1,NA,STH ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL,
0x24000000,"st ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,NA,ST ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL,
0xf4002400,"st ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,NA,ST ,0,1,1,1,0,0,0,1,0,0,0,0} ,NULL,
0xf4002600,"st ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{1,1,NA,ST ,0,1,1,1,0,0,0,1,0,0,0,1} ,NULL,
0x20000000,"st.d ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,NA,STD ,i16bit,0,1,0,0,0,0,1,0,0,0,0} ,NULL,
0xf4002000,"st.d ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,NA,STD ,0,1,1,1,0,0,0,1,0,0,0,0} ,NULL,
0xf4002200,"st.d ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{1,1,NA,STD ,0,1,1,1,0,0,0,1,0,0,0,1} ,NULL,
0xf4002500,"st.usr ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,NA,ST ,0,1,1,1,0,0,0,1,0,0,0,0} ,NULL,
0xf4002700,"st.usr ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{1,1,NA,ST ,0,1,1,1,0,0,0,1,0,0,0,1} ,NULL,
0x00000000,"xmem.bu ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {3,1,PMEM,XMEMBU ,i16bit,1,1,1,0,0,0,1,0,0,0,0} ,NULL,
0xf4000000,"xmem.bu ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,XMEM ,0,1,1,1,0,0,0,1,0,0,0,0} ,NULL,
0x04000000,"xmem ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {3,1,PMEM,XMEM ,i16bit,1,1,1,0,0,0,1,0,0,0,0} ,NULL,
0xf4000400,"xmem ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,XMEM ,0,1,1,1,0,0,0,1,0,0,0,0} ,NULL,
0xf4000600,"xmem ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{3,1,PMEM,XMEM ,0,1,1,1,0,0,0,1,0,0,0,1} ,NULL,
0xf4000500,"xmem.usr ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,XMEM ,0,1,1,1,0,0,0,1,0,0,0,0} ,NULL,
0xf4000700,"xmem.usr ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{3,1,PMEM,XMEM ,0,1,1,1,0,0,0,1,0,0,0,1} ,NULL,
0xf4003e00,"lda.b ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{1,1,PINT,LDAH, 0,1,1,1,0,0,0,0,0,0,0,1} ,NULL,
0xf4003a00,"lda.h ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{1,1,PINT,LDAH, 0,1,1,1,0,0,0,0,0,0,0,1} ,NULL,
0xf4003600,"lda ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{1,1,PINT,LDA , 0,1,1,1,0,0,0,0,0,0,0,1} ,NULL,
0xf4003200,"lda.d ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{1,1,PINT,LDAD, 0,1,1,1,0,0,0,0,0,0,0,1} ,NULL,
0x80004000,"ldcr ",{21,5,REG} ,{5,6,CRREG} ,{0,0,0} ,{1,1,PINT,LDCR, 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0x80008000,"stcr ",{16,5,REG} ,{5,6,CRREG} ,{0,0,0} ,{1,1,PINT,STCR, 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0x8000c000,"xcr ",{21,5,REG} ,{16,5,REG} ,{5,6,CRREG},{1,1,PINT,XCR, 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4006000,"addu ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,ADDU, 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4006200,"addu.ci ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,ADDU, 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4006100,"addu.co ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,ADDU, 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4006300,"addu.cio ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,ADDU, 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4006400,"subu ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUBU, 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4006600,"subu.ci ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUBU, 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4006500,"subu.co ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUBU, 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4006700,"subu.cio ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUBU, 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4006900,"divu ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {32,32,PINT,DIVU, 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4006d00,"mul ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,4,PINT,MUL, 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4007000,"add ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,ADD , 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4007200,"add.ci ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,ADD , 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4007100,"add.co ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,ADD , 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4007300,"add.cio ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,ADD , 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4007400,"sub ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUB , 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4007600,"sub.ci ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUB , 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4007500,"sub.co ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUB , 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4007700,"sub.cio ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUB , 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4007900,"div ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {32,32,PINT,DIV , 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4007d00,"cmp ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,CMP, 0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0x60000000,"addu ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,ADDU, i16bit,1,0,1,0,0,0,0,0,0,0,0} ,NULL,
0x64000000,"subu ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,SUBU, i16bit,1,0,1,0,0,0,0,0,0,0,0} ,NULL,
0x68000000,"divu ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {32,32,PINT,DIVU, i16bit,1,0,1,0,0,0,0,0,0,0,0} ,NULL,
0x6c000000,"mul ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {4,1,PINT,MUL, i16bit,1,0,1,0,0,0,0,0,0,0,0} ,NULL,
0x70000000,"add ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,ADD, i16bit,1,0,1,0,0,0,0,0,0,0,0} ,NULL,
0x74000000,"sub ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,SUB, i16bit,1,0,1,0,0,0,0,0,0,0,0} ,NULL,
0x78000000,"div ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {32,32,PINT,DIV, i16bit,1,0,1,0,0,0,0,0,0,0,0} ,NULL,
0x7c000000,"cmp ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,CMP, i16bit,1,0,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4004000,"and ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,AND ,0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4004400,"and.c ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,AND ,0,1,1,1,1,0,0,0,0,0,0,0} ,NULL,
0xf4005800,"or ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,OR ,0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4005c00,"or.c ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,OR ,0,1,1,1,1,0,0,0,0,0,0,0} ,NULL,
0xf4005000,"xor ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,XOR ,0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4005400,"xor.c ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,XOR ,0,1,1,1,1,0,0,0,0,0,0,0} ,NULL,
0x40000000,"and ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,AND ,i16bit,1,0,1,0,0,0,0,0,0,0,0} ,NULL,
0x44000000,"and.u ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,AND ,i16bit,1,0,1,0,1,0,0,0,0,0,0} ,NULL,
0x58000000,"or ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,OR ,i16bit,1,0,1,0,0,0,0,0,0,0,0} ,NULL,
0x5c000000,"or.u ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,OR ,i16bit,1,0,1,0,1,0,0,0,0,0,0} ,NULL,
0x50000000,"xor ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,XOR ,i16bit,1,0,1,0,0,0,0,0,0,0,0} ,NULL,
0x54000000,"xor.u ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,XOR ,i16bit,1,0,1,0,1,0,0,0,0,0,0} ,NULL,
0x48000000,"mask ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,MASK ,i16bit,1,0,1,0,0,0,0,0,0,0,0} ,NULL,
0x4c000000,"mask.u ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,MASK ,i16bit,1,0,1,0,1,0,0,0,0,0,0} ,NULL,
0xf400ec00,"ff0 ",{21,5,REG} ,{0,5,REG} ,{0,0,0} , {1,1,PINT,FF0 ,0,0,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf400e800,"ff1 ",{21,5,REG} ,{0,5,REG} ,{0,0,0} , {1,1,PINT,FF1 ,0,0,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf0008000,"clr ",{21,5,REG} ,{16,5,REG} ,{0,10,BF} , {1,1,PINT,CLR ,i10bit,1,0,1,0,0,0,0,0,0,0,0} ,NULL,
0xf0008800,"set ",{21,5,REG} ,{16,5,REG} ,{0,10,BF} , {1,1,PINT,SET ,i10bit,1,0,1,0,0,0,0,0,0,0,0} ,NULL,
0xf0009000,"ext ",{21,5,REG} ,{16,5,REG} ,{0,10,BF} , {1,1,PINT,EXT ,i10bit,1,0,1,0,0,0,0,0,0,0,0} ,NULL,
0xf0009800,"extu ",{21,5,REG} ,{16,5,REG} ,{0,10,BF} , {1,1,PINT,EXTU ,i10bit,1,0,1,0,0,0,0,0,0,0,0} ,NULL,
0xf000a000,"mak ",{21,5,REG} ,{16,5,REG} ,{0,10,BF} , {1,1,PINT,MAK ,i10bit,1,0,1,0,0,0,0,0,0,0,0} ,NULL,
0xf000a800,"rot ",{21,5,REG} ,{16,5,REG} ,{0,10,BF} , {1,1,PINT,ROT ,i10bit,1,0,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4008000,"clr ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,CLR ,0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4008800,"set ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SET ,0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4009000,"ext ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,EXT ,0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf4009800,"extu ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,EXTU ,0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf400a000,"mak ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,MAK ,0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0xf400a800,"rot ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,ROT ,0,1,1,1,0,0,0,0,0,0,0,0} ,NULL,
0x84002800,"fadd.sss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {5,1,PFLT,FADD ,0,1,1,1,0,0,0,1,0,0,0,0} ,NULL,
0x84002880,"fadd.ssd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0,0,0,1,0,0,1,0} ,NULL,
0x84002a00,"fadd.sds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0,0,0,1,0,1,0,0} ,NULL,
0x84002a80,"fadd.sdd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0,0,0,1,0,1,1,0} ,NULL,
0x84002820,"fadd.dss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0,0,0,1,1,0,0,0} ,NULL,
0x840028a0,"fadd.dsd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0,0,0,1,1,0,1,0} ,NULL,
0x84002a20,"fadd.dds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0,0,0,1,1,1,0,0} ,NULL,
0x84002aa0,"fadd.ddd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0,0,0,1,1,1,1,0} ,NULL,
0x84003000,"fsub.sss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {5,1,PFLT,FSUB ,0,1,1,1,0,0,0,1,0,0,0,0} ,NULL,
0x84003080,"fsub.ssd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,0,0,1,0} ,NULL,
0x84003200,"fsub.sds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,0,1,0,0} ,NULL,
0x84003280,"fsub.sdd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,0,1,1,0} ,NULL,
0x84003020,"fsub.dss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,1,0,0,0} ,NULL,
0x840030a0,"fsub.dsd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,1,0,1,0} ,NULL,
0x84003220,"fsub.dds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,1,1,0,0} ,NULL,
0x840032a0,"fsub.ddd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,1,1,1,0} ,NULL,
0x84000000,"fmul.sss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,1,PFLT,FMUL ,0,1,1,1,0,0,0,1,0,0,0,0} ,NULL,
0x84000080,"fmul.ssd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,0,0,1,0} ,NULL,
0x84000200,"fmul.sds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,0,1,0,0} ,NULL,
0x84000280,"fmul.sdd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,0,1,1,0} ,NULL,
0x84000020,"fmul.dss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,1,0,0,0} ,NULL,
0x840000a0,"fmul.dsd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,1,0,1,0} ,NULL,
0x84000220,"fmul.dds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,1,1,0,0} ,NULL,
0x840002a0,"fmul.ddd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,1,1,1,0} ,NULL,
0x84007000,"fdiv.sss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {30,30,PFLT,FDIV ,0,1,1,1,0,0,0,1,0,0,0,0} ,NULL,
0x84007080,"fdiv.ssd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {60,60,PFLT,FDIV ,0,1,1,1,0,0,0,1,0,0,1,0} ,NULL,
0x84007200,"fdiv.sds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {60,60,PFLT,FDIV ,0,1,1,1,0,0,0,1,0,1,0,0} ,NULL,
0x84007280,"fdiv.sdd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {60,60,PFLT,FDIV ,0,1,1,1,0,0,0,1,0,1,1,0} ,NULL,
0x84007020,"fdiv.dss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {60,60,PFLT,FDIV ,0,1,1,1,0,0,0,1,1,0,0,0} ,NULL,
0x840070a0,"fdiv.dsd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {60,60,PFLT,FDIV ,0,1,1,1,0,0,0,1,1,0,1,0} ,NULL,
0x84007220,"fdiv.dds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {60,60,PFLT,FDIV ,0,1,1,1,0,0,0,1,1,1,0,0} ,NULL,
0x840072a0,"fdiv.ddd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {60,60,PFLT,FDIV ,0,1,1,1,0,0,0,1,1,1,1,0} ,NULL,
0x84007800,"fsqrt.ss ",{21,5,REG} ,{0,5,REG} ,{0,0,0} , {5,1,PFLT,FLT ,0,0,1,1,0,0,0,1,0,0,0,0} ,NULL,
0x84007880,"fsqrt.sd ",{21,5,REG} ,{0,5,REG} ,{0,0,0} , {5,1,PFLT,FLT ,0,0,1,1,0,0,0,1,0,0,0,0} ,NULL,
0x84007820,"fsqrt.ds ",{21,5,REG} ,{0,5,REG} ,{0,0,0} , {5,1,PFLT,FLT ,0,0,1,1,0,0,0,1,0,0,0,0} ,NULL,
0x840078a0,"fsqrt.dd ",{21,5,REG} ,{0,5,REG} ,{0,0,0} , {6,1,PFLT,FLT ,0,0,1,1,0,0,0,1,1,0,0,0} ,NULL,
0x84003800,"fcmp.ss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {5,1,PFLT,FCMP ,0,1,1,1,0,0,0,1,0,0,0,0} ,NULL,
0x84003880,"fcmp.sd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,1,PFLT,FCMP ,0,1,1,1,0,0,0,1,0,1,0,0} ,NULL,
0x84003a00,"fcmp.ds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,1,PFLT,FCMP ,0,1,1,1,0,0,0,1,1,0,0,0} ,NULL,
0x84003a80,"fcmp.dd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,1,PFLT,FCMP ,0,1,1,1,0,0,0,1,1,1,0,0} ,NULL,
0x84002000,"flt.s ",{21,5,REG} ,{0,5,REG} ,{0,0,0} , {5,1,PFLT,FLT ,0,0,1,1,0,0,0,1,0,0,0,0} ,NULL,
0x84002020,"flt.d ",{21,5,REG} ,{0,5,REG} ,{0,0,0} , {6,1,PFLT,FLT ,0,0,1,1,0,0,0,1,1,0,0,0} ,NULL,
0x84004800,"int.s ",{21,5,REG} ,{0,5,REG} ,{0,0,0} , {5,1,PFLT,INT ,0,0,1,1,0,0,0,1,0,0,0,0} ,NULL,
0x84004880,"int.d ",{21,5,REG} ,{0,5,REG} ,{0,0,0} , {6,1,PFLT,INT ,0,0,1,1,0,0,0,1,1,0,0,0} ,NULL,
0x84005000,"nint.s ",{21,5,REG} ,{0,5,REG} ,{0,0,0} , {5,1,PFLT,INT ,0,0,1,1,0,0,0,1,0,0,0,0} ,NULL,
0x84005080,"nint.d ",{21,5,REG} ,{0,5,REG} ,{0,0,0} , {6,1,PFLT,INT ,0,0,1,1,0,0,0,1,1,0,0,0} ,NULL,
0x84005800,"trnc.s ",{21,5,REG} ,{0,5,REG} ,{0,0,0} , {5,1,PFLT,TRNC ,0,0,1,1,0,0,0,1,0,0,0,0} ,NULL,
0x84005880,"trnc.d ",{21,5,REG} ,{0,5,REG} ,{0,0,0} , {6,1,PFLT,TRNC ,0,0,1,1,0,0,0,1,1,0,0,0} ,NULL,
0x80004800,"fldcr ",{21,5,REG} ,{5,6,FCRREG} ,{0,0,0} , {1,1,PFLT,FLDC ,0,0,1,1,0,0,0,1,0,0,0,0} ,NULL,
0x80008800,"fstcr ",{16,5,REG} ,{5,6,FCRREG} ,{0,0,0} , {1,1,PFLT,FSTC ,0,0,1,1,0,0,0,1,0,0,0,0} ,NULL,
0x8000c800,"fxcr ",{21,5,REG} ,{16,5,REG} ,{5,6,FCRREG} , {1,1,PFLT,FXC ,0,0,1,1,0,0,0,1,0,0,0,0} ,NULL};

363
include/mips-opcode.h Executable file
View File

@ -0,0 +1,363 @@
/* Mips opcde list for GDB, the GNU debugger.
Copyright (C) 1989 Free Software Foundation, Inc.
Contributed by Nobuyuki Hikichi(hikichi@sra.junet)
Made to work for little-endian machines, and debugged
by Per Bothner (bothner@cs.wisc.edu).
Many fixes contributed by Frank Yellin (fy@lucid.com).
This file is part of GDB.
GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 1, or (at your option)
any later version.
GDB is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GDB; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
#if BITS_BIG_ENDIAN
#define BIT_FIELDS_2(a,b) a;b;
#define BIT_FIELDS_4(a,b,c,d) a;b;c;d;
#define BIT_FIELDS_6(a,b,c,d,e,f) a;b;c;d;e;f;
#else
#define BIT_FIELDS_2(a,b) b;a;
#define BIT_FIELDS_4(a,b,c,d) d;c;b;a;
#define BIT_FIELDS_6(a,b,c,d,e,f) f;e;d;c;b;a;
#endif
struct op_i_fmt
{
BIT_FIELDS_4(
unsigned op : 6,
unsigned rs : 5,
unsigned rt : 5,
unsigned immediate : 16)
};
struct op_j_fmt
{
BIT_FIELDS_2(
unsigned op : 6,
unsigned target : 26)
};
struct op_r_fmt
{
BIT_FIELDS_6(
unsigned op : 6,
unsigned rs : 5,
unsigned rt : 5,
unsigned rd : 5,
unsigned shamt : 5,
unsigned funct : 6)
};
struct fop_i_fmt
{
BIT_FIELDS_4(
unsigned op : 6,
unsigned rs : 5,
unsigned rt : 5,
unsigned immediate : 16)
};
struct op_b_fmt
{
BIT_FIELDS_4(
unsigned op : 6,
unsigned rs : 5,
unsigned rt : 5,
short delta : 16)
};
struct fop_r_fmt
{
BIT_FIELDS_6(
unsigned op : 6,
unsigned fmt : 5,
unsigned ft : 5,
unsigned fs : 5,
unsigned fd : 5,
unsigned funct : 6)
};
struct mips_opcode
{
char *name;
unsigned long opcode;
unsigned long match;
char *args;
int bdelay; /* Nonzero if delayed branch. */
};
/* args format;
"s" rs: source register specifier
"t" rt: target register
"i" immediate
"a" target address
"c" branch condition
"d" rd: destination register specifier
"h" shamt: shift amount
"f" funct: function field
for fpu
"S" fs source 1 register
"T" ft source 2 register
"D" distination register
*/
#define one(x) (x << 26)
#define op_func(x, y) ((x << 26) | y)
#define op_cond(x, y) ((x << 26) | (y << 16))
#define op_rs_func(x, y, z) ((x << 26) | (y << 21) | z)
#define op_rs_b11(x, y, z) ((x << 26) | (y << 21) | z)
#define op_o16(x, y) ((x << 26) | (y << 16))
#define op_bc(x, y, z) ((x << 26) | (y << 21) | (z << 16))
struct mips_opcode mips_opcodes[] =
{
/* These first opcodes are special cases of the ones in the comments */
{"nop", 0, 0xffffffff, /*li*/ "", 0},
{"li", op_bc(9,0,0), op_bc(0x3f,31,0), /*addiu*/ "t,j", 0},
{"b", one(4), 0xffff0000, /*beq*/ "b", 1},
{"move", op_func(0, 33), op_cond(0x3f,31)|0x7ff,/*addu*/ "d,s", 0},
{"sll", op_func(0, 0), op_func(0x3f, 0x3f), "d,t,h", 0},
{"srl", op_func(0, 2), op_func(0x3f, 0x3f), "d,t,h", 0},
{"sra", op_func(0, 3), op_func(0x3f, 0x3f), "d,t,h", 0},
{"sllv", op_func(0, 4), op_func(0x3f, 0x7ff), "d,t,s", 0},
{"srlv", op_func(0, 6), op_func(0x3f, 0x7ff), "d,t,s", 0},
{"srav", op_func(0, 7), op_func(0x3f, 0x7ff), "d,t,s", 0},
{"jr", op_func(0, 8), op_func(0x3f, 0x1fffff), "s", 1},
{"jalr", op_func(0, 9), op_func(0x3f, 0x1f07ff), "d,s", 1},
{"syscall", op_func(0, 12), op_func(0x3f, 0x3f), "", 0},
{"break", op_func(0, 13), op_func(0x3f, 0x3f), "", 0},
{"mfhi", op_func(0, 16), op_func(0x3f, 0x03ff07ff), "d", 0},
{"mthi", op_func(0, 17), op_func(0x3f, 0x1fffff), "s", 0},
{"mflo", op_func(0, 18), op_func(0x3f, 0x03ff07ff), "d", 0},
{"mtlo", op_func(0, 19), op_func(0x3f, 0x1fffff), "s", 0},
{"mult", op_func(0, 24), op_func(0x3f, 0xffff), "s,t", 0},
{"multu", op_func(0, 25), op_func(0x3f, 0xffff), "s,t", 0},
{"div", op_func(0, 26), op_func(0x3f, 0xffff), "s,t", 0},
{"divu", op_func(0, 27), op_func(0x3f, 0xffff), "s,t", 0},
{"add", op_func(0, 32), op_func(0x3f, 0x7ff), "d,s,t", 0},
{"addu", op_func(0, 33), op_func(0x3f, 0x7ff), "d,s,t", 0},
{"sub", op_func(0, 34), op_func(0x3f, 0x7ff), "d,s,t", 0},
{"subu", op_func(0, 35), op_func(0x3f, 0x7ff), "d,s,t", 0},
{"and", op_func(0, 36), op_func(0x3f, 0x7ff), "d,s,t", 0},
{"or", op_func(0, 37), op_func(0x3f, 0x7ff), "d,s,t", 0},
{"xor", op_func(0, 38), op_func(0x3f, 0x7ff), "d,s,t", 0},
{"nor", op_func(0, 39), op_func(0x3f, 0x7ff), "d,s,t", 0},
{"slt", op_func(0, 42), op_func(0x3f, 0x7ff), "d,s,t", 0},
{"sltu", op_func(0, 43), op_func(0x3f, 0x7ff), "d,s,t", 0},
{"bltz", op_cond (1, 0), op_cond(0x3f, 0x1f), "s,b", 1},
{"bgez", op_cond (1, 1), op_cond(0x3f, 0x1f), "s,b", 1},
{"bltzal", op_cond (1, 16),op_cond(0x3f, 0x1f), "s,b", 1},
{"bgezal", op_cond (1, 17),op_cond(0x3f, 0x1f), "s,b", 1},
{"j", one(2), one(0x3f), "a", 1},
{"jal", one(3), one(0x3f), "a", 1},
{"beq", one(4), one(0x3f), "s,t,b", 1},
{"bne", one(5), one(0x3f), "s,t,b", 1},
{"blez", one(6), one(0x3f) | 0x1f0000, "s,b", 1},
{"bgtz", one(7), one(0x3f) | 0x1f0000, "s,b", 1},
{"addi", one(8), one(0x3f), "t,s,j", 0},
{"addiu", one(9), one(0x3f), "t,s,j", 0},
{"slti", one(10), one(0x3f), "t,s,j", 0},
{"sltiu", one(11), one(0x3f), "t,s,j", 0},
{"andi", one(12), one(0x3f), "t,s,i", 0},
{"ori", one(13), one(0x3f), "t,s,i", 0},
{"xori", one(14), one(0x3f), "t,s,i", 0},
/* rs field is don't care field? */
{"lui", one(15), one(0x3f), "t,i", 0},
/* co processor 0 instruction */
{"mfc0", op_rs_b11 (16, 0, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
{"cfc0", op_rs_b11 (16, 2, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
{"mtc0", op_rs_b11 (16, 4, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
{"ctc0", op_rs_b11 (16, 6, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
{"bc0f", op_o16(16, 0x100), op_o16(0x3f, 0x3ff), "b", 1},
{"bc0f", op_o16(16, 0x180), op_o16(0x3f, 0x3ff), "b", 1},
{"bc0t", op_o16(16, 0x101), op_o16(0x3f, 0x3ff), "b", 1},
{"bc0t", op_o16(16, 0x181), op_o16(0x3f, 0x3ff), "b", 1},
{"tlbr", op_rs_func(16, 0x10, 1), ~0, "", 0},
{"tlbwi", op_rs_func(16, 0x10, 2), ~0, "", 0},
{"tlbwr", op_rs_func(16, 0x10, 6), ~0, "", 0},
{"tlbp", op_rs_func(16, 0x10, 8), ~0, "", 0},
{"rfe", op_rs_func(16, 0x10, 16), ~0, "", 0},
{"mfc1", op_rs_b11 (17, 0, 0), op_rs_b11(0x3f, 0x1f, 0),"t,S", 0},
{"cfc1", op_rs_b11 (17, 2, 0), op_rs_b11(0x3f, 0x1f, 0),"t,S", 0},
{"mtc1", op_rs_b11 (17, 4, 0), op_rs_b11(0x3f, 0x1f, 0),"t,S", 0},
{"ctc1", op_rs_b11 (17, 6, 0), op_rs_b11(0x3f, 0x1f, 0),"t,S", 0},
{"bc1f", op_o16(17, 0x100), op_o16(0x3f, 0x3ff), "b", 1},
{"bc1f", op_o16(17, 0x180), op_o16(0x3f, 0x3ff), "b", 1},
{"bc1t", op_o16(17, 0x101), op_o16(0x3f, 0x3ff), "b", 1},
{"bc1t", op_o16(17, 0x181), op_o16(0x3f, 0x3ff), "b", 1},
/* fpu instruction */
{"add.s", op_rs_func(17, 0x10, 0),
op_rs_func(0x3f, 0x1f, 0x3f), "D,S,T", 0},
{"add.d", op_rs_func(17, 0x11, 0),
op_rs_func(0x3f, 0x1f, 0x3f), "D,S,T", 0},
{"sub.s", op_rs_func(17, 0x10, 1),
op_rs_func(0x3f, 0x1f, 0x3f), "D,S,T", 0},
{"sub.d", op_rs_func(17, 0x11, 1),
op_rs_func(0x3f, 0x1f, 0x3f), "D,S,T", 0},
{"mul.s", op_rs_func(17, 0x10, 2),
op_rs_func(0x3f, 0x1f, 0x3f), "D,S,T", 0},
{"mul.d", op_rs_func(17, 0x11, 2),
op_rs_func(0x3f, 0x1f, 0x3f), "D,S,T", 0},
{"div.s", op_rs_func(17, 0x10, 3),
op_rs_func(0x3f, 0x1f, 0x3f), "D,S,T", 0},
{"div.d", op_rs_func(17, 0x11, 3),
op_rs_func(0x3f, 0x1f, 0x3f), "D,S,T", 0},
{"abs.s", op_rs_func(17, 0x10, 5),
op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
{"abs.d", op_rs_func(17, 0x11, 5),
op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
{"mov.s", op_rs_func(17, 0x10, 6),
op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
{"mov.d", op_rs_func(17, 0x11, 6),
op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
{"neg.s", op_rs_func(17, 0x10, 7),
op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
{"neg.d", op_rs_func(17, 0x11, 7),
op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
{"cvt.s.s", op_rs_func(17, 0x10, 32),
op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
{"cvt.s.d", op_rs_func(17, 0x11, 32),
op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
{"cvt.s.w", op_rs_func(17, 0x14, 32),
op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
{"cvt.d.s", op_rs_func(17, 0x10, 33),
op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
{"cvt.d.d", op_rs_func(17, 0x11, 33),
op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
{"cvt.d.w", op_rs_func(17, 0x14, 33),
op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
{"cvt.w.s", op_rs_func(17, 0x10, 36),
op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
{"cvt.w.d", op_rs_func(17, 0x11, 36),
op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
{"c.f.s", op_rs_func(17, 0x10, 48),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.f.d", op_rs_func(17, 0x11, 48),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.un.s", op_rs_func(17, 0x10, 49),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.un.d", op_rs_func(17, 0x11, 49),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.eq.s", op_rs_func(17, 0x10, 50),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.eq.d", op_rs_func(17, 0x11, 50),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.ueq.s", op_rs_func(17, 0x10, 51),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.ueq.d", op_rs_func(17, 0x11, 51),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.olt.s", op_rs_func(17, 0x10, 52),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.olt.d", op_rs_func(17, 0x11, 52),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.ult.s", op_rs_func(17, 0x10, 53),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.ult.d", op_rs_func(17, 0x11, 53),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.ole.s", op_rs_func(17, 0x10, 54),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.ole.d", op_rs_func(17, 0x11, 54),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.ule.s", op_rs_func(17, 0x10, 55),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.ule.d", op_rs_func(17, 0x11, 55),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.sf.s", op_rs_func(17, 0x10, 56),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.sf.d", op_rs_func(17, 0x11, 56),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.ngle.s", op_rs_func(17, 0x10, 57),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.ngle.d", op_rs_func(17, 0x11, 57),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.seq.s", op_rs_func(17, 0x10, 58),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.seq.d", op_rs_func(17, 0x11, 58),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.ngl.s", op_rs_func(17, 0x10, 59),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.ngl.d", op_rs_func(17, 0x11, 59),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.lt.s", op_rs_func(17, 0x10, 60),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.lt.d", op_rs_func(17, 0x11, 60),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.nge.s", op_rs_func(17, 0x10, 61),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.nge.d", op_rs_func(17, 0x11, 61),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.le.s", op_rs_func(17, 0x10, 62),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.le.d", op_rs_func(17, 0x11, 62),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.ngt.s", op_rs_func(17, 0x10, 63),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
{"c.ngt.d", op_rs_func(17, 0x11, 63),
op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
/* co processor 2 instruction */
{"mfc2", op_rs_b11 (18, 0, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
{"cfc2", op_rs_b11 (18, 2, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
{"mtc2", op_rs_b11 (18, 4, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
{"ctc2", op_rs_b11 (18, 6, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
{"bc2f", op_o16(18, 0x100), op_o16(0x3f, 0x3ff), "b", 1},
{"bc2f", op_o16(18, 0x180), op_o16(0x3f, 0x3ff), "b", 1},
{"bc2f", op_o16(18, 0x101), op_o16(0x3f, 0x3ff), "b", 1},
{"bc2t", op_o16(18, 0x181), op_o16(0x3f, 0x3ff), "b", 1},
/* co processor 3 instruction */
{"mtc3", op_rs_b11 (19, 0, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
{"cfc3", op_rs_b11 (19, 2, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
{"mtc3", op_rs_b11 (19, 4, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
{"ctc3", op_rs_b11 (19, 6, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
{"bc3f", op_o16(19, 0x100), op_o16(0x3f, 0x3ff), "b", 1},
{"bc3f", op_o16(19, 0x180), op_o16(0x3f, 0x3ff), "b", 1},
{"bc3t", op_o16(19, 0x101), op_o16(0x3f, 0x3ff), "b", 1},
{"bc3t", op_o16(19, 0x181), op_o16(0x3f, 0x3ff), "b", 1},
{"lb", one(32), one(0x3f), "t,j(s)", 0},
{"lh", one(33), one(0x3f), "t,j(s)", 0},
{"lwl", one(34), one(0x3f), "t,j(s)", 0},
{"lw", one(35), one(0x3f), "t,j(s)", 0},
{"lbu", one(36), one(0x3f), "t,j(s)", 0},
{"lhu", one(37), one(0x3f), "t,j(s)", 0},
{"lwr", one(38), one(0x3f), "t,j(s)", 0},
{"sb", one(40), one(0x3f), "t,j(s)", 0},
{"sh", one(41), one(0x3f), "t,j(s)", 0},
{"swl", one(42), one(0x3f), "t,j(s)", 0},
{"swr", one(46), one(0x3f), "t,j(s)", 0},
{"sw", one(43), one(0x3f), "t,j(s)", 0},
{"lwc0", one(48), one(0x3f), "t,j(s)", 0},
/* for fpu */
{"lwc1", one(49), one(0x3f), "T,j(s)", 0},
{"lwc2", one(50), one(0x3f), "t,j(s)", 0},
{"lwc3", one(51), one(0x3f), "t,j(s)", 0},
{"swc0", one(56), one(0x3f), "t,j(s)", 0},
/* for fpu */
{"swc1", one(57), one(0x3f), "T,j(s)", 0},
{"swc2", one(58), one(0x3f), "t,j(s)", 0},
{"swc3", one(59), one(0x3f), "t,j(s)", 0},
};

422
include/np1-opcode.h Executable file
View File

@ -0,0 +1,422 @@
/* Print GOULD NPL instructions for GDB, the GNU debugger.
Copyright (C) 1986, 1987, 1989 Free Software Foundation, Inc.
This file is part of GDB.
GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 1, or (at your option)
any later version.
GDB is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GDB; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
struct gld_opcode
{
char *name;
unsigned long opcode;
unsigned long mask;
char *args;
int length;
};
/* We store four bytes of opcode for all opcodes because that
is the most any of them need. The actual length of an instruction
is always at least 2 bytes, and at most four. The length of the
instruction is based on the opcode.
The mask component is a mask saying which bits must match
particular opcode in order for an instruction to be an instance
of that opcode.
The args component is a string containing characters
that are used to format the arguments to the instruction. */
/* Kinds of operands:
r Register in first field
R Register in second field
b Base register in first field
B Base register in second field
v Vector register in first field
V Vector register in first field
A Optional address register (base register)
X Optional index register
I Immediate data (16bits signed)
O Offset field (16bits signed)
h Offset field (15bits signed)
d Offset field (14bits signed)
S Shift count field
any other characters are printed as is...
*/
/* The assembler requires that this array be sorted as follows:
all instances of the same mnemonic must be consecutive.
All instances of the same mnemonic with the same number of operands
must be consecutive.
*/
struct gld_opcode gld_opcodes[] =
{
{ "lb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 },
{ "lnb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 },
{ "lbs", 0xec080000, 0xfc080000, "r,xOA,X", 4 },
{ "lh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 },
{ "lnh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 },
{ "lw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 },
{ "lnw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 },
{ "ld", 0xb4000002, 0xfc080002, "r,xOA,X", 4 },
{ "lnd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 },
{ "li", 0xf8000000, 0xfc7f0000, "r,I", 4 },
{ "lpa", 0x50080000, 0xfc080000, "r,xOA,X", 4 },
{ "la", 0x50000000, 0xfc080000, "r,xOA,X", 4 },
{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 },
{ "lbp", 0x90080000, 0xfc080000, "r,xOA,X", 4 },
{ "lhp", 0x90000001, 0xfc080001, "r,xOA,X", 4 },
{ "lwp", 0x90000000, 0xfc080000, "r,xOA,X", 4 },
{ "ldp", 0x90000002, 0xfc080002, "r,xOA,X", 4 },
{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 },
{ "lf", 0xbc000000, 0xfc080000, "r,xOA,X", 4 },
{ "lfbr", 0xbc080000, 0xfc080000, "b,xOA,X", 4 },
{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 },
{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 },
{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 },
{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 },
{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 },
{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 },
{ "stfbr", 0xdc080000, 0xfc080000, "b,xOA,X", 4 },
{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 },
{ "zmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 },
{ "zmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 },
{ "zmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 },
{ "zmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 },
{ "stbp", 0x94080000, 0xfc080000, "r,xOA,X", 4 },
{ "sthp", 0x94000001, 0xfc080001, "r,xOA,X", 4 },
{ "stwp", 0x94000000, 0xfc080000, "r,xOA,X", 4 },
{ "stdp", 0x94000002, 0xfc080002, "r,xOA,X", 4 },
{ "lil", 0xf80b0000, 0xfc7f0000, "r,D", 4 },
{ "lwsl1", 0xec000000, 0xfc080000, "r,xOA,X", 4 },
{ "lwsl2", 0xfc000000, 0xfc080000, "r,xOA,X", 4 },
{ "lwsl3", 0xfc080000, 0xfc080000, "r,xOA,X", 4 },
{ "lvb", 0xb0080000, 0xfc080000, "v,xOA,X", 4 },
{ "lvh", 0xb0000001, 0xfc080001, "v,xOA,X", 4 },
{ "lvw", 0xb0000000, 0xfc080000, "v,xOA,X", 4 },
{ "lvd", 0xb0000002, 0xfc080002, "v,xOA,X", 4 },
{ "liv", 0x3c040000, 0xfc0f0000, "v,R", 2 },
{ "livf", 0x3c080000, 0xfc0f0000, "v,R", 2 },
{ "stvb", 0xd0080000, 0xfc080000, "v,xOA,X", 4 },
{ "stvh", 0xd0000001, 0xfc080001, "v,xOA,X", 4 },
{ "stvw", 0xd0000000, 0xfc080000, "v,xOA,X", 4 },
{ "stvd", 0xd0000002, 0xfc080002, "v,xOA,X", 4 },
{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 },
{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 },
{ "trnd", 0x2c0c0000, 0xfc0f0000, "r,R", 2 },
{ "trabs", 0x2c010000, 0xfc0f0000, "r,R", 2 },
{ "trabsd", 0x2c090000, 0xfc0f0000, "r,R", 2 },
{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 },
{ "xcr", 0x28040000, 0xfc0f0000, "r,R", 2 },
{ "cxcr", 0x2c060000, 0xfc0f0000, "r,R", 2 },
{ "cxcrd", 0x2c0e0000, 0xfc0f0000, "r,R", 2 },
{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 },
{ "trbr", 0x28030000, 0xfc0f0000, "b,R", 2 },
{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 },
{ "tbrbr", 0x28010000, 0xfc0f0000, "b,B", 2 },
{ "trvv", 0x28050000, 0xfc0f0000, "v,V", 2 },
{ "trvvn", 0x2c050000, 0xfc0f0000, "v,V", 2 },
{ "trvvnd", 0x2c0d0000, 0xfc0f0000, "v,V", 2 },
{ "trvab", 0x2c070000, 0xfc0f0000, "v,V", 2 },
{ "trvabd", 0x2c0f0000, 0xfc0f0000, "v,V", 2 },
{ "cmpv", 0x14060000, 0xfc0f0000, "v,V", 2 },
{ "expv", 0x14070000, 0xfc0f0000, "v,V", 2 },
{ "mrvvlt", 0x10030000, 0xfc0f0000, "v,V", 2 },
{ "mrvvle", 0x10040000, 0xfc0f0000, "v,V", 2 },
{ "mrvvgt", 0x14030000, 0xfc0f0000, "v,V", 2 },
{ "mrvvge", 0x14040000, 0xfc0f0000, "v,V", 2 },
{ "mrvveq", 0x10050000, 0xfc0f0000, "v,V", 2 },
{ "mrvvne", 0x10050000, 0xfc0f0000, "v,V", 2 },
{ "mrvrlt", 0x100d0000, 0xfc0f0000, "v,R", 2 },
{ "mrvrle", 0x100e0000, 0xfc0f0000, "v,R", 2 },
{ "mrvrgt", 0x140d0000, 0xfc0f0000, "v,R", 2 },
{ "mrvrge", 0x140e0000, 0xfc0f0000, "v,R", 2 },
{ "mrvreq", 0x100f0000, 0xfc0f0000, "v,R", 2 },
{ "mrvrne", 0x140f0000, 0xfc0f0000, "v,R", 2 },
{ "trvr", 0x140b0000, 0xfc0f0000, "r,V", 2 },
{ "trrv", 0x140c0000, 0xfc0f0000, "v,R", 2 },
{ "bu", 0x40000000, 0xff880000, "xOA,X", 4 },
{ "bns", 0x70080000, 0xff880000, "xOA,X", 4 },
{ "bnco", 0x70880000, 0xff880000, "xOA,X", 4 },
{ "bge", 0x71080000, 0xff880000, "xOA,X", 4 },
{ "bne", 0x71880000, 0xff880000, "xOA,X", 4 },
{ "bunge", 0x72080000, 0xff880000, "xOA,X", 4 },
{ "bunle", 0x72880000, 0xff880000, "xOA,X", 4 },
{ "bgt", 0x73080000, 0xff880000, "xOA,X", 4 },
{ "bnany", 0x73880000, 0xff880000, "xOA,X", 4 },
{ "bs" , 0x70000000, 0xff880000, "xOA,X", 4 },
{ "bco", 0x70800000, 0xff880000, "xOA,X", 4 },
{ "blt", 0x71000000, 0xff880000, "xOA,X", 4 },
{ "beq", 0x71800000, 0xff880000, "xOA,X", 4 },
{ "buge", 0x72000000, 0xff880000, "xOA,X", 4 },
{ "bult", 0x72800000, 0xff880000, "xOA,X", 4 },
{ "ble", 0x73000000, 0xff880000, "xOA,X", 4 },
{ "bany", 0x73800000, 0xff880000, "xOA,X", 4 },
{ "brlnk", 0x44000000, 0xfc080000, "r,xOA,X", 4 },
{ "bib", 0x48000000, 0xfc080000, "r,xOA,X", 4 },
{ "bih", 0x48080000, 0xfc080000, "r,xOA,X", 4 },
{ "biw", 0x4c000000, 0xfc080000, "r,xOA,X", 4 },
{ "bid", 0x4c080000, 0xfc080000, "r,xOA,X", 4 },
{ "bivb", 0x60000000, 0xfc080000, "r,xOA,X", 4 },
{ "bivh", 0x60080000, 0xfc080000, "r,xOA,X", 4 },
{ "bivw", 0x64000000, 0xfc080000, "r,xOA,X", 4 },
{ "bivd", 0x64080000, 0xfc080000, "r,xOA,X", 4 },
{ "bvsb", 0x68000000, 0xfc080000, "r,xOA,X", 4 },
{ "bvsh", 0x68080000, 0xfc080000, "r,xOA,X", 4 },
{ "bvsw", 0x6c000000, 0xfc080000, "r,xOA,X", 4 },
{ "bvsd", 0x6c080000, 0xfc080000, "r,xOA,X", 4 },
{ "camb", 0x80080000, 0xfc080000, "r,xOA,X", 4 },
{ "camh", 0x80000001, 0xfc080001, "r,xOA,X", 4 },
{ "camw", 0x80000000, 0xfc080000, "r,xOA,X", 4 },
{ "camd", 0x80000002, 0xfc080002, "r,xOA,X", 4 },
{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 },
{ "card", 0x14000000, 0xfc0f0000, "r,R", 2 },
{ "ci", 0xf8050000, 0xfc7f0000, "r,I", 4 },
{ "chkbnd", 0x5c080000, 0xfc080000, "r,xOA,X", 4 },
{ "cavv", 0x10010000, 0xfc0f0000, "v,V", 2 },
{ "cavr", 0x10020000, 0xfc0f0000, "v,R", 2 },
{ "cavvd", 0x10090000, 0xfc0f0000, "v,V", 2 },
{ "cavrd", 0x100b0000, 0xfc0f0000, "v,R", 2 },
{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 },
{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 },
{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 },
{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 },
{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 },
{ "ani", 0xf8080000, 0xfc7f0000, "r,I", 4 },
{ "ormb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 },
{ "ormh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 },
{ "ormw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 },
{ "ormd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 },
{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 },
{ "oi", 0xf8090000, 0xfc7f0000, "r,I", 4 },
{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 },
{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 },
{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 },
{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 },
{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 },
{ "eoi", 0xf80a0000, 0xfc7f0000, "r,I", 4 },
{ "anvv", 0x04010000, 0xfc0f0000, "v,V", 2 },
{ "anvr", 0x04020000, 0xfc0f0000, "v,R", 2 },
{ "orvv", 0x08010000, 0xfc0f0000, "v,V", 2 },
{ "orvr", 0x08020000, 0xfc0f0000, "v,R", 2 },
{ "eovv", 0x0c010000, 0xfc0f0000, "v,V", 2 },
{ "eovr", 0x0c020000, 0xfc0f0000, "v,R", 2 },
{ "sacz", 0x100c0000, 0xfc0f0000, "r,R", 2 },
{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 },
{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 },
{ "slc", 0x24400000, 0xfc600000, "r,S", 2 },
{ "slad", 0x20400000, 0xfc600000, "r,S", 2 },
{ "slld", 0x20600000, 0xfc600000, "r,S", 2 },
{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 },
{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 },
{ "src", 0x24000000, 0xfc600000, "r,S", 2 },
{ "srad", 0x20000000, 0xfc600000, "r,S", 2 },
{ "srld", 0x20200000, 0xfc600000, "r,S", 2 },
{ "sda", 0x3c030000, 0xfc0f0000, "r,R", 2 },
{ "sdl", 0x3c020000, 0xfc0f0000, "r,R", 2 },
{ "sdc", 0x3c010000, 0xfc0f0000, "r,R", 2 },
{ "sdad", 0x3c0b0000, 0xfc0f0000, "r,R", 2 },
{ "sdld", 0x3c0a0000, 0xfc0f0000, "r,R", 2 },
{ "svda", 0x3c070000, 0xfc0f0000, "v,R", 2 },
{ "svdl", 0x3c060000, 0xfc0f0000, "v,R", 2 },
{ "svdc", 0x3c050000, 0xfc0f0000, "v,R", 2 },
{ "svdad", 0x3c0e0000, 0xfc0f0000, "v,R", 2 },
{ "svdld", 0x3c0d0000, 0xfc0f0000, "v,R", 2 },
{ "sbm", 0xac080000, 0xfc080000, "f,xOA,X", 4 },
{ "zbm", 0xac000000, 0xfc080000, "f,xOA,X", 4 },
{ "tbm", 0xa8080000, 0xfc080000, "f,xOA,X", 4 },
{ "incmb", 0xa0000000, 0xfc080000, "xOA,X", 4 },
{ "incmh", 0xa0080000, 0xfc080000, "xOA,X", 4 },
{ "incmw", 0xa4000000, 0xfc080000, "xOA,X", 4 },
{ "incmd", 0xa4080000, 0xfc080000, "xOA,X", 4 },
{ "sbmd", 0x7c080000, 0xfc080000, "r,xOA,X", 4 },
{ "zbmd", 0x7c000000, 0xfc080000, "r,xOA,X", 4 },
{ "tbmd", 0x78080000, 0xfc080000, "r,xOA,X", 4 },
{ "ssm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 },
{ "zsm", 0x9c000000, 0xfc080000, "f,xOA,X", 4 },
{ "tsm", 0x98080000, 0xfc080000, "f,xOA,X", 4 },
{ "admb", 0xc8080000, 0xfc080000, "r,xOA,X", 4 },
{ "admh", 0xc8000001, 0xfc080001, "r,xOA,X", 4 },
{ "admw", 0xc8000000, 0xfc080000, "r,xOA,X", 4 },
{ "admd", 0xc8000002, 0xfc080002, "r,xOA,X", 4 },
{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 },
{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 },
{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 },
{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 },
{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 },
{ "adi", 0xf8010000, 0xfc0f0000, "r,I", 4 },
{ "sumb", 0xcc080000, 0xfc080000, "r,xOA,X", 4 },
{ "sumh", 0xcc000001, 0xfc080001, "r,xOA,X", 4 },
{ "sumw", 0xcc000000, 0xfc080000, "r,xOA,X", 4 },
{ "sumd", 0xcc000002, 0xfc080002, "r,xOA,X", 4 },
{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 },
{ "sui", 0xf8020000, 0xfc0f0000, "r,I", 4 },
{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 },
{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 },
{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 },
{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 },
{ "mprd", 0x3c0f0000, 0xfc0f0000, "r,R", 2 },
{ "mpi", 0xf8030000, 0xfc0f0000, "r,I", 4 },
{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 },
{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 },
{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 },
{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 },
{ "dvi", 0xf8040000, 0xfc0f0000, "r,I", 4 },
{ "exs", 0x38080000, 0xfc0f0000, "r,R", 2 },
{ "advv", 0x30000000, 0xfc0f0000, "v,V", 2 },
{ "advvd", 0x30080000, 0xfc0f0000, "v,V", 2 },
{ "adrv", 0x34000000, 0xfc0f0000, "v,R", 2 },
{ "adrvd", 0x34080000, 0xfc0f0000, "v,R", 2 },
{ "suvv", 0x30010000, 0xfc0f0000, "v,V", 2 },
{ "suvvd", 0x30090000, 0xfc0f0000, "v,V", 2 },
{ "surv", 0x34010000, 0xfc0f0000, "v,R", 2 },
{ "survd", 0x34090000, 0xfc0f0000, "v,R", 2 },
{ "mpvv", 0x30020000, 0xfc0f0000, "v,V", 2 },
{ "mprv", 0x34020000, 0xfc0f0000, "v,R", 2 },
{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 },
{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 },
{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 },
{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 },
{ "surfw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 },
{ "surfd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 },
{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 },
{ "surfd", 0x380b0000, 0xfc0f0000, "r,R", 2 },
{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 },
{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 },
{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 },
{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 },
{ "rfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 },
{ "rfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 },
{ "rrfw", 0x0c0e0000, 0xfc0f0000, "r", 2 },
{ "rrfd", 0x0c0f0000, 0xfc0f0000, "r", 2 },
{ "advvfw", 0x30040000, 0xfc0f0000, "v,V", 2 },
{ "advvfd", 0x300c0000, 0xfc0f0000, "v,V", 2 },
{ "adrvfw", 0x34040000, 0xfc0f0000, "v,R", 2 },
{ "adrvfd", 0x340c0000, 0xfc0f0000, "v,R", 2 },
{ "suvvfw", 0x30050000, 0xfc0f0000, "v,V", 2 },
{ "suvvfd", 0x300d0000, 0xfc0f0000, "v,V", 2 },
{ "survfw", 0x34050000, 0xfc0f0000, "v,R", 2 },
{ "survfd", 0x340d0000, 0xfc0f0000, "v,R", 2 },
{ "mpvvfw", 0x30060000, 0xfc0f0000, "v,V", 2 },
{ "mpvvfd", 0x300e0000, 0xfc0f0000, "v,V", 2 },
{ "mprvfw", 0x34060000, 0xfc0f0000, "v,R", 2 },
{ "mprvfd", 0x340e0000, 0xfc0f0000, "v,R", 2 },
{ "rvfw", 0x30070000, 0xfc0f0000, "v", 2 },
{ "rvfd", 0x300f0000, 0xfc0f0000, "v", 2 },
{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 },
{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 },
{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 },
{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 },
{ "cfpds", 0x3c090000, 0xfc0f0000, "r,R", 2 },
{ "fltvw", 0x080d0000, 0xfc0f0000, "v,V", 2 },
{ "fltvd", 0x080f0000, 0xfc0f0000, "v,V", 2 },
{ "fixvw", 0x080c0000, 0xfc0f0000, "v,V", 2 },
{ "fixvd", 0x080e0000, 0xfc0f0000, "v,V", 2 },
{ "cfpvds", 0x0c0d0000, 0xfc0f0000, "v,V", 2 },
{ "orvrn", 0x000a0000, 0xfc0f0000, "r,V", 2 },
{ "andvrn", 0x00080000, 0xfc0f0000, "r,V", 2 },
{ "frsteq", 0x04090000, 0xfc0f0000, "r,V", 2 },
{ "sigma", 0x0c080000, 0xfc0f0000, "r,V", 2 },
{ "sigmad", 0x0c0a0000, 0xfc0f0000, "r,V", 2 },
{ "sigmf", 0x08080000, 0xfc0f0000, "r,V", 2 },
{ "sigmfd", 0x080a0000, 0xfc0f0000, "r,V", 2 },
{ "prodf", 0x04080000, 0xfc0f0000, "r,V", 2 },
{ "prodfd", 0x040a0000, 0xfc0f0000, "r,V", 2 },
{ "maxv", 0x10080000, 0xfc0f0000, "r,V", 2 },
{ "maxvd", 0x100a0000, 0xfc0f0000, "r,V", 2 },
{ "minv", 0x14080000, 0xfc0f0000, "r,V", 2 },
{ "minvd", 0x140a0000, 0xfc0f0000, "r,V", 2 },
{ "lpsd", 0xf0000000, 0xfc080000, "xOA,X", 4 },
{ "ldc", 0xf0080000, 0xfc080000, "xOA,X", 4 },
{ "spm", 0x040c0000, 0xfc0f0000, "r", 2 },
{ "rpm", 0x040d0000, 0xfc0f0000, "r", 2 },
{ "tritr", 0x00070000, 0xfc0f0000, "r", 2 },
{ "trrit", 0x00060000, 0xfc0f0000, "r", 2 },
{ "rpswt", 0x04080000, 0xfc0f0000, "r", 2 },
{ "exr", 0xf8070000, 0xfc0f0000, "", 4 },
{ "halt", 0x00000000, 0xfc0f0000, "", 2 },
{ "wait", 0x00010000, 0xfc0f0000, "", 2 },
{ "nop", 0x00020000, 0xfc0f0000, "", 2 },
{ "eiae", 0x00030000, 0xfc0f0000, "", 2 },
{ "efae", 0x000d0000, 0xfc0f0000, "", 2 },
{ "diae", 0x000e0000, 0xfc0f0000, "", 2 },
{ "dfae", 0x000f0000, 0xfc0f0000, "", 2 },
{ "spvc", 0xf8060000, 0xfc0f0000, "r,T,N", 4 },
{ "rdsts", 0x00090000, 0xfc0f0000, "r", 2 },
{ "setcpu", 0x000c0000, 0xfc0f0000, "r", 2 },
{ "cmc", 0x000b0000, 0xfc0f0000, "r", 2 },
{ "trrcu", 0x00040000, 0xfc0f0000, "r", 2 },
{ "attnio", 0x00050000, 0xfc0f0000, "", 2 },
{ "fudit", 0x28080000, 0xfc0f0000, "", 2 },
{ "break", 0x28090000, 0xfc0f0000, "", 2 },
{ "frzss", 0x280a0000, 0xfc0f0000, "", 2 },
{ "ripi", 0x04040000, 0xfc0f0000, "r,R", 2 },
{ "xcp", 0x04050000, 0xfc0f0000, "r", 2 },
{ "block", 0x04060000, 0xfc0f0000, "", 2 },
{ "unblock", 0x04070000, 0xfc0f0000, "", 2 },
{ "trsc", 0x08060000, 0xfc0f0000, "r,R", 2 },
{ "tscr", 0x08070000, 0xfc0f0000, "r,R", 2 },
{ "fq", 0x04080000, 0xfc0f0000, "r", 2 },
{ "flupte", 0x2c080000, 0xfc0f0000, "r", 2 },
{ "rviu", 0x040f0000, 0xfc0f0000, "", 2 },
{ "ldel", 0x280c0000, 0xfc0f0000, "r,R", 2 },
{ "ldu", 0x280d0000, 0xfc0f0000, "r,R", 2 },
{ "stdecc", 0x280b0000, 0xfc0f0000, "r,R", 2 },
{ "trpc", 0x08040000, 0xfc0f0000, "r", 2 },
{ "tpcr", 0x08050000, 0xfc0f0000, "r", 2 },
{ "ghalt", 0x0c050000, 0xfc0f0000, "r", 2 },
{ "grun", 0x0c040000, 0xfc0f0000, "", 2 },
{ "tmpr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 },
{ "trmp", 0x2c0b0000, 0xfc0f0000, "r,R", 2 },
{ "trrve", 0x28060000, 0xfc0f0000, "r", 2 },
{ "trver", 0x28070000, 0xfc0f0000, "r", 2 },
{ "trvlr", 0x280f0000, 0xfc0f0000, "r", 2 },
{ "linkfl", 0x18000000, 0xfc0f0000, "r,R", 2 },
{ "linkbl", 0x18020000, 0xfc0f0000, "r,R", 2 },
{ "linkfp", 0x18010000, 0xfc0f0000, "r,R", 2 },
{ "linkbp", 0x18030000, 0xfc0f0000, "r,R", 2 },
{ "linkpl", 0x18040000, 0xfc0f0000, "r,R", 2 },
{ "ulinkl", 0x18080000, 0xfc0f0000, "r,R", 2 },
{ "ulinkp", 0x18090000, 0xfc0f0000, "r,R", 2 },
{ "ulinktl", 0x180a0000, 0xfc0f0000, "r,R", 2 },
{ "ulinktp", 0x180b0000, 0xfc0f0000, "r,R", 2 },
};
int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]);
struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) /
sizeof(gld_opcodes[0]);

491
include/ns32k-opcode.h Executable file
View File

@ -0,0 +1,491 @@
/* ns32k-opcode.h -- Opcode table for National Semi 32k processor
Copyright (C) 1987 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 1, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
#ifdef SEQUENT_COMPATABILITY
#define DEF_MODEC 20
#define DEF_MODEL 21
#endif
#ifndef DEF_MODEC
#define DEF_MODEC 20
#endif
#ifndef DEF_MODEL
#define DEF_MODEL 20
#endif
/*
After deciding the instruction entry (via hash.c) the instruction parser
will try to match the operands after the instruction to the required set
given in the entry operandfield. Every operand will result in a change in
the opcode or the addition of data to the opcode.
The operands in the source instruction are checked for inconsistent
semantics.
F : 32 bit float general form
L : 64 bit float "
B : byte "
W : word "
D : double-word "
Q : quad-word "
A : double-word gen-address-form ie no regs allowed
d : displacement
b : displacement - pc relative addressing acb
p : displacement - pc relative addressing br bcond bsr cxp
q : quick
i : immediate (8 bits)
This is not a standard ns32k operandtype, it is used to build
instructions like svc arg1,arg2
Svc is the instruction SuperVisorCall and is sometimes used to
call OS-routines from usermode. Some args might be handy!
r : register number (3 bits)
O : setcfg instruction optionslist
C : cinv instruction optionslist
S : stringinstruction optionslist
U : registerlist save,enter
u : registerlist restore,exit
M : mmu register
P : cpu register
g : 3:rd operand of inss or exts instruction
G : 4:th operand of inss or exts instruction
Those operands are encoded in the same byte.
This byte is placed last in the instruction.
f : operand of sfsr
H : sequent-hack for bsr (Warning)
column 1 instructions
2 number of bits in opcode.
3 number of bits in opcode explicitly
determined by the instruction type.
4 opcodeseed, the number we build our opcode
from.
5 operandtypes, used by operandparser.
6 size in bytes of immediate
*/
struct ns32k_opcode {
char *name;
unsigned char opcode_id_size; /* not used by the assembler */
unsigned char opcode_size;
unsigned long opcode_seed;
char *operands;
unsigned char im_size; /* not used by dissassembler */
char *default_args; /* default to those args when none given */
char default_modec; /* default to this addr-mode when ambigous
ie when the argument of a general addr-mode
is a plain constant */
char default_model; /* is a plain label */
};
#ifdef comment
/* This section was from the gdb version of this file. */
#ifndef ns32k_opcodeT
#define ns32k_opcodeT int
#endif /* no ns32k_opcodeT */
struct not_wot /* ns32k opcode table: wot to do with this */
/* particular opcode */
{
int obits; /* number of opcode bits */
int ibits; /* number of instruction bits */
ns32k_opcodeT code; /* op-code (may be > 8 bits!) */
char *args; /* how to compile said opcode */
};
struct not /* ns32k opcode text */
{
char * name; /* opcode name: lowercase string [key] */
struct not_wot detail; /* rest of opcode table [datum] */
};
/* Instructions look like this:
basic instruction--1, 2, or 3 bytes
index byte for operand A, if operand A is indexed--1 byte
index byte for operand B, if operand B is indexed--1 byte
addressing extension for operand A
addressing extension for operand B
implied operands
Operand A is the operand listed first in the following opcode table.
Operand B is the operand listed second in the following opcode table.
All instructions have at most 2 general operands, so this is enough.
The implied operands are associated with operands other than A and B.
Each operand has a digit and a letter.
The digit gives the position in the assembly language. The letter,
one of the following, tells us what kind of operand it is. */
/* F : 32 bit float
* L : 64 bit float
* B : byte
* W : word
* D : double-word
* Q : quad-word
* d : displacement
* q : quick
* i : immediate (8 bits)
* r : register number (3 bits)
* p : displacement - pc relative addressing
*/
#endif /* comment */
static const struct ns32k_opcode ns32k_opcodes[]=
{
{ "absf", 14,24, 0x35be, "1F2F", 4, "", DEF_MODEC,DEF_MODEL },
{ "absl", 14,24, 0x34be, "1L2L", 8, "", DEF_MODEC,DEF_MODEL },
{ "absb", 14,24, 0x304e, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "absw", 14,24, 0x314e, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "absd", 14,24, 0x334e, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "acbb", 7,16, 0x4c, "2B1q3p", 1, "", DEF_MODEC,DEF_MODEL },
{ "acbw", 7,16, 0x4d, "2W1q3p", 2, "", DEF_MODEC,DEF_MODEL },
{ "acbd", 7,16, 0x4f, "2D1q3p", 4, "", DEF_MODEC,DEF_MODEL },
{ "addf", 14,24, 0x01be, "1F2F", 4, "", DEF_MODEC,DEF_MODEL },
{ "addl", 14,24, 0x00be, "1L2L", 8, "", DEF_MODEC,DEF_MODEL },
{ "addb", 6,16, 0x00, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "addw", 6,16, 0x01, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "addd", 6,16, 0x03, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "addcb", 6,16, 0x10, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "addcw", 6,16, 0x11, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "addcd", 6,16, 0x13, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "addpb", 14,24, 0x3c4e, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "addpw", 14,24, 0x3d4e, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "addpd", 14,24, 0x3f4e, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "addqb", 7,16, 0x0c, "2B1q", 1, "", DEF_MODEC,DEF_MODEL },
{ "addqw", 7,16, 0x0d, "2W1q", 2, "", DEF_MODEC,DEF_MODEL },
{ "addqd", 7,16, 0x0f, "2D1q", 4, "", DEF_MODEC,DEF_MODEL },
{ "addr", 6,16, 0x27, "1A2D", 4, "", 21,21 },
{ "adjspb", 11,16, 0x057c, "1B", 1, "", DEF_MODEC,DEF_MODEL },
{ "adjspw", 11,16, 0x057d, "1W", 2, "", DEF_MODEC,DEF_MODEL },
{ "adjspd", 11,16, 0x057f, "1D", 4, "", DEF_MODEC,DEF_MODEL },
{ "andb", 6,16, 0x28, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "andw", 6,16, 0x29, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "andd", 6,16, 0x2b, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "ashb", 14,24, 0x044e, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "ashw", 14,24, 0x054e, "1B2W", 1, "", DEF_MODEC,DEF_MODEL },
{ "ashd", 14,24, 0x074e, "1B2D", 1, "", DEF_MODEC,DEF_MODEL },
{ "beq", 8,8, 0x0a, "1p", 0, "", 21,21 },
{ "bne", 8,8, 0x1a, "1p", 0, "", 21,21 },
{ "bcs", 8,8, 0x2a, "1p", 0, "", 21,21 },
{ "bcc", 8,8, 0x3a, "1p", 0, "", 21,21 },
{ "bhi", 8,8, 0x4a, "1p", 0, "", 21,21 },
{ "bls", 8,8, 0x5a, "1p", 0, "", 21,21 },
{ "bgt", 8,8, 0x6a, "1p", 0, "", 21,21 },
{ "ble", 8,8, 0x7a, "1p", 0, "", 21,21 },
{ "bfs", 8,8, 0x8a, "1p", 0, "", 21,21 },
{ "bfc", 8,8, 0x9a, "1p", 0, "", 21,21 },
{ "blo", 8,8, 0xaa, "1p", 0, "", 21,21 },
{ "bhs", 8,8, 0xba, "1p", 0, "", 21,21 },
{ "blt", 8,8, 0xca, "1p", 0, "", 21,21 },
{ "bge", 8,8, 0xda, "1p", 0, "", 21,21 },
{ "but", 8,8, 0xea, "1p", 0, "", 21,21 },
{ "buf", 8,8, 0xfa, "1p", 0, "", 21,21 },
{ "bicb", 6,16, 0x08, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "bicw", 6,16, 0x09, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "bicd", 6,16, 0x0b, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "bicpsrb", 11,16, 0x17c, "1B", 1, "", DEF_MODEC,DEF_MODEL },
{ "bicpsrw", 11,16, 0x17d, "1W", 2, "", DEF_MODEC,DEF_MODEL },
{ "bispsrb", 11,16, 0x37c, "1B", 1, "", DEF_MODEC,DEF_MODEL },
{ "bispsrw", 11,16, 0x37d, "1W", 2, "", DEF_MODEC,DEF_MODEL },
{ "bpt", 8,8, 0xf2, "", 0, "", DEF_MODEC,DEF_MODEL },
{ "br", 8,8, 0xea, "1p", 0, "", 21,21 },
#ifdef SEQUENT_COMPATABILITY
{ "bsr", 8,8, 0x02, "1H", 0, "", 21,21 },
#else
{ "bsr", 8,8, 0x02, "1p", 0, "", 21,21 },
#endif
{ "caseb", 11,16, 0x77c, "1B", 1, "", DEF_MODEC,DEF_MODEL },
{ "casew", 11,16, 0x77d, "1W", 2, "", DEF_MODEC,DEF_MODEL },
{ "cased", 11,16, 0x77f, "1D", 4, "", DEF_MODEC,DEF_MODEL },
{ "cbitb", 14,24, 0x084e, "1B2D", 1, "", DEF_MODEC,DEF_MODEL },
{ "cbitw", 14,24, 0x094e, "1W2D", 2, "", DEF_MODEC,DEF_MODEL },
{ "cbitd", 14,24, 0x0b4e, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "cbitib", 14,24, 0x0c4e, "1B2D", 1, "", DEF_MODEC,DEF_MODEL },
{ "cbitiw", 14,24, 0x0d4e, "1W2D", 2, "", DEF_MODEC,DEF_MODEL },
{ "cbitid", 14,24, 0x0f4e, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "checkb", 11,24, 0x0ee, "2A3B1r", 1, "", DEF_MODEC,DEF_MODEL },
{ "checkw", 11,24, 0x1ee, "2A3W1r", 2, "", DEF_MODEC,DEF_MODEL },
{ "checkd", 11,24, 0x3ee, "2A3D1r", 4, "", DEF_MODEC,DEF_MODEL },
{ "cinv", 14,24, 0x271e, "2D1C", 4, "", DEF_MODEC,DEF_MODEL },
{ "cmpf", 14,24, 0x09be, "1F2F", 4, "", DEF_MODEC,DEF_MODEL },
{ "cmpl", 14,24, 0x08be, "1L2L", 8, "", DEF_MODEC,DEF_MODEL },
{ "cmpb", 6,16, 0x04, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "cmpw", 6,16, 0x05, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "cmpd", 6,16, 0x07, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "cmpmb", 14,24, 0x04ce, "1A2A3b", 1, "", DEF_MODEC,DEF_MODEL },
{ "cmpmw", 14,24, 0x05ce, "1A2A3b", 2, "", DEF_MODEC,DEF_MODEL },
{ "cmpmd", 14,24, 0x07ce, "1A2A3b", 4, "", DEF_MODEC,DEF_MODEL },
{ "cmpqb", 7,16, 0x1c, "2B1q", 1, "", DEF_MODEC,DEF_MODEL },
{ "cmpqw", 7,16, 0x1d, "2W1q", 2, "", DEF_MODEC,DEF_MODEL },
{ "cmpqd", 7,16, 0x1f, "2D1q", 4, "", DEF_MODEC,DEF_MODEL },
{ "cmpsb", 16,24, 0x040e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "cmpsw", 16,24, 0x050e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "cmpsd", 16,24, 0x070e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "cmpst", 16,24, 0x840e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "comb", 14,24, 0x344e, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "comw", 14,24, 0x354e, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "comd", 14,24, 0x374e, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "cvtp", 11,24, 0x036e, "2A3D1r", 4, "", DEF_MODEC,DEF_MODEL },
{ "cxp", 8,8, 0x22, "1p", 0, "", 21,21 },
{ "cxpd", 11,16, 0x07f, "1A", 4, "", DEF_MODEC,DEF_MODEL },
{ "deib", 14,24, 0x2cce, "1B2W", 1, "", DEF_MODEC,DEF_MODEL },
{ "deiw", 14,24, 0x2dce, "1W2D", 2, "", DEF_MODEC,DEF_MODEL },
{ "deid", 14,24, 0x2fce, "1D2Q", 4, "", DEF_MODEC,DEF_MODEL },
{ "dia", 8,8, 0xc2, "", 1, "", DEF_MODEC,DEF_MODEL },
{ "divf", 14,24, 0x21be, "1F2F", 4, "", DEF_MODEC,DEF_MODEL },
{ "divl", 14,24, 0x20be, "1L2L", 8, "", DEF_MODEC,DEF_MODEL },
{ "divb", 14,24, 0x3cce, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "divw", 14,24, 0x3dce, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "divd", 14,24, 0x3fce, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "enter", 8,8, 0x82, "1U2d", 0, "", DEF_MODEC,DEF_MODEL },
{ "exit", 8,8, 0x92, "1u", 0, "", DEF_MODEC,DEF_MODEL },
{ "extb", 11,24, 0x02e, "2D3B1r4d", 1, "", DEF_MODEC,DEF_MODEL },
{ "extw", 11,24, 0x12e, "2D3W1r4d", 2, "", DEF_MODEC,DEF_MODEL },
{ "extd", 11,24, 0x32e, "2D3D1r4d", 4, "", DEF_MODEC,DEF_MODEL },
{ "extsb", 14,24, 0x0cce, "1D2B3g4G", 1, "", DEF_MODEC,DEF_MODEL },
{ "extsw", 14,24, 0x0dce, "1D2W3g4G", 2, "", DEF_MODEC,DEF_MODEL },
{ "extsd", 14,24, 0x0fce, "1D2D3g4G", 4, "", DEF_MODEC,DEF_MODEL },
{ "ffsb", 14,24, 0x046e, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "ffsw", 14,24, 0x056e, "1W2B", 2, "", DEF_MODEC,DEF_MODEL },
{ "ffsd", 14,24, 0x076e, "1D2B", 4, "", DEF_MODEC,DEF_MODEL },
{ "flag", 8,8, 0xd2, "", 0, "", DEF_MODEC,DEF_MODEL },
{ "floorfb", 14,24, 0x3c3e, "1F2B", 4, "", DEF_MODEC,DEF_MODEL },
{ "floorfw", 14,24, 0x3d3e, "1F2W", 4, "", DEF_MODEC,DEF_MODEL },
{ "floorfd", 14,24, 0x3f3e, "1F2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "floorlb", 14,24, 0x383e, "1L2B", 8, "", DEF_MODEC,DEF_MODEL },
{ "floorlw", 14,24, 0x393e, "1L2W", 8, "", DEF_MODEC,DEF_MODEL },
{ "floorld", 14,24, 0x3b3e, "1L2D", 8, "", DEF_MODEC,DEF_MODEL },
{ "ibitb", 14,24, 0x384e, "1B2D", 1, "", DEF_MODEC,DEF_MODEL },
{ "ibitw", 14,24, 0x394e, "1W2D", 2, "", DEF_MODEC,DEF_MODEL },
{ "ibitd", 14,24, 0x3b4e, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "indexb", 11,24, 0x42e, "2B3B1r", 1, "", DEF_MODEC,DEF_MODEL },
{ "indexw", 11,24, 0x52e, "2W3W1r", 2, "", DEF_MODEC,DEF_MODEL },
{ "indexd", 11,24, 0x72e, "2D3D1r", 4, "", DEF_MODEC,DEF_MODEL },
{ "insb", 11,24, 0x0ae, "2B3B1r4d", 1, "", DEF_MODEC,DEF_MODEL },
{ "insw", 11,24, 0x1ae, "2W3W1r4d", 2, "", DEF_MODEC,DEF_MODEL },
{ "insd", 11,24, 0x3ae, "2D3D1r4d", 4, "", DEF_MODEC,DEF_MODEL },
{ "inssb", 14,24, 0x08ce, "1B2D3g4G", 1, "", DEF_MODEC,DEF_MODEL },
{ "inssw", 14,24, 0x09ce, "1W2D3g4G", 2, "", DEF_MODEC,DEF_MODEL },
{ "inssd", 14,24, 0x0bce, "1D2D3g4G", 4, "", DEF_MODEC,DEF_MODEL },
{ "jsr", 11,16, 0x67f, "1A", 4, "", 21,21 },
{ "jump", 11,16, 0x27f, "1A", 4, "", 21,21 },
{ "lfsr", 19,24, 0x00f3e,"1D", 4, "", DEF_MODEC,DEF_MODEL },
{ "lmr", 15,24, 0x0b1e, "2D1M", 4, "", DEF_MODEC,DEF_MODEL },
{ "lprb", 7,16, 0x6c, "2B1P", 1, "", DEF_MODEC,DEF_MODEL },
{ "lprw", 7,16, 0x6d, "2W1P", 2, "", DEF_MODEC,DEF_MODEL },
{ "lprd", 7,16, 0x6f, "2D1P", 4, "", DEF_MODEC,DEF_MODEL },
{ "lshb", 14,24, 0x144e, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "lshw", 14,24, 0x154e, "1B2W", 1, "", DEF_MODEC,DEF_MODEL },
{ "lshd", 14,24, 0x174e, "1B2D", 1, "", DEF_MODEC,DEF_MODEL },
{ "meib", 14,24, 0x24ce, "1B2W", 1, "", DEF_MODEC,DEF_MODEL },
{ "meiw", 14,24, 0x25ce, "1W2D", 2, "", DEF_MODEC,DEF_MODEL },
{ "meid", 14,24, 0x27ce, "1D2Q", 4, "", DEF_MODEC,DEF_MODEL },
{ "modb", 14,24, 0x38ce, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "modw", 14,24, 0x39ce, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "modd", 14,24, 0x3bce, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "movf", 14,24, 0x05be, "1F2F", 4, "", DEF_MODEC,DEF_MODEL },
{ "movl", 14,24, 0x04be, "1L2L", 8, "", DEF_MODEC,DEF_MODEL },
{ "movb", 6,16, 0x14, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "movw", 6,16, 0x15, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "movd", 6,16, 0x17, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "movbf", 14,24, 0x043e, "1B2F", 1, "", DEF_MODEC,DEF_MODEL },
{ "movwf", 14,24, 0x053e, "1W2F", 2, "", DEF_MODEC,DEF_MODEL },
{ "movdf", 14,24, 0x073e, "1D2F", 4, "", DEF_MODEC,DEF_MODEL },
{ "movbl", 14,24, 0x003e, "1B2L", 1, "", DEF_MODEC,DEF_MODEL },
{ "movwl", 14,24, 0x013e, "1W2L", 2, "", DEF_MODEC,DEF_MODEL },
{ "movdl", 14,24, 0x033e, "1D2L", 4, "", DEF_MODEC,DEF_MODEL },
{ "movfl", 14,24, 0x1b3e, "1F2L", 4, "", DEF_MODEC,DEF_MODEL },
{ "movlf", 14,24, 0x163e, "1L2F", 8, "", DEF_MODEC,DEF_MODEL },
{ "movmb", 14,24, 0x00ce, "1A2A3b", 1, "", DEF_MODEC,DEF_MODEL },
{ "movmw", 14,24, 0x01ce, "1A2A3b", 2, "", DEF_MODEC,DEF_MODEL },
{ "movmd", 14,24, 0x03ce, "1A2A3b", 4, "", DEF_MODEC,DEF_MODEL },
{ "movqb", 7,16, 0x5c, "2B1q", 1, "", DEF_MODEC,DEF_MODEL },
{ "movqw", 7,16, 0x5d, "2B1q", 2, "", DEF_MODEC,DEF_MODEL },
{ "movqd", 7,16, 0x5f, "2B1q", 4, "", DEF_MODEC,DEF_MODEL },
{ "movsb", 16,24, 0x000e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "movsw", 16,24, 0x010e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "movsd", 16,24, 0x030e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "movst", 16,24, 0x800e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "movsub", 14,24, 0x0cae, "1A2A", 1, "", DEF_MODEC,DEF_MODEL },
{ "movsuw", 14,24, 0x0dae, "1A2A", 2, "", DEF_MODEC,DEF_MODEL },
{ "movsud", 14,24, 0x0fae, "1A2A", 4, "", DEF_MODEC,DEF_MODEL },
{ "movusb", 14,24, 0x1cae, "1A2A", 1, "", DEF_MODEC,DEF_MODEL },
{ "movusw", 14,24, 0x1dae, "1A2A", 2, "", DEF_MODEC,DEF_MODEL },
{ "movusd", 14,24, 0x1fae, "1A2A", 4, "", DEF_MODEC,DEF_MODEL },
{ "movxbd", 14,24, 0x1cce, "1B2D", 1, "", DEF_MODEC,DEF_MODEL },
{ "movxwd", 14,24, 0x1dce, "1W2D", 2, "", DEF_MODEC,DEF_MODEL },
{ "movxbw", 14,24, 0x10ce, "1B2W", 1, "", DEF_MODEC,DEF_MODEL },
{ "movzbd", 14,24, 0x18ce, "1B2D", 1, "", DEF_MODEC,DEF_MODEL },
{ "movzwd", 14,24, 0x19ce, "1W2D", 2, "", DEF_MODEC,DEF_MODEL },
{ "movzbw", 14,24, 0x14ce, "1B2W", 1, "", DEF_MODEC,DEF_MODEL },
{ "mulf", 14,24, 0x31be, "1F2F", 4, "", DEF_MODEC,DEF_MODEL },
{ "mull", 14,24, 0x30be, "1L2L", 8, "", DEF_MODEC,DEF_MODEL },
{ "mulb", 14,24, 0x20ce, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "mulw", 14,24, 0x21ce, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "muld", 14,24, 0x23ce, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "negf", 14,24, 0x15be, "1F2F", 4, "", DEF_MODEC,DEF_MODEL },
{ "negl", 14,24, 0x14be, "1L2L", 8, "", DEF_MODEC,DEF_MODEL },
{ "negb", 14,24, 0x204e, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "negw", 14,24, 0x214e, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "negd", 14,24, 0x234e, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "nop", 8,8, 0xa2, "", 0, "", DEF_MODEC,DEF_MODEL },
{ "notb", 14,24, 0x244e, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "notw", 14,24, 0x254e, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "notd", 14,24, 0x274e, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "orb", 6,16, 0x18, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "orw", 6,16, 0x19, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "ord", 6,16, 0x1b, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "quob", 14,24, 0x30ce, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "quow", 14,24, 0x31ce, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "quod", 14,24, 0x33ce, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "rdval", 19,24, 0x0031e,"1A", 4, "", DEF_MODEC,DEF_MODEL },
{ "remb", 14,24, 0x34ce, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "remw", 14,24, 0x35ce, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "remd", 14,24, 0x37ce, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "restore", 8,8, 0x72, "1u", 0, "", DEF_MODEC,DEF_MODEL },
{ "ret", 8,8, 0x12, "1d", 0, "", DEF_MODEC,DEF_MODEL },
{ "reti", 8,8, 0x52, "", 0, "", DEF_MODEC,DEF_MODEL },
{ "rett", 8,8, 0x42, "1d", 0, "", DEF_MODEC,DEF_MODEL },
{ "rotb", 14,24, 0x004e, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "rotw", 14,24, 0x014e, "1B2W", 1, "", DEF_MODEC,DEF_MODEL },
{ "rotd", 14,24, 0x034e, "1B2D", 1, "", DEF_MODEC,DEF_MODEL },
{ "roundfb", 14,24, 0x243e, "1F2B", 4, "", DEF_MODEC,DEF_MODEL },
{ "roundfw", 14,24, 0x253e, "1F2W", 4, "", DEF_MODEC,DEF_MODEL },
{ "roundfd", 14,24, 0x273e, "1F2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "roundlb", 14,24, 0x203e, "1L2B", 8, "", DEF_MODEC,DEF_MODEL },
{ "roundlw", 14,24, 0x213e, "1L2W", 8, "", DEF_MODEC,DEF_MODEL },
{ "roundld", 14,24, 0x233e, "1L2D", 8, "", DEF_MODEC,DEF_MODEL },
{ "rxp", 8,8, 0x32, "1d", 0, "", DEF_MODEC,DEF_MODEL },
{ "seqb", 11,16, 0x3c, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "seqw", 11,16, 0x3d, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "seqd", 11,16, 0x3f, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sneb", 11,16, 0xbc, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "snew", 11,16, 0xbd, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sned", 11,16, 0xbf, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "scsb", 11,16, 0x13c, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "scsw", 11,16, 0x13d, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "scsd", 11,16, 0x13f, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sccb", 11,16, 0x1bc, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "sccw", 11,16, 0x1bd, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sccd", 11,16, 0x1bf, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "shib", 11,16, 0x23c, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "shiw", 11,16, 0x23d, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "shid", 11,16, 0x23f, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "slsb", 11,16, 0x2bc, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "slsw", 11,16, 0x2bd, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "slsd", 11,16, 0x2bf, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sgtb", 11,16, 0x33c, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "sgtw", 11,16, 0x33d, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sgtd", 11,16, 0x33f, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sleb", 11,16, 0x3bc, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "slew", 11,16, 0x3bd, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sled", 11,16, 0x3bf, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sfsb", 11,16, 0x43c, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "sfsw", 11,16, 0x43d, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sfsd", 11,16, 0x43f, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sfcb", 11,16, 0x4bc, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "sfcw", 11,16, 0x4bd, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sfcd", 11,16, 0x4bf, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "slob", 11,16, 0x53c, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "slow", 11,16, 0x53d, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "slod", 11,16, 0x53f, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "shsb", 11,16, 0x5bc, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "shsw", 11,16, 0x5bd, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "shsd", 11,16, 0x5bf, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sltb", 11,16, 0x63c, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "sltw", 11,16, 0x63d, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sltd", 11,16, 0x63f, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sgeb", 11,16, 0x6bc, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "sgew", 11,16, 0x6bd, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sged", 11,16, 0x6bf, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sutb", 11,16, 0x73c, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "sutw", 11,16, 0x73d, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sutd", 11,16, 0x73f, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sufb", 11,16, 0x7bc, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "sufw", 11,16, 0x7bd, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sufd", 11,16, 0x7bf, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "save", 8,8, 0x62, "1U", 0, "", DEF_MODEC,DEF_MODEL },
{ "sbitb", 14,24, 0x184e, "1B2A", 1, "", DEF_MODEC,DEF_MODEL },
{ "sbitw", 14,24, 0x194e, "1W2A", 2, "", DEF_MODEC,DEF_MODEL },
{ "sbitd", 14,24, 0x1b4e, "1D2A", 4, "", DEF_MODEC,DEF_MODEL },
{ "sbitib", 14,24, 0x1c4e, "1B2A", 1, "", DEF_MODEC,DEF_MODEL },
{ "sbitiw", 14,24, 0x1d4e, "1W2A", 2, "", DEF_MODEC,DEF_MODEL },
{ "sbitid", 14,24, 0x1f4e, "1D2A", 4, "", DEF_MODEC,DEF_MODEL },
{ "setcfg", 15,24, 0x0b0e, "1O", 0, "", DEF_MODEC,DEF_MODEL },
{ "sfsr", 14,24, 0x373e, "1f", 0, "", DEF_MODEC,DEF_MODEL },
{ "skpsb", 16,24, 0x0c0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "skpsw", 16,24, 0x0d0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "skpsd", 16,24, 0x0f0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "skpst", 16,24, 0x8c0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "smr", 15,24, 0x0f1e, "2D1M", 4, "", DEF_MODEC,DEF_MODEL },
{ "sprb", 7,16, 0x2c, "2B1P", 1, "", DEF_MODEC,DEF_MODEL },
{ "sprw", 7,16, 0x2d, "2W1P", 2, "", DEF_MODEC,DEF_MODEL },
{ "sprd", 7,16, 0x2f, "2D1P", 4, "", DEF_MODEC,DEF_MODEL },
{ "subf", 14,24, 0x11be, "1F2F", 4, "", DEF_MODEC,DEF_MODEL },
{ "subl", 14,24, 0x10be, "1L2L", 8, "", DEF_MODEC,DEF_MODEL },
{ "subb", 6,16, 0x20, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "subw", 6,16, 0x21, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "subd", 6,16, 0x23, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "subcb", 6,16, 0x30, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "subcw", 6,16, 0x31, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "subcd", 6,16, 0x33, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "subpb", 14,24, 0x2c4e, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "subpw", 14,24, 0x2d4e, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "subpd", 14,24, 0x2f4e, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
#ifdef NS32K_SVC_IMMED_OPERANDS
{ "svc", 8,8, 0xe2, "2i1i", 1, "", DEF_MODEC,DEF_MODEL }, /* not really, but unix uses it */
#else
{ "svc", 8,8, 0xe2, "", 0, "", DEF_MODEC,DEF_MODEL },
#endif
{ "tbitb", 6,16, 0x34, "1B2A", 1, "", DEF_MODEC,DEF_MODEL },
{ "tbitw", 6,16, 0x35, "1W2A", 2, "", DEF_MODEC,DEF_MODEL },
{ "tbitd", 6,16, 0x37, "1D2A", 4, "", DEF_MODEC,DEF_MODEL },
{ "truncfb", 14,24, 0x2c3e, "1F2B", 4, "", DEF_MODEC,DEF_MODEL },
{ "truncfw", 14,24, 0x2d3e, "1F2W", 4, "", DEF_MODEC,DEF_MODEL },
{ "truncfd", 14,24, 0x2f3e, "1F2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "trunclb", 14,24, 0x283e, "1L2B", 8, "", DEF_MODEC,DEF_MODEL },
{ "trunclw", 14,24, 0x293e, "1L2W", 8, "", DEF_MODEC,DEF_MODEL },
{ "truncld", 14,24, 0x2b3e, "1L2D", 8, "", DEF_MODEC,DEF_MODEL },
{ "wait", 8,8, 0xb2, "", 0, "", DEF_MODEC,DEF_MODEL },
{ "wrval", 19,24, 0x0071e,"1A", 0, "", DEF_MODEC,DEF_MODEL },
{ "xorb", 6,16, 0x38, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "xorw", 6,16, 0x39, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "xord", 6,16, 0x3b, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
#if defined(NS32381) /* I'm not too sure of these */
{ "dotf", 14,24, 0x0dfe, "1F2F", 4, "", DEF_MODEC,DEF_MODEL },
{ "dotl", 14,24, 0x0cfe, "1L2L", 8, "", DEF_MODEC,DEF_MODEL },
{ "logbf", 14,24, 0x15fe, "1F2F", 4, "", DEF_MODEC,DEF_MODEL },
{ "logbl", 14,24, 0x14fe, "1L2L", 8, "", DEF_MODEC,DEF_MODEL },
{ "polyf", 14,24, 0x09fe, "1F2F", 4, "", DEF_MODEC,DEF_MODEL },
{ "polyl", 14,24, 0x08fe, "1L2L", 8, "", DEF_MODEC,DEF_MODEL },
{ "scalbf", 14,24, 0x11fe, "1F2F", 4, "", DEF_MODEC,DEF_MODEL },
{ "scalbl", 14,24, 0x10fe, "1L2L", 8, "", DEF_MODEC,DEF_MODEL },
#endif
};
static const int numopcodes=sizeof(ns32k_opcodes)/sizeof(ns32k_opcodes[0]);
static const struct ns32k_opcode *endop = ns32k_opcodes+sizeof(ns32k_opcodes)/sizeof(ns32k_opcodes[0]);
#define MAX_ARGS 4
#define ARG_LEN 50

282
include/pn-opcode.h Executable file
View File

@ -0,0 +1,282 @@
/* Print GOULD PN (PowerNode) instructions for GDB, the GNU debugger.
Copyright (C) 1986, 1987, 1989 Free Software Foundation, Inc.
This file is part of GDB.
GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 1, or (at your option)
any later version.
GDB is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GDB; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
struct gld_opcode
{
char *name;
unsigned long opcode;
unsigned long mask;
char *args;
int length;
};
/* We store four bytes of opcode for all opcodes because that
is the most any of them need. The actual length of an instruction
is always at least 2 bytes, and at most four. The length of the
instruction is based on the opcode.
The mask component is a mask saying which bits must match
particular opcode in order for an instruction to be an instance
of that opcode.
The args component is a string containing characters
that are used to format the arguments to the instruction. */
/* Kinds of operands:
r Register in first field
R Register in second field
b Base register in first field
B Base register in second field
v Vector register in first field
V Vector register in first field
A Optional address register (base register)
X Optional index register
I Immediate data (16bits signed)
O Offset field (16bits signed)
h Offset field (15bits signed)
d Offset field (14bits signed)
S Shift count field
any other characters are printed as is...
*/
/* The assembler requires that this array be sorted as follows:
all instances of the same mnemonic must be consecutive.
All instances of the same mnemonic with the same number of operands
must be consecutive.
*/
struct gld_opcode gld_opcodes[] =
{
{ "abm", 0xa0080000, 0xfc080000, "f,xOA,X", 4 },
{ "abr", 0x18080000, 0xfc0c0000, "r,f", 2 },
{ "aci", 0xfc770000, 0xfc7f8000, "r,I", 4 },
{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 },
{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 },
{ "adi", 0xc8010000, 0xfc7f0000, "r,I", 4 },
{ "admb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 },
{ "admd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 },
{ "admh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 },
{ "admw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 },
{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 },
{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 },
{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 },
{ "adrm", 0x38080000, 0xfc0f0000, "r,R", 2 },
{ "ai", 0xfc030000, 0xfc07ffff, "I", 4 },
{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 },
{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 },
{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 },
{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 },
{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 },
{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 },
{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 },
{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 },
{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 },
{ "bcf", 0xf0000000, 0xfc080000, "I,xOA,X", 4 },
{ "bct", 0xec000000, 0xfc080000, "I,xOA,X", 4 },
{ "bei", 0x00060000, 0xffff0000, "", 2 },
{ "bft", 0xf0000000, 0xff880000, "xOA,X", 4 },
{ "bib", 0xf4000000, 0xfc780000, "r,xOA", 4 },
{ "bid", 0xf4600000, 0xfc780000, "r,xOA", 4 },
{ "bih", 0xf4200000, 0xfc780000, "r,xOA", 4 },
{ "biw", 0xf4400000, 0xfc780000, "r,xOA", 4 },
{ "bl", 0xf8800000, 0xff880000, "xOA,X", 4 },
{ "bsub", 0x5c080000, 0xff8f0000, "", 2 },
{ "bsubm", 0x28080000, 0xfc080000, "", 4 },
{ "bu", 0xec000000, 0xff880000, "xOA,X", 4 },
{ "call", 0x28080000, 0xfc0f0000, "", 2 },
{ "callm", 0x5c080000, 0xff880000, "", 4 },
{ "camb", 0x90080000, 0xfc080000, "r,xOA,X", 4 },
{ "camd", 0x90000002, 0xfc080002, "r,xOA,X", 4 },
{ "camh", 0x90000001, 0xfc080001, "r,xOA,X", 4 },
{ "camw", 0x90000000, 0xfc080000, "r.xOA,X", 4 },
{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 },
{ "cd", 0xfc060000, 0xfc070000, "r,f", 4 },
{ "cea", 0x000f0000, 0xffff0000, "", 2 },
{ "ci", 0xc8050000, 0xfc7f0000, "r,I", 4 },
{ "cmc", 0x040a0000, 0xfc7f0000, "r", 2 },
{ "cmmb", 0x94080000, 0xfc080000, "r,xOA,X", 4 },
{ "cmmd", 0x94000002, 0xfc080002, "r,xOA,X", 4 },
{ "cmmh", 0x94000001, 0xfc080001, "r,xOA,X", 4 },
{ "cmmw", 0x94000000, 0xfc080000, "r,xOA,X", 4 },
{ "cmr", 0x14000000, 0xfc0f0000, "r,R", 2 },
{ "daci", 0xfc7f0000, 0xfc7f8000, "r,I", 4 },
{ "dae", 0x000e0000, 0xffff0000, "", 2 },
{ "dai", 0xfc040000, 0xfc07ffff, "I", 4 },
{ "dci", 0xfc6f0000, 0xfc7f8000, "r,I", 4 },
{ "di", 0xfc010000, 0xfc07ffff, "I", 4 },
{ "dvfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 },
{ "dvfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 },
{ "dvi", 0xc8040000, 0xfc7f0000, "r,I", 4 },
{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 },
{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 },
{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 },
{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 },
{ "dvrfd", 0x380c0000, 0xfc0f0000, "r,R", 4 },
{ "dvrfw", 0x38040000, 0xfc0f0000, "r,xOA,X", 4 },
{ "eae", 0x00080000, 0xffff0000, "", 2 },
{ "eci", 0xfc670000, 0xfc7f8080, "r,I", 4 },
{ "ecwcs", 0xfc4f0000, 0xfc7f8000, "", 4 },
{ "ei", 0xfc000000, 0xfc07ffff, "I", 4 },
{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 },
{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 },
{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 },
{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 },
{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 },
{ "eorm", 0x0c080000, 0xfc0f0000, "r,R", 2 },
{ "es", 0x00040000, 0xfc7f0000, "r", 2 },
{ "exm", 0xa8000000, 0xff880000, "xOA,X", 4 },
{ "exr", 0xc8070000, 0xfc7f0000, "r", 2 },
{ "exrr", 0xc8070002, 0xfc7f0002, "r", 2 },
{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 },
{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 },
{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 },
{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 },
{ "grio", 0xfc3f0000, 0xfc7f8000, "r,I", 4 },
{ "halt", 0x00000000, 0xffff0000, "", 2 },
{ "hio", 0xfc370000, 0xfc7f8000, "r,I", 4 },
{ "jwcs", 0xfa080000, 0xff880000, "xOA,X", 4 },
{ "la", 0x50000000, 0xfc000000, "r,xOA,X", 4 },
{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 },
{ "lb", 0xac080000, 0xfc080000, "r,xOA,X", 4 },
{ "lcs", 0x00030000, 0xfc7f0000, "r", 2 },
{ "ld", 0xac000002, 0xfc080002, "r,xOA,X", 4 },
{ "lear", 0x80000000, 0xfc080000, "r,xOA,X", 4 },
{ "lf", 0xcc000000, 0xfc080000, "r,xOA,X", 4 },
{ "lfbr", 0xcc080000, 0xfc080000, "b,xOA,X", 4 },
{ "lh", 0xac000001, 0xfc080001, "r,xOA,X", 4 },
{ "li", 0xc8000000, 0xfc7f0000, "r,I", 4 },
{ "lmap", 0x2c070000, 0xfc7f0000, "r", 2 },
{ "lmb", 0xb0080000, 0xfc080000, "r,xOA,X", 4 },
{ "lmd", 0xb0000002, 0xfc080002, "r,xOA,X", 4 },
{ "lmh", 0xb0000001, 0xfc080001, "r,xOA,X", 4 },
{ "lmw", 0xb0000000, 0xfc080000, "r,xOA,X", 4 },
{ "lnb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 },
{ "lnd", 0xb4000002, 0xfc080002, "r,xOA,X", 4 },
{ "lnh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 },
{ "lnw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 },
{ "lpsd", 0xf9800000, 0xff880000, "r,xOA,X", 4 },
{ "lpsdcm", 0xfa800000, 0xff880000, "r,xOA,X", 4 },
{ "lw", 0xac000000, 0xfc080000, "r,xOA,X", 4 },
{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 },
{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 },
{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 },
{ "mpi", 0xc8030000, 0xfc7f0000, "r,I", 4 },
{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 },
{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 },
{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 },
{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 },
{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 },
{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 },
{ "nop", 0x00020000, 0xffff0000, "", 2 },
{ "ormb", 0x88080000, 0xfc080000, "r,xOA,X", 4 },
{ "ormd", 0x88000002, 0xfc080002, "r,xOA,X", 4 },
{ "ormh", 0x88000001, 0xfc080001, "r,xOA,X", 4 },
{ "ormw", 0x88000000, 0xfc080000, "r,xOA,X", 4 },
{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 },
{ "orrm", 0x08080000, 0xfc0f0000, "r,R", 2 },
{ "rdsts", 0x00090000, 0xfc7f0000, "r", 2 },
{ "return", 0x280e0000, 0xfc7f0000, "", 2 },
{ "ri", 0xfc020000, 0xfc07ffff, "I", 4 },
{ "rnd", 0x00050000, 0xfc7f0000, "r", 2 },
{ "rpswt", 0x040b0000, 0xfc7f0000, "r", 2 },
{ "rschnl", 0xfc2f0000, 0xfc7f8000, "r,I", 4 },
{ "rsctl", 0xfc470000, 0xfc7f8000, "r,I", 4 },
{ "rwcs", 0x000b0000, 0xfc0f0000, "r,R", 2 },
{ "sacz", 0x10080000, 0xfc0f0000, "r,R", 2 },
{ "sbm", 0x98080000, 0xfc080000, "f,xOA,X", 4 },
{ "sbr", 0x18000000, 0xfc0c0000, "r,f", 4 },
{ "sea", 0x000d0000, 0xffff0000, "", 2 },
{ "setcpu", 0x2c090000, 0xfc7f0000, "r", 2 },
{ "sio", 0xfc170000, 0xfc7f8000, "r,I", 4 },
{ "sipu", 0x000a0000, 0xffff0000, "", 2 },
{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 },
{ "slad", 0x20400000, 0xfc600000, "r,S", 2 },
{ "slc", 0x24400000, 0xfc600000, "r,S", 2 },
{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 },
{ "slld", 0x20600000, 0xfc600000, "r,S", 2 },
{ "smc", 0x04070000, 0xfc070000, "", 2 },
{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 },
{ "srad", 0x20000000, 0xfc600000, "r,S", 2 },
{ "src", 0x24000000, 0xfc600000, "r,S", 2 },
{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 },
{ "srld", 0x20200000, 0xfc600000, "r,S", 2 },
{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 },
{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 },
{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 },
{ "stfbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 },
{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 },
{ "stmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 },
{ "stmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 },
{ "stmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 },
{ "stmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 },
{ "stpio", 0xfc270000, 0xfc7f8000, "r,I", 4 },
{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 },
{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 },
{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 },
{ "sufd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 },
{ "sufw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 },
{ "sui", 0xc8020000, 0xfc7f0000, "r,I", 4 },
{ "sumb", 0xbc080000, 0xfc080000, "r,xOA,X", 4 },
{ "sumd", 0xbc000002, 0xfc080002, "r,xOA,X", 4 },
{ "sumh", 0xbc000001, 0xfc080001, "r,xOA,X", 4 },
{ "sumw", 0xbc000000, 0xfc080000, "r,xOA,X", 4 },
{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 },
{ "surfd", 0x380b0000, 0xfc0f0000, "r,xOA,X", 4 },
{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 },
{ "surm", 0x3c080000, 0xfc0f0000, "r,R", 2 },
{ "svc", 0xc8060000, 0xffff0000, "", 4 },
{ "tbm", 0xa4080000, 0xfc080000, "f,xOA,X", 4 },
{ "tbr", 0x180c0000, 0xfc0c0000, "r,f", 2 },
{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 },
{ "tccr", 0x28040000, 0xfc7f0000, "", 2 },
{ "td", 0xfc050000, 0xfc070000, "r,f", 4 },
{ "tio", 0xfc1f0000, 0xfc7f8000, "r,I", 4 },
{ "tmapr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 },
{ "tpcbr", 0x280c0000, 0xfc7f0000, "r", 2 },
{ "trbr", 0x2c010000, 0xfc0f0000, "b,R", 2 },
{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 },
{ "trcc", 0x28050000, 0xfc7f0000, "", 2 },
{ "trcm", 0x2c0b0000, 0xfc0f0000, "r,R", 2 },
{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 },
{ "trnm", 0x2c0c0000, 0xfc0f0000, "r,R", 2 },
{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 },
{ "trrm", 0x2c080000, 0xfc0f0000, "r,R", 2 },
{ "trsc", 0x2c0e0000, 0xfc0f0000, "r,R", 2 },
{ "trsw", 0x28000000, 0xfc7f0000, "r", 2 },
{ "tscr", 0x2c0f0000, 0xfc0f0000, "r,R", 2 },
{ "uei", 0x00070000, 0xffff0000, "", 2 },
{ "wait", 0x00010000, 0xffff0000, "", 2 },
{ "wcwcs", 0xfc5f0000, 0xfc7f8000, "", 4 },
{ "wwcs", 0x000c0000, 0xfc0f0000, "r,R", 2 },
{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 },
{ "xcr", 0x2c050000, 0xfc0f0000, "r,R", 2 },
{ "xcrm", 0x2c0d0000, 0xfc0f0000, "r,R", 2 },
{ "zbm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 },
{ "zbr", 0x18040000, 0xfc0c0000, "r,f", 2 },
{ "zmb", 0xf8080000, 0xfc080000, "r,xOA,X", 4 },
{ "zmd", 0xf8000002, 0xfc080002, "r,xOA,X", 4 },
{ "zmh", 0xf8000001, 0xfc080001, "r,xOA,X", 4 },
{ "zmw", 0xf8000000, 0xfc080000, "r,xOA,X", 4 },
{ "zr", 0x0c000000, 0xfc0f0000, "r", 2 },
};
int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]);
struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) /
sizeof(gld_opcodes[0]);

287
include/pyr-opcode.h Executable file
View File

@ -0,0 +1,287 @@
/* pyramid.opcode.h -- gdb initial attempt. */
/* pyramid opcode table: wot to do with this
particular opcode */
struct pyr_datum
{
char nargs;
char * args; /* how to compile said opcode */
unsigned long mask; /* Bit vector: which operand modes are valid
for this opcode */
unsigned char code; /* op-code (always 6(?) bits */
};
typedef struct pyr_insn_format {
unsigned int mode :4;
unsigned int operator :8;
unsigned int index_scale :2;
unsigned int index_reg :6;
unsigned int operand_1 :6;
unsigned int operand_2:6;
} pyr_insn_format;
/* We store four bytes of opcode for all opcodes.
Pyramid is sufficiently RISCy that:
- insns are always an integral number of words;
- the length of any insn can be told from the first word of
the insn. (ie, if there are zero, one, or two words of
immediate operand/offset).
The args component is a string containing two characters for each
operand of the instruction. The first specifies the kind of operand;
the second, the place it is stored. */
/* Kinds of operands:
mask assembler syntax description
0x0001: movw Rn,Rn register to register
0x0002: movw K,Rn quick immediate to register
0x0004: movw I,Rn long immediate to register
0x0008: movw (Rn),Rn register indirect to register
movw (Rn)[x],Rn register indirect to register
0x0010: movw I(Rn),Rn offset register indirect to register
movw I(Rn)[x],Rn offset register indirect, indexed, to register
0x0020: movw Rn,(Rn) register to register indirect
0x0040: movw K,(Rn) quick immediate to register indirect
0x0080: movw I,(Rn) long immediate to register indirect
0x0100: movw (Rn),(Rn) register indirect to-register indirect
0x0100: movw (Rn),(Rn) register indirect to-register indirect
0x0200: movw I(Rn),(Rn) register indirect+offset to register indirect
0x0200: movw I(Rn),(Rn) register indirect+offset to register indirect
0x0400: movw Rn,I(Rn) register to register indirect+offset
0x0800: movw K,I(Rn) quick immediate to register indirect+offset
0x1000: movw I,I(Rn) long immediate to register indirect+offset
0x1000: movw (Rn),I(Rn) register indirect to-register indirect+offset
0x1000: movw I(Rn),I(Rn) register indirect+offset to register indirect
+offset
0x0000: (irregular) ???
Each insn has a four-bit field encoding the type(s) of its operands.
*/
/* Some common combinations
*/
/* the first 5,(0x1|0x2|0x4|0x8|0x10) ie (1|2|4|8|16), ie ( 32 -1)*/
#define GEN_TO_REG (31)
#define UNKNOWN ((unsigned long)-1)
#define ANY (GEN_TO_REG | (GEN_TO_REG << 5) | (GEN_TO_REG << 15))
#define CONVERT (1|8|0x10|0x20|0x200)
#define K_TO_REG (2)
#define I_TO_REG (4)
#define NOTK_TO_REG (GEN_TO_REG & ~K_TO_REG)
#define NOTI_TO_REG (GEN_TO_REG & ~I_TO_REG)
/* The assembler requires that this array be sorted as follows:
all instances of the same mnemonic must be consecutive.
All instances of the same mnemonic with the same number of operands
must be consecutive.
*/
struct pyr_opcode /* pyr opcode text */
{
char * name; /* opcode name: lowercase string [key] */
struct pyr_datum datum; /* rest of opcode table [datum] */
};
#define pyr_how args
#define pyr_nargs nargs
#define pyr_mask mask
#define pyr_name name
struct pyr_opcode pyr_opcodes[] =
{
{"movb", { 2, "", UNKNOWN, 0x11}, },
{"movh", { 2, "", UNKNOWN, 0x12} },
{"movw", { 2, "", ANY, 0x10} },
{"movl", { 2, "", ANY, 0x13} },
{"mnegw", { 2, "", (0x1|0x8|0x10), 0x14} },
{"mnegf", { 2, "", 0x1, 0x15} },
{"mnegd", { 2, "", 0x1, 0x16} },
{"mcomw", { 2, "", (0x1|0x8|0x10), 0x17} },
{"mabsw", { 2, "", (0x1|0x8|0x10), 0x18} },
{"mabsf", { 2, "", 0x1, 0x19} },
{"mabsd", { 2, "", 0x1, 0x1a} },
{"mtstw", { 2, "", (0x1|0x8|0x10), 0x1c} },
{"mtstf", { 2, "", 0x1, 0x1d} },
{"mtstd", { 2, "", 0x1, 0x1e} },
{"mova", { 2, "", 0x8|0x10, 0x1f} },
{"movzbw", { 2, "", (0x1|0x8|0x10), 0x20} },
{"movzhw", { 2, "", (0x1|0x8|0x10), 0x21} },
/* 2 insns out of order here */
{"movbl", { 2, "", 1, 0x4f} },
{"filbl", { 2, "", 1, 0x4e} },
{"cvtbw", { 2, "", CONVERT, 0x22} },
{"cvthw", { 2, "", CONVERT, 0x23} },
{"cvtwb", { 2, "", CONVERT, 0x24} },
{"cvtwh", { 2, "", CONVERT, 0x25} },
{"cvtwf", { 2, "", CONVERT, 0x26} },
{"cvtwd", { 2, "", CONVERT, 0x27} },
{"cvtfw", { 2, "", CONVERT, 0x28} },
{"cvtfd", { 2, "", CONVERT, 0x29} },
{"cvtdw", { 2, "", CONVERT, 0x2a} },
{"cvtdf", { 2, "", CONVERT, 0x2b} },
{"addw", { 2, "", GEN_TO_REG, 0x40} },
{"addwc", { 2, "", GEN_TO_REG, 0x41} },
{"subw", { 2, "", GEN_TO_REG, 0x42} },
{"subwb", { 2, "", GEN_TO_REG, 0x43} },
{"rsubw", { 2, "", GEN_TO_REG, 0x44} },
{"mulw", { 2, "", GEN_TO_REG, 0x45} },
{"emul", { 2, "", GEN_TO_REG, 0x47} },
{"umulw", { 2, "", GEN_TO_REG, 0x46} },
{"divw", { 2, "", GEN_TO_REG, 0x48} },
{"ediv", { 2, "", GEN_TO_REG, 0x4a} },
{"rdivw", { 2, "", GEN_TO_REG, 0x4b} },
{"udivw", { 2, "", GEN_TO_REG, 0x49} },
{"modw", { 2, "", GEN_TO_REG, 0x4c} },
{"umodw", { 2, "", GEN_TO_REG, 0x4d} },
{"addf", { 2, "", 1, 0x50} },
{"addd", { 2, "", 1, 0x51} },
{"subf", { 2, "", 1, 0x52} },
{"subd", { 2, "", 1, 0x53} },
{"mulf", { 2, "", 1, 0x56} },
{"muld", { 2, "", 1, 0x57} },
{"divf", { 2, "", 1, 0x58} },
{"divd", { 2, "", 1, 0x59} },
{"cmpb", { 2, "", UNKNOWN, 0x61} },
{"cmph", { 2, "", UNKNOWN, 0x62} },
{"cmpw", { 2, "", UNKNOWN, 0x60} },
{"ucmpb", { 2, "", UNKNOWN, 0x66} },
/* WHY no "ucmph"??? */
{"ucmpw", { 2, "", UNKNOWN, 0x65} },
{"xchw", { 2, "", UNKNOWN, 0x0f} },
{"andw", { 2, "", GEN_TO_REG, 0x30} },
{"orw", { 2, "", GEN_TO_REG, 0x31} },
{"xorw", { 2, "", GEN_TO_REG, 0x32} },
{"bicw", { 2, "", GEN_TO_REG, 0x33} },
{"lshlw", { 2, "", GEN_TO_REG, 0x38} },
{"ashlw", { 2, "", GEN_TO_REG, 0x3a} },
{"ashll", { 2, "", GEN_TO_REG, 0x3c} },
{"ashrw", { 2, "", GEN_TO_REG, 0x3b} },
{"ashrl", { 2, "", GEN_TO_REG, 0x3d} },
{"rotlw", { 2, "", GEN_TO_REG, 0x3e} },
{"rotrw", { 2, "", GEN_TO_REG, 0x3f} },
/* push and pop insns are "going away next release". */
{"pushw", { 2, "", GEN_TO_REG, 0x0c} },
{"popw", { 2, "", (0x1|0x8|0x10), 0x0d} },
{"pusha", { 2, "", (0x8|0x10), 0x0e} },
{"bitsw", { 2, "", UNKNOWN, 0x35} },
{"bitcw", { 2, "", UNKNOWN, 0x36} },
/* some kind of ibra/dbra insns??*/
{"icmpw", { 2, "", UNKNOWN, 0x67} },
{"dcmpw", { 2, "", (1|4|0x20|0x80|0x400|0x1000), 0x69} },/*FIXME*/
{"acmpw", { 2, "", 1, 0x6b} },
/* Call is written as a 1-op insn, but is always (dis)assembled as a 2-op
insn with a 2nd op of tr14. The assembler will have to grok this. */
{"call", { 2, "", GEN_TO_REG, 0x04} },
{"call", { 1, "", GEN_TO_REG, 0x04} },
{"callk", { 1, "", UNKNOWN, 0x06} },/* system call?*/
/* Ret is usually written as a 0-op insn, but gets disassembled as a
1-op insn. The operand is always tr15. */
{"ret", { 0, "", UNKNOWN, 0x09} },
{"ret", { 1, "", UNKNOWN, 0x09} },
{"adsf", { 2, "", (1|2|4), 0x08} },
{"retd", { 2, "", UNKNOWN, 0x0a} },
{"btc", { 2, "", UNKNOWN, 0x01} },
{"bfc", { 2, "", UNKNOWN, 0x02} },
/* Careful: halt is 0x00000000. Jump must have some other (mode?)bit set?? */
{"jump", { 1, "", UNKNOWN, 0x00} },
{"btp", { 2, "", UNKNOWN, 0xf00} },
/* read control-stack pointer is another 1-or-2 operand insn. */
{"rcsp", { 2, "", UNKNOWN, 0x01f} },
{"rcsp", { 1, "", UNKNOWN, 0x01f} }
};
/* end: pyramid.opcode.h */
/* One day I will have to take the time to find out what operands
are valid for these insns, and guess at what they mean.
I can't imagine what the "I???" insns (iglob, etc) do.
the arithmetic-sounding insns ending in "p" sound awfully like BCD
arithmetic insns:
dshlp -> Decimal SHift Left Packed
dshrp -> Decimal SHift Right Packed
and cvtlp would be convert long to packed.
I have no idea how the operands are interpreted; but having them be
a long register with (address, length) of an in-memory packed BCD operand
would not be surprising.
They are unlikely to be a packed bcd string: 64 bits of long give
is only 15 digits+sign, which isn't enough for COBOL.
*/
#if 0
{"wcsp", { 2, "", UNKNOWN, 0x00} }, /*write csp?*/
/* The OSx Operating System Porting Guide claims SSL does things
with tr12 (a register reserved to it) to do with static block-structure
references. SSL=Set Static Link? It's "Going away next release". */
{"ssl", { 2, "", UNKNOWN, 0x00} },
{"ccmps", { 2, "", UNKNOWN, 0x00} },
{"lcd", { 2, "", UNKNOWN, 0x00} },
{"uemul", { 2, "", UNKNOWN, 0x00} }, /*unsigned emul*/
{"srf", { 2, "", UNKNOWN, 0x00} }, /*Gidget time???*/
{"mnegp", { 2, "", UNKNOWN, 0x00} }, /move-neg phys?*/
{"ldp", { 2, "", UNKNOWN, 0x00} }, /*load phys?*/
{"ldti", { 2, "", UNKNOWN, 0x00} },
{"ldb", { 2, "", UNKNOWN, 0x00} },
{"stp", { 2, "", UNKNOWN, 0x00} },
{"stti", { 2, "", UNKNOWN, 0x00} },
{"stb", { 2, "", UNKNOWN, 0x00} },
{"stu", { 2, "", UNKNOWN, 0x00} },
{"addp", { 2, "", UNKNOWN, 0x00} },
{"subp", { 2, "", UNKNOWN, 0x00} },
{"mulp", { 2, "", UNKNOWN, 0x00} },
{"divp", { 2, "", UNKNOWN, 0x00} },
{"dshlp", { 2, "", UNKNOWN, 0x00} }, /* dec shl packed? */
{"dshrp", { 2, "", UNKNOWN, 0x00} }, /* dec shr packed? */
{"movs", { 2, "", UNKNOWN, 0x00} }, /*move (string?)?*/
{"cmpp", { 2, "", UNKNOWN, 0x00} }, /* cmp phys?*/
{"cmps", { 2, "", UNKNOWN, 0x00} }, /* cmp (string?)?*/
{"cvtlp", { 2, "", UNKNOWN, 0x00} }, /* cvt long to p??*/
{"cvtpl", { 2, "", UNKNOWN, 0x00} }, /* cvt p to l??*/
{"dintr", { 2, "", UNKNOWN, 0x00} }, /* ?? intr ?*/
{"rphysw", { 2, "", UNKNOWN, 0x00} }, /* read phys word?*/
{"wphysw", { 2, "", UNKNOWN, 0x00} }, /* write phys word?*/
{"cmovs", { 2, "", UNKNOWN, 0x00} },
{"rsubw", { 2, "", UNKNOWN, 0x00} },
{"bicpsw", { 2, "", UNKNOWN, 0x00} }, /* clr bit in psw? */
{"bispsw", { 2, "", UNKNOWN, 0x00} }, /* set bit in psw? */
{"eio", { 2, "", UNKNOWN, 0x00} }, /* ?? ?io ? */
{"callp", { 2, "", UNKNOWN, 0x00} }, /* call phys?*/
{"callr", { 2, "", UNKNOWN, 0x00} },
{"lpcxt", { 2, "", UNKNOWN, 0x00} }, /*load proc context*/
{"rei", { 2, "", UNKNOWN, 0x00} }, /*ret from intrpt*/
{"rport", { 2, "", UNKNOWN, 0x00} }, /*read-port?*/
{"rtod", { 2, "", UNKNOWN, 0x00} }, /*read-time-of-day?*/
{"ssi", { 2, "", UNKNOWN, 0x00} },
{"vtpa", { 2, "", UNKNOWN, 0x00} }, /*virt-to-phys-addr?*/
{"wicl", { 2, "", UNKNOWN, 0x00} }, /* write icl ? */
{"wport", { 2, "", UNKNOWN, 0x00} }, /*write-port?*/
{"wtod", { 2, "", UNKNOWN, 0x00} }, /*write-time-of-day?*/
{"flic", { 2, "", UNKNOWN, 0x00} },
{"iglob", { 2, "", UNKNOWN, 0x00} }, /* I global? */
{"iphys", { 2, "", UNKNOWN, 0x00} }, /* I physical? */
{"ipid", { 2, "", UNKNOWN, 0x00} }, /* I pid? */
{"ivect", { 2, "", UNKNOWN, 0x00} }, /* I vector? */
{"lamst", { 2, "", UNKNOWN, 0x00} },
{"tio", { 2, "", UNKNOWN, 0x00} },
#endif

750
include/sparc-opcode.h Executable file
View File

@ -0,0 +1,750 @@
/* Table of opcodes for the sparc.
Copyright (C) 1989 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
GAS/GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 1, or (at your option)
any later version.
GAS/GDB is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS or GDB; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
/*
$Id$
$Log$
Revision 1.1 1991/05/19 00:19:52 rich
Initial revision
* Revision 1.1.1.1 1991/03/21 21:26:54 gumby
* Back from Intel with Steve
*
* Revision 1.1 1991/03/21 21:26:53 gumby
* Initial revision
*
* Revision 1.1 1991/03/13 00:34:24 chrisb
* Initial revision
*
* Revision 1.2 1991/03/08 21:54:49 rich
* Modified Files:
* Makefile ar.c binutils.h bucomm.c copy.c cplus-dem.c getopt.c
* i960-pinsn.c m68k-pinsn.c nm.c objdump.c sparc-opcode.h
* sparc-pinsn.c strip.c
*
* Verifying Portland tree with steve's last changes. Also, some partial
* porting.
*
* Revision 1.1 1991/02/22 16:48:08 sac
* Initial revision
*
*/
#if !defined(__STDC__) && !defined(const)
#define const
#endif
/*
* Structure of an opcode table entry.
*/
struct sparc_opcode
{
const char *name;
unsigned long int match; /* Bits that must be set. */
unsigned long int lose; /* Bits that must not be set. */
const char *args;
/* Nonzero if this is a delayed branch instruction. */
/* This was called "flags" in the gdb version. */
char delayed;
};
/*
All sparc opcodes are 32 bits, except for the `set' instruction (really
a macro), which is 64 bits. It is handled as a special case.
The match component is a mask saying which bits must match a
particular opcode in order for an instruction to be an instance
of that opcode.
The args component is a string containing one character
for each operand of the instruction.
Kinds of operands:
# Number used by optimizer. It is ignored.
1 rs1 register.
2 rs2 register.
d rd register.
e frs1 floating point register.
f frs2 floating point register.
g frsd floating point register.
b crs1 coprocessor register
c crs2 coprocessor register
D crsd coprocessor register
h 22 high bits.
i 13 bit Immediate.
l 22 bit PC relative immediate.
L 30 bit PC relative immediate.
a Annul. The annul bit is set.
A Alternate address space. Stored as 8 bits.
C Coprocessor state register.
F floating point state register.
p Processor state register.
q Floating point queue.
r Single register that is both rs1 and rsd.
Q Coprocessor queue.
S Special case.
t Trap base register.
w Window invalid mask register.
y Y register.
*/
/* The order of the opcodes in this table is significant:
* The assembler requires that all instances of the same mnemonic must be
consecutive. If they aren't, the assembler will bomb at runtime.
* The disassembler should not care about the order of the opcodes. */
static struct sparc_opcode sparc_opcodes[] =
{
{ "ldd", 0xc1980000, 0x0060201f, "[1],D", 0 }, /* ldd [rs1+%g0],d */
{ "ldd", 0xc1982000, 0x00601fff, "[1],D", 0 }, /* ldd [rs1+0],d */
{ "ldd", 0xc1982000, 0x00600000, "[1+i],D", 0 },
{ "ldd", 0xc1982000, 0x00600000, "[i+1],D", 0 },
{ "ldd", 0xc1980000, 0x00602000, "[1+2],D", 0 },
{ "ldd", 0xc1180000, 0x00e0201f, "[1],g", 0 }, /* ldd [rs1+%g0],d */
{ "ldd", 0xc1182000, 0x00e01fff, "[1],g", 0 }, /* ldd [rs1+0],d */
{ "ldd", 0xc1182000, 0x00e00000, "[1+i],g", 0 },
{ "ldd", 0xc1182000, 0x00e00000, "[i+1],g", 0 },
{ "ldd", 0xc1180000, 0x00e02000, "[1+2],g", 0 },
{ "ldd", 0xc0180000, 0x01e0201f, "[1],d", 0 }, /* ldd [rs1+%g0],d */
{ "ldd", 0xc0182000, 0x01e01fff, "[1],d", 0 }, /* ldd [rs1+0],d */
{ "ldd", 0xc0182000, 0x01e00000, "[1+i],d", 0 },
{ "ldd", 0xc0182000, 0x01e00000, "[i+1],d", 0 },
{ "ldd", 0xc0180000, 0x01e02000, "[1+2],d", 0 },
{ "ld", 0xc1880000, 0x0070201f, "[1],C", 0 }, /* ld [rs1+%g0],d */
{ "ld", 0xc1882000, 0x00701fff, "[1],C", 0 }, /* ld [rs1+0],d */
{ "ld", 0xc1882000, 0x00700000, "[1+i],C", 0 },
{ "ld", 0xc1882000, 0x00700000, "[i+1],C", 0 },
{ "ld", 0xc1880000, 0x00702000, "[1+2],C", 0 },
{ "ld", 0xc1800000, 0x0078201f, "[1],D", 0 }, /* ld [rs1+%g0],d */
{ "ld", 0xc1802000, 0x00781fff, "[1],D", 0 }, /* ld [rs1+0],d */
{ "ld", 0xc1802000, 0x00780000, "[1+i],D", 0 },
{ "ld", 0xc1802000, 0x00780000, "[i+1],D", 0 },
{ "ld", 0xc1800000, 0x00782000, "[1+2],D", 0 },
{ "ld", 0xc1080000, 0x00f0201f, "[1],F", 0 }, /* ld [rs1+%g0],d */
{ "ld", 0xc1082000, 0x00f01fff, "[1],F", 0 }, /* ld [rs1+0],d */
{ "ld", 0xc1082000, 0x00f00000, "[1+i],F", 0 },
{ "ld", 0xc1082000, 0x00f00000, "[i+1],F", 0 },
{ "ld", 0xc1080000, 0x00f02000, "[1+2],F", 0 },
{ "ld", 0xc1000000, 0x00f8201f, "[1],g", 0 }, /* ld [rs1+%g0],d */
{ "ld", 0xc1002000, 0x00f81fff, "[1],g", 0 }, /* ld [rs1+0],d */
{ "ld", 0xc1002000, 0x00f80000, "[1+i],g", 0 },
{ "ld", 0xc1002000, 0x00f80000, "[i+1],g", 0 },
{ "ld", 0xc1000000, 0x00f82000, "[1+2],g", 0 },
{ "ld", 0xc0000000, 0x01f8201f, "[1],d", 0 }, /* ld [rs1+%g0],d */
{ "ld", 0xc0002000, 0x01f81fff, "[1],d", 0 }, /* ld [rs1+0],d */
{ "ld", 0xc0002000, 0x01f80000, "[1+i],d", 0 },
{ "ld", 0xc0002000, 0x01f80000, "[i+1],d", 0 },
{ "ld", 0xc0000000, 0x01f82000, "[1+2],d", 0 },
{ "ldstuba", 0xc0d80000, 0x0100201f, "[1]A,d", 0 }, /* ldstuba [rs1+%g0],d */
{ "ldstuba", 0xc0d80000, 0x01002000, "[1+2]A,d", 0 },
{ "ldsha", 0xc0d00000, 0x0128201f, "[1]A,d", 0 }, /* ldsha [rs1+%g0],d */
{ "ldsha", 0xc0d00000, 0x01282000, "[1+2]A,d", 0 },
{ "ldsba", 0xc0c80000, 0x0130201f, "[1]A,d", 0 }, /* ldsba [rs1+%g0],d */
{ "ldsba", 0xc0c80000, 0x01302000, "[1+2]A,d", 0 },
{ "ldda", 0xc0980000, 0x0160201f, "[1]A,d", 0 }, /* ldda [rs1+%g0],d */
{ "ldda", 0xc0980000, 0x01602000, "[1+2]A,d", 0 },
{ "lduha", 0xc0900000, 0x0168201f, "[1]A,d", 0 }, /* lduha [rs1+%g0],d */
{ "lduha", 0xc0900000, 0x01682000, "[1+2]A,d", 0 },
{ "ldstub", 0xc0680000, 0x0190201f, "[1],d", 0 }, /* ldstub [rs1+%g0],d */
{ "ldstub", 0xc0682000, 0x01900000, "[1+i],d", 0 },
{ "ldstub", 0xc0682000, 0x01900000, "[i+1],d", 0 },
{ "ldstub", 0xc0680000, 0x01902000, "[1+2],d", 0 },
{ "lda", 0xc0800000, 0x0178201f, "[1]A,d", 0 }, /* lda [rs1+%g0],d */
{ "lda", 0xc0800000, 0x01782000, "[1+2]A,d", 0 },
{ "ldsh", 0xc0500000, 0x0000000d, "[1],d", 0 }, /* ldsh [rs1+%g0],d */
{ "ldsh", 0xc0502000, 0x01a81fff, "[1],d", 0 }, /* ldsh [rs1+0],d */
{ "ldsh", 0xc0502000, 0x01a80000, "[1+i],d", 0 },
{ "ldsh", 0xc0502000, 0x01a80000, "[i+1],d", 0 },
{ "ldsh", 0xc0500000, 0x01a82000, "[1+2],d", 0 },
{ "ldsb", 0xc0480000, 0x01b0201f, "[1],d", 0 }, /* ldsb [rs1+%g0],d */
{ "ldsb", 0xc0482000, 0x01b01fff, "[1],d", 0 }, /* ldsb [rs1+0],d */
{ "ldsb", 0xc0482000, 0x01b00000, "[1+i],d", 0 },
{ "ldsb", 0xc0482000, 0x01b00000, "[i+1],d", 0 },
{ "ldsb", 0xc0480000, 0x01b02000, "[1+2],d", 0 },
{ "ldub", 0xc0080000, 0x01f0201f, "[1],d", 0 }, /* ldub [rs1+%g0],d */
{ "ldub", 0xc0082000, 0x01f01fff, "[1],d", 0 }, /* ldub [rs1+0],d */
{ "ldub", 0xc0082000, 0x01f00000, "[1+i],d", 0 },
{ "ldub", 0xc0082000, 0x01f00000, "[i+1],d", 0 },
{ "ldub", 0xc0080000, 0x01f02000, "[1+2],d", 0 },
{ "lduba", 0xc0880000, 0x0170201f, "[1]A,d", 0 }, /* lduba [rs1+%g0],d */
{ "lduba", 0xc0880000, 0x01702000, "[1+2]A,d", 0 },
{ "lduh", 0xc0102000, 0x01e80000, "[1+i],d", 0 },
{ "lduh", 0xc0102000, 0x01e80000, "[i+1],d", 0 },
{ "lduh", 0xc0100000, 0x01e8201f, "[1],d", 0 }, /* lduh [rs1+%g0],d */
{ "lduh", 0xc0102000, 0x01e81fff, "[1],d", 0 }, /* lduh [rs1+0],d */
{ "lduh", 0xc0100000, 0x01e82000, "[1+2],d", 0 },
{ "st", 0xc0200000, 0x01d8201f, "d,[1]", 0 }, /* st d,[rs1+%g0] */
{ "st", 0xc0202000, 0x01d81fff, "d,[1]", 0 }, /* st d,[rs1+0] */
{ "st", 0xc0202000, 0x01d80000, "d,[1+i]", 0 },
{ "st", 0xc0202000, 0x01d80000, "d,[i+1]", 0 },
{ "st", 0xc0200000, 0x01d82000, "d,[1+2]", 0 },
{ "st", 0xc1200000, 0x00d8201f, "g,[1]", 0 }, /* st d[rs1+%g0] */
{ "st", 0xc1202000, 0x00d81fff, "g,[1]", 0 }, /* st d,[rs1+0] */
{ "st", 0xc1202000, 0x00d80000, "g,[1+i]", 0 },
{ "st", 0xc1202000, 0x00d80000, "g,[i+1]", 0 },
{ "st", 0xc1200000, 0x00d82000, "g,[1+2]", 0 },
{ "st", 0xc1280000, 0x00c0d01f, "F,[1]", 0 }, /* st d,[rs1+%g0] */
{ "st", 0xc1282000, 0x00c0dfff, "F,[1]", 0 }, /* st d,[rs1+0] */
{ "st", 0xc1282000, 0x00c0d000, "F,[1+i]", 0 },
{ "st", 0xc1282000, 0x00c0d000, "F,[i+1]", 0 },
{ "st", 0xc1280000, 0x00c0d000, "F,[1+2]", 0 },
{ "st", 0xc1a00000, 0x0058201f, "D,[1]", 0 }, /* st d,[rs1+%g0] */
{ "st", 0xc1a02000, 0x00581fff, "D,[1]", 0 }, /* st d,[rs1+0] */
{ "st", 0xc1a02000, 0x00580000, "D,[1+i]", 0 },
{ "st", 0xc1a02000, 0x00580000, "D,[i+1]", 0 },
{ "st", 0xc1a00000, 0x00582000, "D,[1+2]", 0 },
{ "st", 0xc1a80000, 0x0050201f, "C,[1]", 0 }, /* st d,[rs1+%g0] */
{ "st", 0xc1a82000, 0x00501fff, "C,[1]", 0 }, /* st d,[rs1+0] */
{ "st", 0xc1a82000, 0x00500000, "C,[1+i]", 0 },
{ "st", 0xc1a82000, 0x00500000, "C,[i+1]", 0 },
{ "st", 0xc1a80000, 0x00502000, "C,[1+2]", 0 },
{ "sta", 0xc0a00000, 0x0108201f, "d,[1]A", 0 }, /* sta d,[rs1+%g0] */
{ "sta", 0xc0a00000, 0x01082000, "d,[1+2]A", 0 },
{ "stb", 0xc0280000, 0x01d0201f, "d,[1]", 0 }, /* stb d,[rs1+%g0] */
{ "stb", 0xc0282000, 0x01d01fff, "d,[1]", 0 }, /* stb d,[rs1+0] */
{ "stb", 0xc0282000, 0x01d00000, "d,[1+i]", 0 },
{ "stb", 0xc0282000, 0x01d00000, "d,[i+1]", 0 },
{ "stb", 0xc0280000, 0x01d02000, "d,[1+2]", 0 },
{ "stba", 0xc0a80000, 0x01002000, "d,[1+2]A", 0 },
{ "stba", 0xc0a80000, 0x0100201f, "d,[1]A", 0 }, /* stba d,[rs1+%g0] */
{ "std", 0xc0380000, 0x01c0201f, "d,[1]", 0 }, /* std d,[rs1+%g0] */
{ "std", 0xc0382000, 0x01c01fff, "d,[1]", 0 }, /* std d,[rs1+0] */
{ "std", 0xc0382000, 0x01c00000, "d,[1+i]", 0 },
{ "std", 0xc0382000, 0x01c00000, "d,[i+1]", 0 },
{ "std", 0xc0380000, 0x01c02000, "d,[1+2]", 0 },
{ "std", 0xc1380000, 0x00c0201f, "g,[1]", 0 }, /* std d,[rs1+%g0] */
{ "std", 0xc1382000, 0x00c01fff, "g,[1]", 0 }, /* std d,[rs1+0] */
{ "std", 0xc1382000, 0x00c00000, "g,[1+i]", 0 },
{ "std", 0xc1382000, 0x00c00000, "g,[i+1]", 0 },
{ "std", 0xc1380000, 0x00c02000, "g,[1+2]", 0 },
{ "std", 0xc1300000, 0x00c8201f, "q,[1]", 0 }, /* std d,[rs1+%g0] */
{ "std", 0xc1302000, 0x00c81fff, "q,[1]", 0 }, /* std d,[rs1+0] */
{ "std", 0xc1302000, 0x00c80000, "q,[1+i]", 0 },
{ "std", 0xc1302000, 0x00c80000, "q,[i+1]", 0 },
{ "std", 0xc1300000, 0x00c82000, "q,[1+2]", 0 },
{ "std", 0xc1b80000, 0x0040201f, "D,[1]", 0 }, /* std d,[rs1+%g0] */
{ "std", 0xc1b82000, 0x00401fff, "D,[1]", 0 }, /* std d,[rs1+0] */
{ "std", 0xc1b82000, 0x00400000, "D,[1+i]", 0 },
{ "std", 0xc1b82000, 0x00400000, "D,[i+1]", 0 },
{ "std", 0xc1b80000, 0x00402000, "D,[1+2]", 0 },
{ "std", 0xc1b00000, 0x0048201f, "Q,[1]", 0 }, /* std d,[rs1+%g0] */
{ "std", 0xc1b02000, 0x00481fff, "Q,[1]", 0 }, /* std d,[rs1+0] */
{ "std", 0xc1b02000, 0x00480000, "Q,[1+i]", 0 },
{ "std", 0xc1b02000, 0x00480000, "Q,[i+1]", 0 },
{ "std", 0xc1b00000, 0x00482000, "Q,[1+2]", 0 },
{ "stda", 0xc0b80000, 0x01402000, "d,[1+2]A", 0 },
{ "stda", 0xc0b80000, 0x0140201f, "d,[1]A", 0 }, /* stda d,[rs1+%g0] */
{ "sth", 0xc0300000, 0x01c8201f, "d,[1]", 0 }, /* sth d,[rs1+%g0] */
{ "sth", 0xc0302000, 0x01c81fff, "d,[1]", 0 }, /* sth d,[rs1+0] */
{ "sth", 0xc0300000, 0x01c82000, "d,[1+2]", 0 },
{ "sth", 0xc0302000, 0x01c80000, "d,[1+i]", 0 },
{ "sth", 0xc0302000, 0x01c80000, "d,[i+1]", 0 },
{ "stha", 0xc0b00000, 0x0148201f, "d,[1]A", 0 }, /* stha d,[rs1+%g0] */
{ "stha", 0xc0b00000, 0x01482000, "d,[1+2]A", 0 },
{ "swap", 0xc0780000, 0x0180201f, "[1],d", 0 }, /* swap [rs1+%g0],d */
{ "swap", 0xc0782000, 0x01801fff, "[1],d", 0 }, /* swap [rs1+0],d */
{ "swap", 0xc0782000, 0x01800000, "[1+i],d", 0 },
{ "swap", 0xc0782000, 0x01800000, "[i+1],d", 0 },
{ "swap", 0xc0780000, 0x01802000, "[1+2],d", 0 },
{ "swapa", 0xc0f80000, 0x01002000, "[1+2]A,d", 0 },
{ "swapa", 0xc0f80000, 0x0100201f, "[1]A,d", 0 }, /* swapa [rs1+%g0],d */
{ "restore", 0x81e80000, 0x7e17e01f, "", 0 }, /* restore %g0,%g0,%g0 */
{ "restore", 0x81e82000, 0x7e14dfff, "", 0 }, /* restore %g0,0,%g0 */
{ "restore", 0x81e82000, 0x00000000, "1,i,d", 0 },
{ "restore", 0x81e80000, 0x00000000, "1,2,d", 0 },
{ "rett", 0x81c82000, 0x40300000, "1+i", 1 },
{ "rett", 0x81c82000, 0x40300000, "i+1", 1 },
{ "rett", 0x81c80000, 0x40302000, "1+2", 1 },
{ "rett", 0x81c82000, 0x40300000, "1", 1},
{ "save", 0x81e02000, 0x40180000, "1,i,d", 0 },
{ "save", 0x81e00000, 0x40180000, "1,2,d", 0 },
{ "ret", 0x81c7e008, 0x00001ff7, "", 1 }, /* jmpl %i7+8,%g0 */
{ "retl", 0x81c3e008, 0x00001ff7, "", 1 }, /* jmpl %o7+8,%g0 */
{ "jmpl", 0x81c00000, 0x4038201f, "1,d", 1 }, /* jmpl rs1+%g0,d */
{ "jmpl", 0x81c02000, 0x4037c000, "i,d", 1 }, /* jmpl %g0+i,d */
{ "jmpl", 0x81c02000, 0x40380000, "1+i,d", 1 },
{ "jmpl", 0x81c02000, 0x40380000, "i+1,d", 1 },
{ "jmpl", 0x81c00000, 0x40382000, "1+2,d", 1 },
{ "wr", 0x81982000, 0x40600000, "1,i,t", 0 },
{ "wr", 0x81980000, 0x40600000, "1,2,t", 0 },
{ "wr", 0x81902000, 0x40680000, "1,i,w", 0 },
{ "wr", 0x81900000, 0x40680000, "1,2,w", 0 },
{ "wr", 0x81882000, 0x40700000, "1,i,p", 0 },
{ "wr", 0x81880000, 0x40700000, "1,2,p", 0 },
{ "wr", 0x81802000, 0x40780000, "1,i,y", 0 },
{ "wr", 0x81800000, 0x40780000, "1,2,y", 0 },
{ "rd", 0x81580000, 0x40a00000, "t,d", 0 },
{ "rd", 0x81500000, 0x40a80000, "w,d", 0 },
{ "rd", 0x81480000, 0x40b00000, "p,d", 0 },
{ "rd", 0x81400000, 0x40b80000, "y,d", 0 },
{ "sra", 0x81382000, 0x00000000, "1,i,d", 0 },
{ "sra", 0x81380000, 0x00000000, "1,2,d", 0 },
{ "srl", 0x81302000, 0x40c80000, "1,i,d", 0 },
{ "srl", 0x81300000, 0x40c80000, "1,2,d", 0 },
{ "sll", 0x81282000, 0x40d00000, "1,i,d", 0 },
{ "sll", 0x81280000, 0x40d00000, "1,2,d", 0 },
{ "mulscc", 0x81202000, 0x40d80000, "1,i,d", 0 },
{ "mulscc", 0x81200000, 0x40d80000, "1,2,d", 0 },
{ "clr", 0x80100000, 0x4e87e01f, "d", 0 }, /* or %g0,%g0,d */
{ "clr", 0x80102000, 0x41efdfff, "d", 0 }, /* or %g0,0,d */
{ "clr", 0xc0200000, 0x3fd8001f, "[1]", 0 }, /* st %g0,[rs1+%g0] */
{ "clr", 0xc0202000, 0x3fd81fff, "[1]", 0 }, /* st %g0,[rs1+0] */
{ "clr", 0xc0202000, 0x3fd80000, "[1+i]", 0 },
{ "clr", 0xc0202000, 0x3fd80000, "[i+1]", 0 },
{ "clr", 0xc0200000, 0x3fd80000, "[1+2]", 0 },
{ "clrb", 0xc0280000, 0x3fd0001f, "[1]", 0 }, /* stb %g0,[rs1+%g0]
{ "clrb", 0xc0282000, 0x3fd00000, "[1+i]", 0 },
{ "clrb", 0xc0282000, 0x3fd00000, "[i+1]", 0 },
{ "clrb", 0xc0280000, 0x3fd00000, "[1+2]", 0 },
{ "clrh", 0xc0300000, 0x3fc8001f, "[1]", 0 }, */ /* sth %g0,[rs1+%g0]
{ "clrh", 0xc0300000, 0x3fc80000, "[1+2]", 0 },
{ "clrh", 0xc0302000, 0x3fc80000, "[1+i]", 0 },
{ "clrh", 0xc0302000, 0x3fc80000, "[i+1]", 0 },
{ "orncc", 0x80b02000, 0x04048000, "1,i,d", 0 },
{ "orncc", 0x80b02000, 0x04048000, "i,1,d", 0 },
{ "orncc", 0x80b00000, 0x04048000, "1,2,d", 0 },
{ "tst", 0x80900000, 0x7f6fe000, "2", 0 }, */ /* orcc %g0, rs2, %g0 */
{ "tst", 0x80900000, 0x7f68201f, "1", 0 }, /* orcc rs1, %g0, %g0 */
{ "tst", 0x80902000, 0x7f681fff, "1", 0 }, /* orcc rs1, 0, %g0 */
{ "orcc", 0x80902000, 0x41680000, "1,i,d", 0 },
{ "orcc", 0x80902000, 0x41680000, "i,1,d", 0 },
{ "orcc", 0x80900000, 0x41680000, "1,2,d", 0 },
{ "orn", 0x80302000, 0x41c80000, "1,i,d", 0 },
{ "orn", 0x80302000, 0x41c80000, "i,1,d", 0 },
{ "orn", 0x80300000, 0x41c80000, "1,2,d", 0 },
{ "mov", 0x81800000, 0x4078201f, "1,y", 0 }, /* wr rs1,%g0,%y */
{ "mov", 0x81802000, 0x40781fff, "1,y", 0 }, /* wr rs1,0,%y */
{ "mov", 0x81802000, 0x40780000, "i,y", 0 },
{ "mov", 0x81400000, 0x40b80000, "y,d", 0 }, /* rd %y,d */
{ "mov", 0x81980000, 0x4060201f, "1,t", 0 }, /* wr rs1,%g0,%tbr */
{ "mov", 0x81982000, 0x40601fff, "1,t", 0 }, /* wr rs1,0,%tbr */
{ "mov", 0x81982000, 0x40600000, "i,t", 0 },
{ "mov", 0x81580000, 0x40a00000, "t,d", 0 }, /* rd %tbr,d */
{ "mov", 0x81900000, 0x4068201f, "1,w", 0 }, /* wr rs1,%g0,%wim */
{ "mov", 0x81902000, 0x40681fff, "1,w", 0 }, /* wr rs1,0,%wim */
{ "mov", 0x81902000, 0x40680000, "i,w", 0 },
{ "mov", 0x81500000, 0x40a80000, "w,d", 0 }, /* rd %wim,d */
{ "mov", 0x81880000, 0x4070201f, "1,p", 0 }, /* wr rs1,%g0,%psr */
{ "mov", 0x81882000, 0x40701fff, "1,p", 0 }, /* wr rs1,0,%psr */
{ "mov", 0x81882000, 0x40700000, "i,p", 0 },
{ "mov", 0x81480000, 0x40b00000, "p,d", 0 }, /* rd %psr,d */
{ "mov", 0x80102000, 0x41efc000, "i,d", 0 }, /* or %g0,i,d */
{ "mov", 0x80100000, 0x41efe000, "2,d", 0 }, /* or %g0,rs2,d */
{ "or", 0x80102000, 0x40800000, "1,i,d", 0 },
{ "or", 0x80102000, 0x40800000, "i,1,d", 0 },
{ "or", 0x80100000, 0x40800000, "1,2,d", 0 },
{ "bset", 0x80102000, 0x40800000, "i,r", 0 }, /* or rd,i,rd */
{ "bset", 0x80100000, 0x40800000, "2,r", 0 }, /* or rd,rs2,rd */
{ "andncc", 0x80a82000, 0x41500000, "1,i,d", 0 },
{ "andncc", 0x80a82000, 0x41500000, "i,1,d", 0 },
{ "andncc", 0x80a80000, 0x41500000, "1,2,d", 0 },
{ "andn", 0x80282000, 0x41d00000, "1,i,d", 0 },
{ "andn", 0x80282000, 0x41d00000, "i,1,d", 0 },
{ "andn", 0x80280000, 0x41d00000, "1,2,d", 0 },
{ "bclr", 0x80282000, 0x41d00000, "i,r", 0 }, /* andn rd,i,rd */
{ "bclr", 0x80280000, 0x41d00000, "2,r", 0 }, /* andn rd,rs2,rd */
{ "cmp", 0x80a02000, 0x7d580000, "1,i", 0 }, /* subcc rs1,i,%g0 */
{ "cmp", 0x80a00000, 0x7d580000, "1,2", 0 }, /* subcc rs1,rs2,%g0 */
{ "subcc", 0x80a02000, 0x41580000, "1,i,d", 0 },
{ "subcc", 0x80a00000, 0x41580000, "1,2,d", 0 },
{ "sub", 0x80202000, 0x41d80000, "1,i,d", 0 },
{ "sub", 0x80200000, 0x41d80000, "1,2,d", 0 },
{ "subx", 0x80602000, 0x41980000, "1,i,d", 0 },
{ "subx", 0x80600000, 0x41980000, "1,2,d", 0 },
{ "subxcc", 0x80e02000, 0x41180000, "1,i,d", 0 },
{ "subxcc", 0x80e00000, 0x41180000, "1,2,d", 0 },
{ "andcc", 0x80882000, 0x41700000, "1,i,d", 0 },
{ "andcc", 0x80882000, 0x41700000, "i,1,d", 0 },
{ "andcc", 0x80880000, 0x41700000, "1,2,d", 0 },
{ "and", 0x80082000, 0x41f00000, "1,i,d", 0 },
{ "and", 0x80082000, 0x41f00000, "i,1,d", 0 },
{ "and", 0x80080000, 0x41f00000, "1,2,d", 0 },
{ "inc", 0x80002001, 0x41f81ffe, "r", 0 }, /* add rs1,1,rsd */
{ "inccc", 0x80802001, 0x41781ffe, "r", 0 }, /* addcc rd,1,rd */
{ "dec", 0x80202001, 0x41d81ffe, "r", 0 }, /* sub rd,1,rd */
{ "deccc", 0x80a02001, 0x41581ffe, "r", 0 }, /* subcc rd,1,rd */
{ "btst", 0x80882000, 0x41700000, "i,1", 0 }, /* andcc rs1,i,%g0 */
{ "btst", 0x80880000, 0x41700000, "1,2", 0 }, /* andcc rs1,rs2,%0 */
{ "neg", 0x80200000, 0x41d80000, "r", 0 }, /* sub %0,rd,rd */
{ "neg", 0x80200000, 0x41d80000, "2,d", 0 }, /* sub %0,rs2,rd */
{ "addxcc", 0x80c02000, 0x41380000, "1,i,d", 0 },
{ "addxcc", 0x80c02000, 0x41380000, "i,1,d", 0 },
{ "addxcc", 0x80c00000, 0x41380000, "1,2,d", 0 },
{ "addcc", 0x80802000, 0x41780000, "1,i,d", 0 },
{ "addcc", 0x80802000, 0x41780000, "i,1,d", 0 },
{ "addcc", 0x80800000, 0x41780000, "1,2,d", 0 },
{ "addx", 0x80402000, 0x41b80000, "1,i,d", 0 },
{ "addx", 0x80402000, 0x41b80000, "i,1,d", 0 },
{ "addx", 0x80400000, 0x41b80000, "1,2,d", 0 },
{ "add", 0x80002000, 0x41f80000, "1,i,d", 0 },
{ "add", 0x80002000, 0x41f80000, "i,1,d", 0 },
{ "add", 0x80000000, 0x41f80000, "1,2,d", 0 },
{ "call", 0x9fc00000, 0x4038201f, "1", 1 }, /* jmpl rs1+%g0, %o7 */
{ "call", 0x9fc00000, 0x4038201f, "1,#", 1 },
{ "call", 0x40000000, 0x80000000, "L", 1 },
{ "call", 0x40000000, 0x80000000, "L,#", 1 },
{ "bvc", 0x3e800000, 0xc1400000, ",al", 1 },
{ "bvc", 0x1e800000, 0xc1400000, "l", 1 },
{ "bvs", 0x2e800000, 0xc1400000, ",al", 1 },
{ "bvs", 0x0e800000, 0xc1400000, "l", 1 },
{ "bpos", 0x3c800000, 0xc1400000, ",al", 1 },
{ "bpos", 0x1c800000, 0xc1400000, "l", 1 },
{ "bneg", 0x2c800000, 0xc1400000, ",al", 1 },
{ "bneg", 0x0c800000, 0xc1400000, "l", 1 },
{ "bcc", 0x3a800000, 0xc1400000, ",al", 1 },
{ "bcc", 0x1a800000, 0xc1400000, "l", 1 },
{ "bcs", 0x2a800000, 0xc1400000, ",al", 1 },
{ "bcs", 0x0a800000, 0xc1400000, "l", 1 },
{ "blu", 0x2a800000, 0xc1400000, ",al", 1 },
{ "blu", 0x0a800000, 0xc1400000, "l", 1 }, /* same as bcs */
{ "bgeu", 0x3a800000, 0xc1400000, ",al", 1 },
{ "bgeu", 0x1a800000, 0xc1400000, "l", 1 }, /* same as bcc */
{ "bgu", 0x38800000, 0xc1400000, ",al", 1 },
{ "bgu", 0x18800000, 0xc1400000, "l", 1 },
{ "bleu", 0x28800000, 0xc1400000, ",al", 1 },
{ "bleu", 0x08800000, 0xc1400000, "l", 1 },
{ "bge", 0x36800000, 0xc1400000, ",al", 1 },
{ "bge", 0x16800000, 0xc1400000, "l", 1 },
{ "bl", 0x26800000, 0xc1400000, ",al", 1 },
{ "bl", 0x06800000, 0xc1400000, "l", 1 },
{ "bg", 0x34800000, 0xc1400000, ",al", 1 },
{ "bg", 0x14800000, 0xc1400000, "l", 1 },
{ "ble", 0x24800000, 0xc1400000, ",al", 1 },
{ "ble", 0x04800000, 0xc1400000, "l", 1 },
{ "be", 0x22800000, 0xc1400000, ",al", 1 },
{ "be", 0x02800000, 0xc1400000, "l", 1 },
{ "bz", 0x22800000, 0xc1400000, ",al", 1 }, /* same as be */
{ "bz", 0x02800000, 0xc1400000, "l", 1 },
{ "bne", 0x32800000, 0xc1400000, ",al", 1 },
{ "bne", 0x12800000, 0xc1400000, "l", 1 },
{ "bnz", 0x32800000, 0xc1400000, ",al", 1 }, /* same as bne */
{ "bnz", 0x12800000, 0xc1400000, "l", 1 },
{ "b", 0x30800000, 0xc1400000, ",al", 1 },
{ "b", 0x10800000, 0xc1400000, "l", 1 },
{ "ba", 0x30800000, 0xc1400000, ",al", 1 },
{ "ba", 0x10800000, 0xc1400000, "l", 1 },
{ "bn", 0x20800000, 0xc1400000, ",al", 1 },
{ "bn", 0x00800000, 0xc1400000, "l", 1 },
{ "jmp", 0x81c00000, 0x7e38201f, "1", 1 }, /* jmpl rs1+%g0,%g0 */
{ "jmp", 0x81c02000, 0x7e3fc000, "i", 1 }, /* jmpl %g0+i,%g0 */
{ "jmp", 0x81c00000, 0x7e382000, "1+2", 1 }, /* jmpl rs1+rs2,%g0 */
{ "jmp", 0x81c02000, 0x7e380000, "1+i", 1 }, /* jmpl rs1+i,%g0 */
{ "jmp", 0x81c02000, 0x7e380000, "i+1", 1 }, /* jmpl i+rs1,%g0 */
{ "nop", 0x01000000, 0xfe3fffff, "", 0 }, /* sethi 0, %g0 */
{ "set", 0x01000000, 0xc0c00000, "Sh,d", 0 },
{ "sethi", 0x01000000, 0xc0c00000, "h,d", 0 },
{ "taddcctv", 0x81102000, 0x40e00000, "1,i,d", 0 },
{ "taddcctv", 0x81100000, 0x40e00000, "1,2,d", 0 },
{ "taddcc", 0x81002000, 0x40f80000, "1,i,d", 0 },
{ "taddcc", 0x81000000, 0x40f80000, "1,2,d", 0 },
{ "tvc", 0x9fd02000, 0x402fc000, "i", 0 }, /* tvc %g0+i */
{ "tvc", 0x9fd02000, 0x40280000, "1+i", 0 },
{ "tvc", 0x9fd00000, 0x40282000, "1+2", 0 },
{ "tvc", 0x9fd00000, 0x4028201f, "1", 0 }, /* tvc rs1+%g0 */
{ "tpos", 0x9dd02000, 0x402fc000, "i", 0 }, /* tpos %g0+i */
{ "tpos", 0x9dd02000, 0x40280000, "1+i", 0 },
{ "tpos", 0x9dd00000, 0x40282000, "1+2", 0 },
{ "tpos", 0x9dd00000, 0x4028201f, "1", 0 }, /* tpos rs1+%g0 */
{ "tcc", 0x9bd02000, 0x402fc000, "i", 0 }, /* tcc %g0+i */
{ "tcc", 0x9bd02000, 0x40280000, "1+i", 0 },
{ "tcc", 0x9bd00000, 0x40282000, "1+2", 0 },
{ "tcc", 0x9bd00000, 0x4028201f, "1", 0 }, /* tcc rs1+%g0 */
/* Same as tcc. */
{ "tlu", 0x9bd02000, 0x402fc000, "i", 0 }, /* tcc %g0+i */
{ "tlu", 0x9bd02000, 0x40280000, "1+i", 0 },
{ "tlu", 0x9bd00000, 0x40282000, "1+2", 0 },
{ "tlu", 0x9bd00000, 0x4028201f, "1", 0 }, /* tcc rs1+%g0 */
{ "tgu", 0x99d02000, 0x402fc000, "i", 0 }, /* tgu %g0+i */
{ "tgu", 0x99d02000, 0x40280000, "1+i", 0 },
{ "tgu", 0x99d00000, 0x40282000, "1+2", 0 },
{ "tgu", 0x99d00000, 0x4028201f, "1", 0 }, /* tgu rs1+%g0 */
{ "tge", 0x97d02000, 0x402fc000, "i", 0 }, /* tge %g0+i */
{ "tge", 0x97d02000, 0x40280000, "1+i", 0 },
{ "tge", 0x97d00000, 0x40282000, "1+2", 0 },
{ "tge", 0x97d00000, 0x4028201f, "1", 0 }, /* tge rs1+%g0 */
{ "tg", 0x95d02000, 0x402fc000, "i", 0 }, /* tg %g0+i */
{ "tg", 0x95d02000, 0x40280000, "1+i", 0 },
{ "tg", 0x95d00000, 0x40282000, "1+2", 0 },
{ "tg", 0x95d00000, 0x4028201f, "1", 0 }, /* tg rs1+%g0 */
{ "tne", 0x93d02000, 0x402fc000, "i", 0 }, /* tne %g0+i */
{ "tne", 0x93d02000, 0x40280000, "1+i", 0 },
{ "tne", 0x93d00000, 0x40282000, "1+2", 0 },
{ "tne", 0x93d00000, 0x4028201f, "1", 0 }, /* tne rs1+%g0 */
/* Same as tne. */
{ "tnz", 0x93d02000, 0x402fc000, "i", 0 }, /* tne %g0+i */
{ "tnz", 0x93d02000, 0x40280000, "1+i", 0 },
{ "tnz", 0x93d00000, 0x40282000, "1+2", 0 },
{ "tnz", 0x93d00000, 0x4028201f, "1", 0 }, /* tne rs1+%g0 */
{ "tleu", 0x8bd02000, 0x502fc000, "i", 0 }, /* tleu %g0+i */
{ "tleu", 0x8bd02000, 0x50280000, "1+i", 0 },
{ "tleu", 0x8bd00000, 0x50282000, "1+2", 0 },
{ "tleu", 0x8bd00000, 0x5028201f, "1", 0 }, /* tleu rs1+%g0 */
{ "ta", 0x91d02000, 0x402fc000, "i", 0 }, /* ta %g0+i */
{ "ta", 0x91d02000, 0x402d0000, "1+i", 0 },
{ "ta", 0x91d00000, 0x40282000, "1+2", 0 },
{ "ta", 0x91d00000, 0x4028201f, "1", 0 }, /* ta rs1+%g0 */
/* Same as ta. */
{ "t", 0x91d02000, 0x402fc000, "i", 0 }, /* ta %g0+i */
{ "t", 0x91d02000, 0x402d0000, "1+i", 0 },
{ "t", 0x91d00000, 0x40282000, "1+2", 0 },
{ "t", 0x91d00000, 0x4028201f, "1", 0 }, /* ta rs1+%g0 */
{ "tvs", 0x8fd02000, 0x502fc000, "i", 0 }, /* tvs %g0+i */
{ "tvs", 0x8fd02000, 0x50280000, "1+i", 0 },
{ "tvs", 0x8fd00000, 0x50282000, "1+2", 0 },
{ "tvs", 0x8fd00000, 0x5028201f, "1", 0 }, /* tvs rs1+%g0 */
{ "tneg", 0x8dd02000, 0x502fc000, "i", 0 }, /* tneg %g0+i */
{ "tneg", 0x8dd02000, 0x50280000, "1+i", 0 },
{ "tneg", 0x8dd00000, 0x50282000, "1+2", 0 },
{ "tneg", 0x8dd00000, 0x5028201f, "1", 0 }, /* tneg rs1+%g0 */
{ "tcs", 0x8bd02000, 0x502fc000, "i", 0 }, /* tcs %g0+i */
{ "tcs", 0x8bd02000, 0x50280000, "1+i", 0 },
{ "tcs", 0x8bd00000, 0x50282000, "1+2", 0 },
{ "tcs", 0x8bd00000, 0x5028201f, "1", 0 }, /* tcs rs1+%g0 */
/* Same as tcs. */
{ "tgeu", 0x8bd02000, 0x502fc000, "i", 0 }, /* tcs %g0+i */
{ "tgeu", 0x8bd02000, 0x50280000, "1+i", 0 },
{ "tgeu", 0x8bd00000, 0x50282000, "1+2", 0 },
{ "tgeu", 0x8bd00000, 0x5028201f, "1", 0 }, /* tcs rs1+%g0 */
{ "tl", 0x87d02000, 0x502fc000, "i", 0 }, /* tl %g0+i */
{ "tl", 0x87d02000, 0x50280000, "1+i", 0 },
{ "tl", 0x87d00000, 0x50282000, "1+2", 0 },
{ "tl", 0x87d00000, 0x5028201f, "1", 0 }, /* tl rs1+%g0 */
{ "tle", 0x85d02000, 0x502fc000, "i", 0 }, /* tle %g0+i */
{ "tle", 0x85d02000, 0x50280000, "1+i", 0 },
{ "tle", 0x85d00000, 0x50282000, "1+2", 0 },
{ "tle", 0x85d00000, 0x5028201f, "1", 0 }, /* tle rs1+%g0 */
{ "te", 0x83d02000, 0x502fc000, "i", 0 }, /* te %g0+i */
{ "te", 0x83d02000, 0x50280000, "1+i", 0 },
{ "te", 0x83d00000, 0x50282000, "1+2", 0 },
{ "te", 0x83d00000, 0x5028201f, "1", 0 }, /* te rs1+%g0 */
/* Same as te. */
{ "tz", 0x83d02000, 0x502fc000, "i", 0 }, /* te %g0+i */
{ "tz", 0x83d02000, 0x50280000, "1+i", 0 },
{ "tz", 0x83d00000, 0x50282000, "1+2", 0 },
{ "tz", 0x83d00000, 0x5028201f, "1", 0 }, /* te rs1+%g0 */
{ "tn", 0x81d02000, 0x502fc000, "i", 0 }, /* tn %g0+i */
{ "tn", 0x81d02000, 0x50280000, "1+i", 0 },
{ "tn", 0x81d00000, 0x50282000, "1+2", 0 },
{ "tn", 0x81d00000, 0x5028201f, "1", 0 }, /* tn rs1+%g0 */
{ "tsubcc", 0x81080000, 0x40f00000, "1,2,d", 0 },
{ "tsubcc", 0x81082000, 0x40f00000, "1,i,d", 0 },
{ "tsubcctv", 0x80580000, 0x40a00000, "1,2,d", 0 },
{ "tsubcctv", 0x80582000, 0x40a00000, "1,i,d", 0 },
{ "unimp", 0x00000000, 0x00000000, "l", 0 },
{ "iflush", 0x81d80000, 0x40202000, "1+2", 0 },
{ "iflush", 0x81d82000, 0x40200000, "1+i", 0 },
{ "xnorcc", 0x80b80000, 0x41400000, "1,2,d", 0 },
{ "xnorcc", 0x80b82000, 0x41400000, "1,i,d", 0 },
{ "xnorcc", 0x80b82000, 0x41400000, "i,1,d", 0 },
{ "xorcc", 0x80980000, 0x41600000, "1,2,d", 0 },
{ "xorcc", 0x80982000, 0x41600000, "1,i,d", 0 },
{ "xorcc", 0x80982000, 0x41600000, "i,1,d", 0 },
{ "xnor", 0x80380000, 0x41c00000, "1,2,d", 0 },
{ "xnor", 0x80382000, 0x41c00000, "1,i,d", 0 },
{ "xnor", 0x80382000, 0x41c00000, "i,1,d", 0 },
{ "xor", 0x80180000, 0x41e00000, "1,2,d", 0 },
{ "xor", 0x80182000, 0x41e00000, "1,i,d", 0 },
{ "xor", 0x80182000, 0x41e00000, "i,1,d", 0 },
{ "not", 0x80380000, 0x41c00000, "r", 0 }, /* xnor rd,%0,rd */
{ "not", 0x80380000, 0x41c00000, "1,d", 0 }, /* xnor rs1,%0,rd */
{ "btog", 0x80180000, 0x41e02000, "2,r", 0 }, /* xor rd,rs2,rd */
{ "btog", 0x80182000, 0x41e00000, "i,r", 0 }, /* xor rd,i,rd */
{ "fpop1", 0x81a00000, 0x40580000, "[1+2],d", 0 },
{ "fpop2", 0x81a80000, 0x40500000, "[1+2],d", 0 },
{ "fb", 0x31800000, 0xc0400000, ",al", 1 },
{ "fb", 0x11800000, 0xc0400000, "l", 1 },
{ "fba", 0x31800000, 0xc0400000, ",al", 1 },
{ "fba", 0x11800000, 0xc0400000, "l", 1 },
{ "fbn", 0x21800000, 0xc0400000, ",al", 1 },
{ "fbn", 0x01800000, 0xc0400000, "l", 1 },
{ "fbu", 0x2f800000, 0xc0400000, ",al", 1 },
{ "fbu", 0x0f800000, 0xc0400000, "l", 1 },
{ "fbg", 0x2d800000, 0xc0400000, ",al", 1 },
{ "fbg", 0x0d800000, 0xc0400000, "l", 1 },
{ "fbug", 0x2b800000, 0xc0400000, ",al", 1 },
{ "fbug", 0x0b800000, 0xc0400000, "l", 1 },
{ "fbl", 0x29800000, 0xc0400000, ",al", 1 },
{ "fbl", 0x09800000, 0xc0400000, "l", 1 },
{ "fbul", 0x27800000, 0xc0400000, ",al", 1 },
{ "fbul", 0x07800000, 0xc0400000, "l", 1 },
{ "fblg", 0x25800000, 0xc0400000, ",al", 1 },
{ "fblg", 0x05800000, 0xc0400000, "l", 1 },
{ "fbne", 0x23800000, 0xc0400000, ",al", 1 },
{ "fbne", 0x03800000, 0xc0400000, "l", 1 },
{ "fbe", 0x33800000, 0xc0400000, ",al", 1 },
{ "fbe", 0x13800000, 0xc0400000, "l", 1 },
{ "fbue", 0x35800000, 0xc0400000, ",al", 1 },
{ "fbue", 0x15800000, 0xc0400000, "l", 1 },
{ "fbge", 0x37800000, 0xc0400000, ",al", 1 },
{ "fbge", 0x17800000, 0xc0400000, "l", 1 },
{ "fbuge", 0x39800000, 0xc0400000, ",al", 1 },
{ "fbuge", 0x19800000, 0xc0400000, "l", 1 },
{ "fble", 0x3b800000, 0xc0400000, ",al", 1 },
{ "fble", 0x1b800000, 0xc0400000, "l", 1 },
{ "fbule", 0x3d800000, 0xc0400000, ",al", 1 },
{ "fbule", 0x1d800000, 0xc0400000, "l", 1 },
{ "fbo", 0x3f800000, 0xc0400000, ",al", 1 },
{ "fbo", 0x1f800000, 0xc0400000, "l", 1 },
{ "cba", 0x31c00000, 0xce000000, ",al", 1 },
{ "cba", 0x11c00000, 0xce000000, "l", 1 },
{ "cbn", 0x21c00000, 0xde000000, ",al", 1 },
{ "cbn", 0x01c00000, 0xde000000, "l", 1 },
{ "cb3", 0x2fc00000, 0xc0000000, ",al", 1 },
{ "cb3", 0x0fc00000, 0xc0000000, "l", 1 },
{ "cb2", 0x2dc00000, 0xc0000000, ",al", 1 },
{ "cb2", 0x0dc00000, 0xc0000000, "l", 1 },
{ "cb23", 0x2bc00000, 0xc0000000, ",al", 1 },
{ "cb23", 0x0bc00000, 0xc0000000, "l", 1 },
{ "cb1", 0x29c00000, 0xc0000000, ",al", 1 },
{ "cb1", 0x09c00000, 0xc0000000, "l", 1 },
{ "cb13", 0x27c00000, 0xc0000000, ",al", 1 },
{ "cb13", 0x07c00000, 0xc0000000, "l", 1 },
{ "cb12", 0x25c00000, 0xc0000000, ",al", 1 },
{ "cb12", 0x05c00000, 0xc0000000, "l", 1 },
{ "cb123", 0x23c00000, 0xc0000000, ",al", 1 },
{ "cb123", 0x03c00000, 0xc0000000, "l", 1 },
{ "cb0", 0x33c00000, 0xc0000000, ",al", 1 },
{ "cb0", 0x13c00000, 0xc0000000, "l", 1 },
{ "cb03", 0x35c00000, 0xc0000000, ",al", 1 },
{ "cb03", 0x15c00000, 0xc0000000, "l", 1 },
{ "cb02", 0x37c00000, 0xc0000000, ",al", 1 },
{ "cb02", 0x17c00000, 0xc0000000, "l", 1 },
{ "cb023", 0x39c00000, 0xc0000000, ",al", 1 },
{ "cb023", 0x19c00000, 0xc0000000, "l", 1 },
{ "cb01", 0x3bc00000, 0xc0000000, ",al", 1 },
{ "cb01", 0x1bc00000, 0xc0000000, "l", 1 },
{ "cb013", 0x3dc00000, 0xc0000000, ",al", 1 },
{ "cb013", 0x1dc00000, 0xc0000000, "l", 1 },
{ "cb012", 0x3fc00000, 0xc0000000, ",al", 1 },
{ "cb012", 0x1fc00000, 0xc0000000, "l", 1 },
{ "fstoi", 0x81a01a20, 0x400025c0, "f,g", 0 },
{ "fdtoi", 0x81a01a40, 0x400025a0, "f,g", 0 },
{ "fxtoi", 0x81a01a60, 0x40002580, "f,g", 0 },
{ "fitox", 0x81a01980, 0x40002660, "f,g", 0 },
{ "fitod", 0x81a01900, 0x400026e0, "f,g", 0 },
{ "fitos", 0x81a01880, 0x40002660, "f,g", 0 },
{ "fstod", 0x81a01920, 0x400026c0, "f,g", 0 },
{ "fstox", 0x81a019a0, 0x40002640, "f,g", 0 },
{ "fdtos", 0x81a018c0, 0x40002720, "f,g", 0 },
{ "fdtox", 0x81a019c0, 0x40002620, "f,g", 0 },
{ "fxtos", 0x81a018e0, 0x40002700, "f,g", 0 },
{ "fxtod", 0x81a01960, 0x40002680, "f,g", 0 },
{ "fdivx", 0x81a009e0, 0x40083600, "e,f,g", 0 },
{ "fdivd", 0x81a009c0, 0x40003620, "e,f,g", 0 },
{ "fdivs", 0x81a009a0, 0x40003640, "e,f,g", 0 },
{ "fmuls", 0x81a00920, 0x400036c0, "e,f,g", 0 },
{ "fmuld", 0x81a00940, 0x400036a0, "e,f,g", 0 },
{ "fmulx", 0x81a00960, 0x40003680, "e,f,g", 0 },
{ "fsqrts", 0x81a00520, 0x40003ac0, "f,g", 0 },
{ "fsqrtd", 0x81a00540, 0x40003aa8, "f,g", 0 },
{ "fsqrtx", 0x81a00560, 0x40003a80, "f,g", 0 },
{ "fabss", 0x81a00120, 0x40003ec0, "f,g", 0 },
{ "fnegs", 0x81a000a0, 0x40003f40, "f,g", 0 },
{ "fmovs", 0x81a00020, 0x40003fc0, "f,g", 0 },
{ "fsubx", 0x81a008e0, 0x40003700, "e,f,g", 0 },
{ "fsubd", 0x81a008c0, 0x40003720, "e,f,g", 0 },
{ "fsubs", 0x81a008a0, 0x40003740, "e,f,g", 0 },
{ "faddx", 0x81a00860, 0x40003780, "e,f,g", 0 },
{ "faddd", 0x81a00840, 0x400037a0, "e,f,g", 0 },
{ "fadds", 0x81a00820, 0x400037c0, "e,f,g", 0 },
{ "fcmpex", 0x81a80ae0, 0x40003500, "e,f", 0 },
{ "fcmped", 0x81a80ac0, 0x40003520, "e,f", 0 },
{ "fcmpes", 0x81a80aa0, 0x40003540, "e,f", 0 },
{ "fcmpx", 0x81a80a60, 0x40003580, "e,f", 0 },
{ "fcmpd", 0x81a80a40, 0x400035a0, "e,f", 0 },
{ "fcmps", 0x81a80a20, 0x400035c0, "e,f", 0 },
{ "cpop1", 0x81b00000, 0x40480000, "[1+2],d", 0 },
{ "cpop2", 0x81b80000, 0x40400000, "[1+2],d", 0 },
};
#define NUMOPCODES ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0]))

213
include/tahoe-opcode.h Executable file
View File

@ -0,0 +1,213 @@
/*
* Ported by the State University of New York at Buffalo by the Distributed
* Computer Systems Lab, Department of Computer Science, 1991.
*/
#ifndef tahoe_opcodeT
#define tahoe_opcodeT int
#endif /* no tahoe_opcodeT */
struct vot_wot /* tahoe opcode table: wot to do with this */
/* particular opcode */
{
char * args; /* how to compile said opcode */
tahoe_opcodeT code; /* op-code (may be > 8 bits!) */
};
struct vot /* tahoe opcode text */
{
char * name; /* opcode name: lowercase string [key] */
struct vot_wot detail; /* rest of opcode table [datum] */
};
#define vot_how args
#define vot_code code
#define vot_detail detail
#define vot_name name
static struct vot
votstrs[] =
{
{ "halt", {"", 0x00 } },
{ "sinf", {"", 0x05 } },
{ "ldf", {"rl", 0x06 } },
{ "ldd", {"rq", 0x07 } },
{ "addb2", {"rbmb", 0x08 } },
{ "movb", {"rbwb", 0x09 } },
{ "addw2", {"rwmw", 0x0a } },
{ "movw", {"rwww", 0x0b } },
{ "addl2", {"rlml", 0x0c } },
{ "movl", {"rlwl", 0x0d } },
{ "bbs", {"rlvlbw", 0x0e } },
{ "nop", {"", 0x10 } },
{ "brb", {"bb", 0x11 } },
{ "brw", {"bw", 0x13 } },
{ "cosf", {"", 0x15 } },
{ "lnf", {"rl", 0x16 } },
{ "lnd", {"rq", 0x17 } },
{ "addb3", {"rbrbwb", 0x18 } },
{ "cmpb", {"rbwb", 0x19 } },
{ "addw3", {"rwrwww", 0x1a } },
{ "cmpw", {"rwww", 0x1b } },
{ "addl3", {"rlrlwl", 0x1c } },
{ "cmpl", {"rlwl", 0x1d } },
{ "bbc", {"rlvlbw", 0x1e } },
{ "rei", {"", 0x20 } },
{ "bneq", {"bb", 0x21 } },
{ "bnequ", {"bb", 0x21 } },
{ "cvtwl", {"rwwl", 0x23 } },
{ "stf", {"wl", 0x26 } },
{ "std", {"wq", 0x27 } },
{ "subb2", {"rbmb", 0x28 } },
{ "mcomb", {"rbwb", 0x29 } },
{ "subw2", {"rwmw", 0x2a } },
{ "mcomw", {"rwww", 0x2b } },
{ "subl2", {"rlml", 0x2c } },
{ "mcoml", {"rlwl", 0x2d } },
{ "emul", {"rlrlrlwq", 0x2e } },
{ "aoblss", {"rlmlbw", 0x2f } },
{ "bpt", {"", 0x30 } },
{ "beql", {"bb", 0x31 } },
{ "beqlu", {"bb", 0x31 } },
{ "cvtwb", {"rwwb", 0x33 } },
{ "logf", {"", 0x35 } },
{ "cmpf", {"rl", 0x36 } },
{ "cmpd", {"rq", 0x37 } },
{ "subb3", {"rbrbwb", 0x38 } },
{ "bitb", {"rbrb", 0x39 } },
{ "subw3", {"rwrwww", 0x3a } },
{ "bitw", {"rwrw", 0x3b } },
{ "subl3", {"rlrlwl", 0x3c } },
{ "bitl", {"rlrl", 0x3d } },
{ "ediv", {"rlrqwlwl", 0x3e } },
{ "aobleq", {"rlmlbw", 0x3f } },
{ "ret", {"", 0x40 } },
{ "bgtr", {"bb", 0x41 } },
{ "sqrtf", {"", 0x45 } },
{ "cmpf2", {"rl", 0x46 } },
{ "cmpd2", {"rqrq", 0x47 } },
{ "shll", {"rbrlwl", 0x48 } },
{ "clrb", {"wb", 0x49 } },
{ "shlq", {"rbrqwq", 0x4a } },
{ "clrw", {"ww", 0x4b } },
{ "mull2", {"rlml", 0x4c } },
{ "clrl", {"wl", 0x4d } },
{ "shal", {"rbrlwl", 0x4e } },
{ "bleq", {"bb", 0x51 } },
{ "expf", {"", 0x55 } },
{ "tstf", {"", 0x56 } },
{ "tstd", {"", 0x57 } },
{ "shrl", {"rbrlwl", 0x58 } },
{ "tstb", {"rb", 0x59 } },
{ "shrq", {"rbrqwq", 0x5a } },
{ "tstw", {"rw", 0x5b } },
{ "mull3", {"rlrlwl", 0x5c } },
{ "tstl", {"rl", 0x5d } },
{ "shar", {"rbrlwl", 0x5e } },
{ "bbssi", {"rlmlbw", 0x5f } },
{ "ldpctx", {"", 0x60 } },
{ "pushd", {"", 0x67 } },
{ "incb", {"mb", 0x69 } },
{ "incw", {"mw", 0x6b } },
{ "divl2", {"rlml", 0x6c } },
{ "incl", {"ml", 0x6d } },
{ "cvtlb", {"rlwb", 0x6f } },
{ "svpctx", {"", 0x70 } },
{ "jmp", {"ab", 0x71 } },
{ "cvlf", {"rl", 0x76 } },
{ "cvld", {"rl", 0x77 } },
{ "decb", {"mb", 0x79 } },
{ "decw", {"mw", 0x7b } },
{ "divl3", {"rlrlwl", 0x7c } },
{ "decl", {"ml", 0x7d } },
{ "cvtlw", {"rlww", 0x7f } },
{ "bgeq", {"bb", 0x81 } },
{ "movs2", {"abab", 0x82 } },
{ "cvfl", {"wl", 0x86 } },
{ "cvdl", {"wl", 0x87 } },
{ "orb2", {"rbmb", 0x88 } },
{ "cvtbl", {"rbwl", 0x89 } },
{ "orw2", {"rwmw", 0x8a } },
{ "bispsw", {"rw", 0x8b } },
{ "orl2", {"rlml", 0x8c } },
{ "adwc", {"rlml", 0x8d } },
{ "adda", {"rlml", 0x8e } },
{ "blss", {"bb", 0x91 } },
{ "cmps2", {"abab", 0x92 } },
{ "ldfd", {"rl", 0x97 } },
{ "orb3", {"rbrbwb", 0x98 } },
{ "cvtbw", {"rbww", 0x99 } },
{ "orw3", {"rwrwww", 0x9a } },
{ "bicpsw", {"rw", 0x9b } },
{ "orl3", {"rlrlwl", 0x9c } },
{ "sbwc", {"rlml", 0x9d } },
{ "suba", {"rlml", 0x9e } },
{ "bgtru", {"bb", 0xa1 } },
{ "cvdf", {"", 0xa6 } },
{ "andb2", {"rbmb", 0xa8 } },
{ "movzbl", {"rbwl", 0xa9 } },
{ "andw2", {"rwmw", 0xaa } },
{ "loadr", {"rwal", 0xab } },
{ "andl2", {"rlml", 0xac } },
{ "mtpr", {"rlrl", 0xad } },
{ "ffs", {"rlwl", 0xae } },
{ "blequ", {"bb", 0xb1 } },
{ "negf", {"", 0xb6 } },
{ "negd", {"", 0xb7 } },
{ "andb3", {"rbrbwb", 0xb8 } },
{ "movzbw", {"rbww", 0xb9 } },
{ "andw3", {"rwrwww", 0xba } },
{ "storer", {"rwal", 0xbb } },
{ "andl3", {"rlrlwl", 0xbc } },
{ "mfpr", {"rlwl", 0xbd } },
{ "ffc", {"rlwl", 0xbe } },
{ "calls", {"rbab", 0xbf } },
{ "prober", {"rbabrl", 0xc0 } },
{ "bvc", {"bb", 0xc1 } },
{ "movs3", {"ababrw", 0xc2 } },
{ "movzwl", {"rwwl", 0xc3 } },
{ "addf", {"rl", 0xc6 } },
{ "addd", {"rq", 0xc7 } },
{ "xorb2", {"rbmb", 0xc8 } },
{ "movob", {"rbwb", 0xc9 } },
{ "xorw2", {"rwmw", 0xca } },
{ "movow", {"rwww", 0xcb } },
{ "xorl2", {"rlml", 0xcc } },
{ "movpsl", {"wl", 0xcd } },
{ "kcall", {"rw", 0xcf } },
{ "probew", {"rbabrl", 0xd0 } },
{ "bvs", {"bb", 0xd1 } },
{ "cmps3", {"ababrw", 0xd2 } },
{ "subf", {"rq", 0xd6 } },
{ "subd", {"rq", 0xd7 } },
{ "xorb3", {"rbrbwb", 0xd8 } },
{ "pushb", {"rb", 0xd9 } },
{ "xorw3", {"rwrwww", 0xda } },
{ "pushw", {"rw", 0xdb } },
{ "xorl3", {"rlrlwl", 0xdc } },
{ "pushl", {"rl", 0xdd } },
{ "insque", {"abab", 0xe0 } },
{ "bcs", {"bb", 0xe1 } },
{ "bgequ", {"bb", 0xe1 } },
{ "mulf", {"rq", 0xe6 } },
{ "muld", {"rq", 0xe7 } },
{ "mnegb", {"rbwb", 0xe8 } },
{ "movab", {"abwl", 0xe9 } },
{ "mnegw", {"rwww", 0xea } },
{ "movaw", {"awwl", 0xeb } },
{ "mnegl", {"rlwl", 0xec } },
{ "moval", {"alwl", 0xed } },
{ "remque", {"ab", 0xf0 } },
{ "bcc", {"bb", 0xf1 } },
{ "blssu", {"bb", 0xf1 } },
{ "divf", {"rq", 0xf6 } },
{ "divd", {"rq", 0xf7 } },
{ "movblk", {"alalrw", 0xf8 } },
{ "pushab", {"ab", 0xf9 } },
{ "pushaw", {"aw", 0xfb } },
{ "casel", {"rlrlrl", 0xfc } },
{ "pushal", {"al", 0xfd } },
{ "callf", {"rbab", 0xfe } },
{ "" , "" } /* empty is end sentinel */
};

382
include/vax-opcode.h Executable file
View File

@ -0,0 +1,382 @@
/* Vax opcde list.
Copyright (C) 1989, Free Software Foundation, Inc.
This file is part of GDB and GAS.
GDB and GAS are free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 1, or (at your option)
any later version.
GDB and GAS are distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GDB or GAS; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
#ifndef vax_opcodeT
#define vax_opcodeT int
#endif /* no vax_opcodeT */
struct vot_wot /* vax opcode table: wot to do with this */
/* particular opcode */
{
char * args; /* how to compile said opcode */
vax_opcodeT code; /* op-code (may be > 8 bits!) */
};
struct vot /* vax opcode text */
{
char * name; /* opcode name: lowercase string [key] */
struct vot_wot detail; /* rest of opcode table [datum] */
};
#define vot_how args
#define vot_code code
#define vot_detail detail
#define vot_name name
static const struct vot
votstrs[] =
{
{ "halt", {"", 0x00 } },
{ "nop", {"", 0x01 } },
{ "rei", {"", 0x02 } },
{ "bpt", {"", 0x03 } },
{ "ret", {"", 0x04 } },
{ "rsb", {"", 0x05 } },
{ "ldpctx", {"", 0x06 } },
{ "svpctx", {"", 0x07 } },
{ "cvtps", {"rwabrwab", 0x08 } },
{ "cvtsp", {"rwabrwab", 0x09 } },
{ "index", {"rlrlrlrlrlwl", 0x0a } },
{ "crc", {"abrlrwab", 0x0b } },
{ "prober", {"rbrwab", 0x0c } },
{ "probew", {"rbrwab", 0x0d } },
{ "insque", {"abab", 0x0e } },
{ "remque", {"abwl", 0x0f } },
{ "bsbb", {"bb", 0x10 } },
{ "brb", {"bb", 0x11 } },
{ "bneq", {"bb", 0x12 } },
{ "bnequ", {"bb", 0x12 } },
{ "beql", {"bb", 0x13 } },
{ "beqlu", {"bb", 0x13 } },
{ "bgtr", {"bb", 0x14 } },
{ "bleq", {"bb", 0x15 } },
{ "jsb", {"ab", 0x16 } },
{ "jmp", {"ab", 0x17 } },
{ "bgeq", {"bb", 0x18 } },
{ "blss", {"bb", 0x19 } },
{ "bgtru", {"bb", 0x1a } },
{ "blequ", {"bb", 0x1b } },
{ "bvc", {"bb", 0x1c } },
{ "bvs", {"bb", 0x1d } },
{ "bcc", {"bb", 0x1e } },
{ "bgequ", {"bb", 0x1e } },
{ "blssu", {"bb", 0x1f } },
{ "bcs", {"bb", 0x1f } },
{ "addp4", {"rwabrwab", 0x20 } },
{ "addp6", {"rwabrwabrwab", 0x21 } },
{ "subp4", {"rwabrwab", 0x22 } },
{ "subp6", {"rwabrwabrwab", 0x23 } },
{ "cvtpt", {"rwababrwab", 0x24 } },
{ "mulp", {"rwabrwabrwab", 0x25 } },
{ "cvttp", {"rwababrwab", 0x26 } },
{ "divp", {"rwabrwabrwab", 0x27 } },
{ "movc3", {"rwabab", 0x28 } },
{ "cmpc3", {"rwabab", 0x29 } },
{ "scanc", {"rwababrb", 0x2a } },
{ "spanc", {"rwababrb", 0x2b } },
{ "movc5", {"rwabrbrwab", 0x2c } },
{ "cmpc5", {"rwabrbrwab", 0x2d } },
{ "movtc", {"rwabrbabrwab", 0x2e } },
{ "movtuc", {"rwabrbabrwab", 0x2f } },
{ "bsbw", {"bw", 0x30 } },
{ "brw", {"bw", 0x31 } },
{ "cvtwl", {"rwwl", 0x32 } },
{ "cvtwb", {"rwwb", 0x33 } },
{ "movp", {"rwabab", 0x34 } },
{ "cmpp3", {"rwabab", 0x35 } },
{ "cvtpl", {"rwabwl", 0x36 } },
{ "cmpp4", {"rwabrwab", 0x37 } },
{ "editpc", {"rwababab", 0x38 } },
{ "matchc", {"rwabrwab", 0x39 } },
{ "locc", {"rbrwab", 0x3a } },
{ "skpc", {"rbrwab", 0x3b } },
{ "movzwl", {"rwwl", 0x3c } },
{ "acbw", {"rwrwmwbw", 0x3d } },
{ "movaw", {"awwl", 0x3e } },
{ "pushaw", {"aw", 0x3f } },
{ "addf2", {"rfmf", 0x40 } },
{ "addf3", {"rfrfwf", 0x41 } },
{ "subf2", {"rfmf", 0x42 } },
{ "subf3", {"rfrfwf", 0x43 } },
{ "mulf2", {"rfmf", 0x44 } },
{ "mulf3", {"rfrfwf", 0x45 } },
{ "divf2", {"rfmf", 0x46 } },
{ "divf3", {"rfrfwf", 0x47 } },
{ "cvtfb", {"rfwb", 0x48 } },
{ "cvtfw", {"rfww", 0x49 } },
{ "cvtfl", {"rfwl", 0x4a } },
{ "cvtrfl", {"rfwl", 0x4b } },
{ "cvtbf", {"rbwf", 0x4c } },
{ "cvtwf", {"rwwf", 0x4d } },
{ "cvtlf", {"rlwf", 0x4e } },
{ "acbf", {"rfrfmfbw", 0x4f } },
{ "movf", {"rfwf", 0x50 } },
{ "cmpf", {"rfrf", 0x51 } },
{ "mnegf", {"rfwf", 0x52 } },
{ "tstf", {"rf", 0x53 } },
{ "emodf", {"rfrbrfwlwf", 0x54 } },
{ "polyf", {"rfrwab", 0x55 } },
{ "cvtfd", {"rfwd", 0x56 } },
/* opcode 57 is not defined yet */
{ "adawi", {"rwmw", 0x58 } },
/* opcode 59 is not defined yet */
/* opcode 5a is not defined yet */
/* opcode 5b is not defined yet */
{ "insqhi", {"abaq", 0x5c } },
{ "insqti", {"abaq", 0x5d } },
{ "remqhi", {"aqwl", 0x5e } },
{ "remqti", {"aqwl", 0x5f } },
{ "addd2", {"rdmd", 0x60 } },
{ "addd3", {"rdrdwd", 0x61 } },
{ "subd2", {"rdmd", 0x62 } },
{ "subd3", {"rdrdwd", 0x63 } },
{ "muld2", {"rdmd", 0x64 } },
{ "muld3", {"rdrdwd", 0x65 } },
{ "divd2", {"rdmd", 0x66 } },
{ "divd3", {"rdrdwd", 0x67 } },
{ "cvtdb", {"rdwb", 0x68 } },
{ "cvtdw", {"rdww", 0x69 } },
{ "cvtdl", {"rdwl", 0x6a } },
{ "cvtrdl", {"rdwl", 0x6b } },
{ "cvtbd", {"rbwd", 0x6c } },
{ "cvtwd", {"rwwd", 0x6d } },
{ "cvtld", {"rlwd", 0x6e } },
{ "acbd", {"rdrdmdbw", 0x6f } },
{ "movd", {"rdwd", 0x70 } },
{ "cmpd", {"rdrd", 0x71 } },
{ "mnegd", {"rdwd", 0x72 } },
{ "tstd", {"rd", 0x73 } },
{ "emodd", {"rdrbrdwlwd", 0x74 } },
{ "polyd", {"rdrwab", 0x75 } },
{ "cvtdf", {"rdwf", 0x76 } },
/* opcode 77 is not defined yet */
{ "ashl", {"rbrlwl", 0x78 } },
{ "ashq", {"rbrqwq", 0x79 } },
{ "emul", {"rlrlrlwq", 0x7a } },
{ "ediv", {"rlrqwlwl", 0x7b } },
{ "clrd", {"wd", 0x7c } },
{ "clrg", {"wg", 0x7c } },
{ "clrq", {"wd", 0x7c } },
{ "movq", {"rqwq", 0x7d } },
{ "movaq", {"aqwl", 0x7e } },
{ "movad", {"adwl", 0x7e } },
{ "pushaq", {"aq", 0x7f } },
{ "pushad", {"ad", 0x7f } },
{ "addb2", {"rbmb", 0x80 } },
{ "addb3", {"rbrbwb", 0x81 } },
{ "subb2", {"rbmb", 0x82 } },
{ "subb3", {"rbrbwb", 0x83 } },
{ "mulb2", {"rbmb", 0x84 } },
{ "mulb3", {"rbrbwb", 0x85 } },
{ "divb2", {"rbmb", 0x86 } },
{ "divb3", {"rbrbwb", 0x87 } },
{ "bisb2", {"rbmb", 0x88 } },
{ "bisb3", {"rbrbwb", 0x89 } },
{ "bicb2", {"rbmb", 0x8a } },
{ "bicb3", {"rbrbwb", 0x8b } },
{ "xorb2", {"rbmb", 0x8c } },
{ "xorb3", {"rbrbwb", 0x8d } },
{ "mnegb", {"rbwb", 0x8e } },
{ "caseb", {"rbrbrb", 0x8f } },
{ "movb", {"rbwb", 0x90 } },
{ "cmpb", {"rbrb", 0x91 } },
{ "mcomb", {"rbwb", 0x92 } },
{ "bitb", {"rbrb", 0x93 } },
{ "clrb", {"wb", 0x94 } },
{ "tstb", {"rb", 0x95 } },
{ "incb", {"mb", 0x96 } },
{ "decb", {"mb", 0x97 } },
{ "cvtbl", {"rbwl", 0x98 } },
{ "cvtbw", {"rbww", 0x99 } },
{ "movzbl", {"rbwl", 0x9a } },
{ "movzbw", {"rbww", 0x9b } },
{ "rotl", {"rbrlwl", 0x9c } },
{ "acbb", {"rbrbmbbw", 0x9d } },
{ "movab", {"abwl", 0x9e } },
{ "pushab", {"ab", 0x9f } },
{ "addw2", {"rwmw", 0xa0 } },
{ "addw3", {"rwrwww", 0xa1 } },
{ "subw2", {"rwmw", 0xa2 } },
{ "subw3", {"rwrwww", 0xa3 } },
{ "mulw2", {"rwmw", 0xa4 } },
{ "mulw3", {"rwrwww", 0xa5 } },
{ "divw2", {"rwmw", 0xa6 } },
{ "divw3", {"rwrwww", 0xa7 } },
{ "bisw2", {"rwmw", 0xa8 } },
{ "bisw3", {"rwrwww", 0xa9 } },
{ "bicw2", {"rwmw", 0xaa } },
{ "bicw3", {"rwrwww", 0xab } },
{ "xorw2", {"rwmw", 0xac } },
{ "xorw3", {"rwrwww", 0xad } },
{ "mnegw", {"rwww", 0xae } },
{ "casew", {"rwrwrw", 0xaf } },
{ "movw", {"rwww", 0xb0 } },
{ "cmpw", {"rwrw", 0xb1 } },
{ "mcomw", {"rwww", 0xb2 } },
{ "bitw", {"rwrw", 0xb3 } },
{ "clrw", {"ww", 0xb4 } },
{ "tstw", {"rw", 0xb5 } },
{ "incw", {"mw", 0xb6 } },
{ "decw", {"mw", 0xb7 } },
{ "bispsw", {"rw", 0xb8 } },
{ "bicpsw", {"rw", 0xb9 } },
{ "popr", {"rw", 0xba } },
{ "pushr", {"rw", 0xbb } },
{ "chmk", {"rw", 0xbc } },
{ "chme", {"rw", 0xbd } },
{ "chms", {"rw", 0xbe } },
{ "chmu", {"rw", 0xbf } },
{ "addl2", {"rlml", 0xc0 } },
{ "addl3", {"rlrlwl", 0xc1 } },
{ "subl2", {"rlml", 0xc2 } },
{ "subl3", {"rlrlwl", 0xc3 } },
{ "mull2", {"rlml", 0xc4 } },
{ "mull3", {"rlrlwl", 0xc5 } },
{ "divl2", {"rlml", 0xc6 } },
{ "divl3", {"rlrlwl", 0xc7 } },
{ "bisl2", {"rlml", 0xc8 } },
{ "bisl3", {"rlrlwl", 0xc9 } },
{ "bicl2", {"rlml", 0xca } },
{ "bicl3", {"rlrlwl", 0xcb } },
{ "xorl2", {"rlml", 0xcc } },
{ "xorl3", {"rlrlwl", 0xcd } },
{ "mnegl", {"rlwl", 0xce } },
{ "casel", {"rlrlrl", 0xcf } },
{ "movl", {"rlwl", 0xd0 } },
{ "cmpl", {"rlrl", 0xd1 } },
{ "mcoml", {"rlwl", 0xd2 } },
{ "bitl", {"rlrl", 0xd3 } },
{ "clrf", {"wf", 0xd4 } },
{ "clrl", {"wl", 0xd4 } },
{ "tstl", {"rl", 0xd5 } },
{ "incl", {"ml", 0xd6 } },
{ "decl", {"ml", 0xd7 } },
{ "adwc", {"rlml", 0xd8 } },
{ "sbwc", {"rlml", 0xd9 } },
{ "mtpr", {"rlrl", 0xda } },
{ "mfpr", {"rlwl", 0xdb } },
{ "movpsl", {"wl", 0xdc } },
{ "pushl", {"rl", 0xdd } },
{ "moval", {"alwl", 0xde } },
{ "movaf", {"afwl", 0xde } },
{ "pushal", {"al", 0xdf } },
{ "pushaf", {"af", 0xdf } },
{ "bbs", {"rlabbb", 0xe0 } },
{ "bbc", {"rlabbb", 0xe1 } },
{ "bbss", {"rlabbb", 0xe2 } },
{ "bbcs", {"rlabbb", 0xe3 } },
{ "bbsc", {"rlabbb", 0xe4 } },
{ "bbcc", {"rlabbb", 0xe5 } },
{ "bbssi", {"rlabbb", 0xe6 } },
{ "bbcci", {"rlabbb", 0xe7 } },
{ "blbs", {"rlbb", 0xe8 } },
{ "blbc", {"rlbb", 0xe9 } },
{ "ffs", {"rlrbvbwl", 0xea } },
{ "ffc", {"rlrbvbwl", 0xeb } },
{ "cmpv", {"rlrbvbrl", 0xec } },
{ "cmpzv", {"rlrbvbrl", 0xed } },
{ "extv", {"rlrbvbwl", 0xee } },
{ "extzv", {"rlrbvbwl", 0xef } },
{ "insv", {"rlrlrbvb", 0xf0 } },
{ "acbl", {"rlrlmlbw", 0xf1 } },
{ "aoblss", {"rlmlbb", 0xf2 } },
{ "aobleq", {"rlmlbb", 0xf3 } },
{ "sobgeq", {"mlbb", 0xf4 } },
{ "sobgtr", {"mlbb", 0xf5 } },
{ "cvtlb", {"rlwb", 0xf6 } },
{ "cvtlw", {"rlww", 0xf7 } },
{ "ashp", {"rbrwabrbrwab", 0xf8 } },
{ "cvtlp", {"rlrwab", 0xf9 } },
{ "callg", {"abab", 0xfa } },
{ "calls", {"rlab", 0xfb } },
{ "xfc", {"", 0xfc } },
/* undefined opcodes here */
{ "cvtdh", {"rdwh", 0x32fd } },
{ "cvtgf", {"rgwh", 0x33fd } },
{ "addg2", {"rgmg", 0x40fd } },
{ "addg3", {"rgrgwg", 0x41fd } },
{ "subg2", {"rgmg", 0x42fd } },
{ "subg3", {"rgrgwg", 0x43fd } },
{ "mulg2", {"rgmg", 0x44fd } },
{ "mulg3", {"rgrgwg", 0x45fd } },
{ "divg2", {"rgmg", 0x46fd } },
{ "divg3", {"rgrgwg", 0x47fd } },
{ "cvtgb", {"rgwb", 0x48fd } },
{ "cvtgw", {"rgww", 0x49fd } },
{ "cvtgl", {"rgwl", 0x4afd } },
{ "cvtrgl", {"rgwl", 0x4bfd } },
{ "cvtbg", {"rbwg", 0x4cfd } },
{ "cvtwg", {"rwwg", 0x4dfd } },
{ "cvtlg", {"rlwg", 0x4efd } },
{ "acbg", {"rgrgmgbw", 0x4ffd } },
{ "movg", {"rgwg", 0x50fd } },
{ "cmpg", {"rgrg", 0x51fd } },
{ "mnegg", {"rgwg", 0x52fd } },
{ "tstg", {"rg", 0x53fd } },
{ "emodg", {"rgrwrgwlwg", 0x54fd } },
{ "polyg", {"rgrwab", 0x55fd } },
{ "cvtgh", {"rgwh", 0x56fd } },
/* undefined opcodes here */
{ "addh2", {"rhmh", 0x60fd } },
{ "addh3", {"rhrhwh", 0x61fd } },
{ "subh2", {"rhmh", 0x62fd } },
{ "subh3", {"rhrhwh", 0x63fd } },
{ "mulh2", {"rhmh", 0x64fd } },
{ "mulh3", {"rhrhwh", 0x65fd } },
{ "divh2", {"rhmh", 0x66fd } },
{ "divh3", {"rhrhwh", 0x67fd } },
{ "cvthb", {"rhwb", 0x68fd } },
{ "cvthw", {"rhww", 0x69fd } },
{ "cvthl", {"rhwl", 0x6afd } },
{ "cvtrhl", {"rhwl", 0x6bfd } },
{ "cvtbh", {"rbwh", 0x6cfd } },
{ "cvtwh", {"rwwh", 0x6dfd } },
{ "cvtlh", {"rlwh", 0x6efd } },
{ "acbh", {"rhrhmhbw", 0x6ffd } },
{ "movh", {"rhwh", 0x70fd } },
{ "cmph", {"rhrh", 0x71fd } },
{ "mnegh", {"rhwh", 0x72fd } },
{ "tsth", {"rh", 0x73fd } },
{ "emodh", {"rhrwrhwlwh", 0x74fd } },
{ "polyh", {"rhrwab", 0x75fd } },
{ "cvthg", {"rhwg", 0x76fd } },
/* undefined opcodes here */
{ "clrh", {"wh", 0x7cfd } },
{ "clro", {"wo", 0x7cfd } },
{ "movo", {"rowo", 0x7dfd } },
{ "movah", {"ahwl", 0x7efd } },
{ "movao", {"aowl", 0x7efd } },
{ "pushah", {"ah", 0x7ffd } },
{ "pushao", {"ao", 0x7ffd } },
/* undefined opcodes here */
{ "cvtfh", {"rfwh", 0x98fd } },
{ "cvtfg", {"rfwg", 0x99fd } },
/* undefined opcodes here */
{ "cvthf", {"rhwf", 0xf6fd } },
{ "cvthd", {"rhwd", 0xf7fd } },
/* undefined opcodes here */
{ "bugl", {"rl", 0xfdff } },
{ "bugw", {"rw", 0xfeff } },
/* undefined opcodes here */
{ "" , "" } /* empty is end sentinel */
}; /* votstrs */
/* end: vax.opcode.h */