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2003-09-25 H.J. Lu <hongjiu.lu@intel.com>

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* gas/ia64/alias-ilp32.d: New file.
	* gas/ia64/secname-ilp32.d: Likewise.
	* gas/ia64/unwind-ilp32.d: Likewise.

	* gas/ia64/dependency-1.d: Support ILP32.
	* gas/ia64/dv-branch.d: Likewise.
	* gas/ia64/dv-imply.d: Likewise.
	* gas/ia64/dv-mutex.d: Likewise.
	* gas/ia64/dv-safe.d: Likewise.
	* gas/ia64/dv-srlz.d: Likewise.
	* gas/ia64/global.d: Likewise.
	* gas/ia64/ldxmov-1.d: Likewise.
	* gas/ia64/ltoff22x-1.d:Likewise.
	* gas/ia64/opc-a.d: Likewise.
	* gas/ia64/opc-b.d: Likewise.
	* gas/ia64/opc-f.d: Likewise.
	* gas/ia64/opc-i.d: Likewise.
	* gas/ia64/opc-m.d: Likewise.
	* gas/ia64/opc-x.d: Likewise.
	* gas/ia64/order.d: Likewise.
	* gas/ia64/regs.d: Likewise.
	* gas/ia64/tls.d: Likewise.

	* gas/ia64/ia64.exp: Run "secname-ilp32", "unwind-ilp32" and
	"alias-ilp32" for ia64-*-hpux*.
This commit is contained in:
H.J. Lu 2003-09-26 03:54:09 +00:00
parent 3809fa0e38
commit 11e8e359f9
22 changed files with 111 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
gas/testsuite/gas/ia64/alias-ilp32.d Normal file
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@ -0,0 +1,30 @@
#readelf: -Ss
#name: ia64 alias and secalias (ilp32)
#as: -milp32
#source: alias.s
There are 8 section headers, starting at offset 0x78:
Section Headers:
\[Nr\] Name Type Addr Off Size ES Flg Lk Inf Al
\[ 0\] NULL 00000000 000000 000000 00 0 0 0
\[ 1\] .text PROGBITS 00000000 000040 000000 00 AX 0 0 16
\[ 2\] .data PROGBITS 00000000 000040 000000 00 WA 0 0 1
\[ 3\] .bss NOBITS 00000000 000040 000000 00 WA 0 0 1
\[ 4\] 1234 PROGBITS 00000000 000040 000005 00 WA 0 0 1
\[ 5\] .shstrtab STRTAB 00000000 000045 000031 00 0 0 1
\[ 6\] .symtab SYMTAB 00000000 0001b8 000060 10 7 6 4
\[ 7\] .strtab STRTAB 00000000 000218 000006 00 0 0 1
Key to Flags:
W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
I \(info\), L \(link order\), G \(group\), x \(unknown\)
O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)
Symbol table '.symtab' contains 6 entries:
Num: Value Size Type Bind Vis Ndx Name
0: 00000000 0 NOTYPE LOCAL DEFAULT UND
1: 00000000 0 SECTION LOCAL DEFAULT 1
2: 00000000 0 SECTION LOCAL DEFAULT 2
3: 00000000 0 SECTION LOCAL DEFAULT 3
4: 00000000 0 SECTION LOCAL DEFAULT 4
5: 00000000 0 NOTYPE LOCAL DEFAULT 4 "@D"

2
gas/testsuite/gas/ia64/dependency-1.d
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@ -11,7 +11,7 @@
Disassembly of section \.text:
0000000000000000 <foo>:
0+000 <foo>:
0:.*0b 40 00 40 10 18.*\[MMI\].*ldfs f8=\[r32\];;
6:.*00 40 84 30 33 00.*stfd \[r33\]=f8
c:.*00 00 04 00.*nop\.i 0x0;;

2
gas/testsuite/gas/ia64/dv-branch.d
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@ -6,7 +6,7 @@
Disassembly of section \.text:
0000000000000000 <\.text>:
0+000 <\.text>:
0: d0 08 00 10 18 90 \[MIB\] \(p06\) ld8 r1=\[r8\]
6: 61 10 04 80 03 03 \(p06\) mov b6=r2
c: 68 00 80 10 \(p06\) br\.call\.sptk\.many b0=b6

2
gas/testsuite/gas/ia64/dv-imply.d
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@ -6,7 +6,7 @@
Disassembly of section \.text:
0000000000000000 <L-0xc0>:
0+000 <L-0xc0>:
0: 3c 20 08 00 00 21 \[MFB\] \(p01\) mov r4=2
6: 00 00 00 02 00 01 nop\.f 0x0
c: c0 00 00 40 \(p02\) br\.cond\.sptk\.few c0 <L>

2
gas/testsuite/gas/ia64/dv-mutex.d
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@ -6,7 +6,7 @@
Disassembly of section \.text:
0000000000000000 <start>:
0+000 <start>:
0: 20 20 08 00 00 a1 \[MII\] \(p01\) mov r4=2
6: 40 28 00 00 c2 81 \(p02\) mov r4=5
c: 70 00 00 84 \(p03\) mov r4=7

2
gas/testsuite/gas/ia64/dv-safe.d
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@ -6,7 +6,7 @@
Disassembly of section \.text:
0000000000000000 <start>:
0+000 <start>:
0: 02 08 04 04 02 38 \[MII\] cmp\.eq p1,p2=r1,r2
6: 30 18 10 08 70 00 cmp\.eq p3,p4=r3,r4;;
c: 00 00 04 00 nop\.i 0x0

2
gas/testsuite/gas/ia64/dv-srlz.d
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@ -6,7 +6,7 @@
Disassembly of section \.text:
0000000000000000 <start>:
0+000 <start>:
0: 0a 00 00 02 34 04 \[MMI\] ptc\.e r1;;
6: 00 00 00 60 00 00 srlz\.d
c: 00 00 04 00 nop\.i 0x0

2
gas/testsuite/gas/ia64/global.d
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@ -2,7 +2,7 @@
#name: ia64 global label
Symbol table '.symtab' contains 5 entries:
Num: Value Size Type Bind Vis Ndx Name
Num:[ ]+Value[ ]+Size[ ]+Type[ ]+Bind[ ]+Vis[ ]+Ndx[ ]+Name
0: 0+0 0 NOTYPE LOCAL DEFAULT UND
1: 0+0 0 SECTION LOCAL DEFAULT 1
2: 0+0 0 SECTION LOCAL DEFAULT 2

12
gas/testsuite/gas/ia64/ia64.exp
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@ -46,7 +46,13 @@ if [istarget "ia64-*"] then {
run_dump_test "align"
run_dump_test "order"
run_dump_test "global"
run_dump_test "secname"
run_dump_test "unwind"
run_dump_test "alias"
if [istarget "ia64-*-hpux*"] then {
run_dump_test "secname-ilp32"
run_dump_test "unwind-ilp32"
run_dump_test "alias-ilp32"
} else {
run_dump_test "secname"
run_dump_test "unwind"
run_dump_test "alias"
}
}

4
gas/testsuite/gas/ia64/ldxmov-1.d
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@ -1,11 +1,11 @@
#objdump: -dr
#name: ia64 ldxmov-1
.*: file format elf64-ia64-little
.*: +file format .*
Disassembly of section \.text:
0*0000000 <\.text>:
0+000 <\.text>:
0: 18 10 00 06 18 10 \[MMB\] ld8 r2=\[r3\]
0: LDXMOV foo
1: LDXMOV \.data

4
gas/testsuite/gas/ia64/ltoff22x-1.d
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@ -4,7 +4,7 @@
.*: +file format .*
RELOCATION RECORDS FOR \[\.text\]:
OFFSET TYPE VALUE
0000000000000000 LTOFF22X foo
OFFSET[ ]+TYPE[ ]+VALUE
0+000 LTOFF22X foo

2
gas/testsuite/gas/ia64/opc-a.d
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@ -5,7 +5,7 @@
Disassembly of section \.text:
0000000000000000 <_start>:
0+000 <_start>:
0: 00 28 9b cf 00 60 \[MII\] add r101=r102,r103
6: 80 4e ab 01 40 60 \(p01\) add r104=r105,r106
c: cd 6e 07 80 add r107=r108,r109,1

2
gas/testsuite/gas/ia64/opc-b.d
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@ -5,7 +5,7 @@
Disassembly of section .text:
0000000000000000 <.text>:
0+000 <.text>:
0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0
6: 00 f8 15 00 20 00 \(p02\) br\.cond\.sptk\.few 0x2bf0
c: 00 00 00 40 br\.few 0x0;;

2
gas/testsuite/gas/ia64/opc-f.d
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@ -5,7 +5,7 @@
Disassembly of section \.text:
0000000000000000 <_start>:
0+000 <_start>:
0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0
6: 40 38 14 0c 40 00 fma\.s0 f4=f5,f6,f7
c: 00 00 00 20 nop\.b 0x0

2
gas/testsuite/gas/ia64/opc-i.d
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@ -5,7 +5,7 @@
Disassembly of section \.text:
0000000000000000 <_start>:
0+000 <_start>:
0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
6: 40 28 18 8c 38 80 pmpyshr2 r4=r5,r6,0
c: 50 30 68 71 pmpyshr2\.u r4=r5,r6,16

2
gas/testsuite/gas/ia64/opc-m.d
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@ -5,7 +5,7 @@
Disassembly of section \.text:
0000000000000000 <_start>:
0+000 <_start>:
0: 18 20 00 0a 00 10 \[MMB\] ld1 r4=\[r5\]
6: 40 30 14 00 24 00 ld1 r4=\[r5\],r6
c: 00 00 00 20 nop\.b 0x0

2
gas/testsuite/gas/ia64/opc-x.d
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@ -5,7 +5,7 @@
Disassembly of section .text:
0000000000000000 <_start>:
0+000 <_start>:
0: 04 00 00 00 01 00 \[MLX\] nop\.m 0x0
6: 00 00 00 00 00 00 break\.x 0x0
c: 00 00 00 00

20
gas/testsuite/gas/ia64/order.d
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@ -4,19 +4,19 @@
.*: +file format .*
RELOCATION RECORDS FOR \[.foo\]:
OFFSET TYPE VALUE
0000000000000008 DIR64MSB foo
0000000000000018 DIR64MSB foo
0000000000000028 DIR64LSB foo
0000000000000038 DIR64LSB foo
OFFSET[ ]+TYPE[ ]+VALUE
0+00008 DIR64MSB foo
0+00018 DIR64MSB foo
0+00028 DIR64LSB foo
0+00038 DIR64LSB foo
RELOCATION RECORDS FOR \[.bar\]:
OFFSET TYPE VALUE
0000000000000010 DIR64LSB foo
0000000000000040 DIR64LSB foo
0000000000000058 DIR64MSB foo
0000000000000080 DIR64MSB foo
OFFSET[ ]+TYPE[ ]+VALUE
0+00010 DIR64LSB foo
0+00040 DIR64LSB foo
0+00058 DIR64MSB foo
0+00080 DIR64MSB foo
Contents of section .foo:

2
gas/testsuite/gas/ia64/regs.d
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@ -5,7 +5,7 @@
Disassembly of section \.text:
0000000000000000 <_start>:
0+000 <_start>:
0: 01 08 00 00 00 21 \[MII\] mov r1=r0
6: 00 00 00 02 00 00 nop\.i 0x0
c: 00 00 04 00 nop\.i 0x0;;

21
gas/testsuite/gas/ia64/secname-ilp32.d Normal file
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@ -0,0 +1,21 @@
#readelf: -S
#name: ia64 section name (ilp32)
#as: -milp32
#source: secname.s
There are 8 section headers, starting at offset 0x7c:
Section Headers:
\[Nr\] Name Type Addr Off Size ES Flg Lk Inf Al
\[ 0\] NULL 00000000 000000 000000 00 0 0 0
\[ 1\] .text PROGBITS 00000000 000040 000000 00 AX 0 0 16
\[ 2\] .data PROGBITS 00000000 000040 000000 00 WA 0 0 1
\[ 3\] .bss NOBITS 00000000 000040 000000 00 WA 0 0 1
\[ 4\] .foo PROGBITS 00000000 000040 000008 00 WA 0 0 8
\[ 5\] .shstrtab STRTAB 00000000 000048 000031 00 0 0 1
\[ 6\] .symtab SYMTAB 00000000 0001bc 000050 10 7 5 4
\[ 7\] .strtab STRTAB 00000000 00020c 000001 00 0 0 1
Key to Flags:
W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
I \(info\), L \(link order\), G \(group\), x \(unknown\)
O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)

2
gas/testsuite/gas/ia64/tls.d
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@ -5,7 +5,7 @@
Disassembly of section \.text:
0000000000000000 <foo>:
0+000 <foo>:
0: 0d 20 21 0a 80 05 \[MFI\] alloc r36=ar\.pfs,8,5,0
2: LTOFF_TPREL22 x
6: 00 00 00 02 00 00 nop\.f 0x0

22
gas/testsuite/gas/ia64/unwind-ilp32.d Normal file
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@ -0,0 +1,22 @@
#readelf: -S
#name: ia64 unwind section (ilp32)
#as: -milp32
#source: unwind.s
There are 9 section headers, starting at offset 0xa0:
Section Headers:
\[Nr\] Name Type Addr Off Size ES Flg Lk Inf Al
\[ 0\] NULL 00000000 000000 000000 00 0 0 0
\[ 1\] .text PROGBITS 00000000 000040 000000 00 AX 0 0 16
\[ 2\] .data PROGBITS 00000000 000040 000000 00 WA 0 0 1
\[ 3\] .bss NOBITS 00000000 000040 000000 00 WA 0 0 1
\[ 4\] .IA_64.unwind_inf PROGBITS 00000000 000040 000008 00 A 0 0 8
\[ 5\] .IA_64.unwind IA_64_UNWIND 00000000 000048 000008 00 AL 1 1 8
\[ 6\] .shstrtab STRTAB 00000000 000050 00004d 00 0 0 1
\[ 7\] .symtab SYMTAB 00000000 000208 000060 10 8 6 4
\[ 8\] .strtab STRTAB 00000000 000268 000001 00 0 0 1
Key to Flags:
W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
I \(info\), L \(link order\), G \(group\), x \(unknown\)
O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)