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ppc: enable msgclr and msgsnd on Power8

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According to my reading of the spec it was an oversight for them to
not having got enabled when Power8 support got added.
This commit is contained in:
Jan Beulich 2014-10-21 09:56:38 +02:00 committed by Jan Beulich
parent 28f013d5cb
commit 12e87fac5c
5 changed files with 15 additions and 2 deletions
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5
gas/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2014-10-21 Jan Beulich <jbeulich@suse.com>
* gas/ppc/power8.s: Test msgclr and msgsnd.
* gas/ppc/power8.d: Adjust accordingly.
2014-10-18 Alan Modra <amodra@gmail.com>
* gas/i386/inval-equ-2.l: Adjust.

2
gas/testsuite/gas/ppc/power8.d
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@ -150,4 +150,6 @@ Disassembly of section \.text:
230: (f3 60 d5 2d|2d d5 60 f3) xscvspdpn vs59,vs26
234: (ff 0e 16 8c|8c 16 0e ff) fmrgow f24,f14,f2
238: (fe c7 2f 8c|8c 2f c7 fe) fmrgew f22,f7,f5
23c: (7c 00 71 9c|9c 71 00 7c) msgsnd r14
240: (7c 00 b9 dc|dc b9 00 7c) msgclr r23
#pass

2
gas/testsuite/gas/ppc/power8.s
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@ -142,3 +142,5 @@ power8:
xscvspdpn 59,26
fmrgow 24,14,2
fmrgew 22,7,5
msgsnd 14
msgclr 23

4
opcodes/ChangeLog
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@ -1,3 +1,7 @@
2014-10-21 Jan Beulich <jbeulich@suse.com>
* ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap

4
opcodes/ppc-opc.c
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@ -4653,7 +4653,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}},
{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}},
{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
@ -4700,7 +4700,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}},
{"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}},
{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},