From 13c02f06ff791ad9a09b562b141f07d9cefd52f8 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sun, 13 Feb 2011 18:55:22 +0000 Subject: [PATCH] opcodes: blackfin: fix decoding of ABS The single cycle dual mac ABS insn was incorrectly decoding the mac1 part of the insn. Once we fix the decode, update the gas tests to have the correct output. Signed-off-by: Mike Frysinger --- gas/testsuite/ChangeLog | 4 ++++ gas/testsuite/gas/bfin/arithmetic.d | 2 +- gas/testsuite/gas/bfin/parallel.d | 2 +- opcodes/ChangeLog | 4 ++++ opcodes/bfin-dis.c | 2 +- 5 files changed, 11 insertions(+), 3 deletions(-) diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index fb8816d1ef..50c23da540 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2011-02-13 Mike Frysinger + + * gas/bfin/arithmetic.d, gas/bfin/parallel.d: Change A0 to A1. + 2011-02-13 Mike Frysinger * gas/bfin/arithmetic.d, gas/bfin/parallel.d, gas/bfin/parallel3.d, diff --git a/gas/testsuite/gas/bfin/arithmetic.d b/gas/testsuite/gas/bfin/arithmetic.d index 0f145e0100..2cbdb71fa4 100644 --- a/gas/testsuite/gas/bfin/arithmetic.d +++ b/gas/testsuite/gas/bfin/arithmetic.d @@ -10,7 +10,7 @@ Disassembly of section .text: 4: 10 c4 [0-3][[:xdigit:]] 40 A0 = ABS A1; 8: 30 c4 [0-3][[:xdigit:]] 00 A1 = ABS A0; c: 30 c4 [0-3][[:xdigit:]] 40 A1 = ABS A1; - 10: 10 c4 [0-3][[:xdigit:]] c0 A1 = ABS A0, A0 = ABS A0; + 10: 10 c4 [0-3][[:xdigit:]] c0 A1 = ABS A1, A0 = ABS A0; 14: 07 c4 10 80 R0 = ABS R2; 00000018 : diff --git a/gas/testsuite/gas/bfin/parallel.d b/gas/testsuite/gas/bfin/parallel.d index db4c8fe991..bd4269cde7 100644 --- a/gas/testsuite/gas/bfin/parallel.d +++ b/gas/testsuite/gas/bfin/parallel.d @@ -37,7 +37,7 @@ Disassembly of section .text: 74: fc b9 0a 9c 78: 30 cc 00 40 A1 = ABS A1 \|\| FP = \[SP\] \|\| R3 = \[I2--\]; 7c: 77 91 93 9c - 80: 10 cc 00 c0 A1 = ABS A0, A0 = ABS A0 \|\| R4 = \[P5 \+ 0x38\] \|\| R0.H = W\[I0\]; + 80: 10 cc 00 c0 A1 = ABS A1, A0 = ABS A0 \|\| R4 = \[P5 \+ 0x38\] \|\| R0.H = W\[I0\]; 84: ac a3 40 9d 88: 07 cc 10 80 R0 = ABS R2 \|\| B\[SP\] = R0 \|\| R1.H = W\[I1\+\+\]; 8c: 30 9b 49 9c diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f0671504e7..364e7c23e3 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2011-02-13 Mike Frysinger + + * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg. + 2011-02-13 Mike Frysinger * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output diff --git a/opcodes/bfin-dis.c b/opcodes/bfin-dis.c index e7646c9ea9..393276273e 100644 --- a/opcodes/bfin-dis.c +++ b/opcodes/bfin-dis.c @@ -3476,7 +3476,7 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf) OUTS (outf, " = (A0 += A1)"); } else if (aop == 3 && HL == 0 && aopcde == 16) - OUTS (outf, "A1 = ABS A0, A0 = ABS A0"); + OUTS (outf, "A1 = ABS A1, A0 = ABS A0"); else if (aop == 0 && aopcde == 23 && HL == 1) {