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https://github.com/darlinghq/darling-gdb.git
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Always compile FP code (test for FP at run-time).
Remove dependance of interp.c on gencode.c's output.
This commit is contained in:
Andrew Cagney
parent
fcb12def35
commit
192ae475f9
@ -1,3 +1,15 @@
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Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (oengine.h): Do not include when building with IGEN.
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(sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
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(sim_info): Ditto for PROCESSOR_64BIT.
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(sim_monitor): Replace ut_reg with unsigned_word.
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(*): Ditto for t_reg.
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(LOADDRMASK): Define.
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(sim_open): Remove defunct check that host FP is IEEE compliant,
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using software to emulate floating point.
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(value_fpr, ...): Always compile, was conditional on HASFPU.
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Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
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@ -75,9 +75,13 @@ char* pr_uword64 PARAMS ((uword64 addr));
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/* Get the simulator engine description, without including the code: */
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#if (WITH_IGEN)
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#define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3)
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#else
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#define SIM_MANIFESTS
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#include "oengine.c"
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#undef SIM_MANIFESTS
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#endif
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/* Within interp.c we refer to the sim_state and sim_cpu directly. */
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#define SD sd
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@ -331,45 +335,17 @@ sim_open (kind, cb, abfd, argv)
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SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
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SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
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#if defined(HASFPU)
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/* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
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and DOUBLE binary formats. This is a bit nasty, requiring that we
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trust the explicit manifests held in the source: */
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/* TODO: We need to cope with the simulated target and the host not
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having the same endianness. This will require the high and low
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words of a (double) to be swapped when converting between the
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host and the simulated target. */
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{
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union {
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unsigned int i[2];
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double d;
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float f[2];
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} s;
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s.d = (double)523.2939453125;
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if ((s.i[0] == 0 && (s.f[1] != (float)4.01102924346923828125
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|| s.i[1] != 0x40805A5A))
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|| (s.i[1] == 0 && (s.f[0] != (float)4.01102924346923828125
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|| s.i[0] != 0x40805A5A)))
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{
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fprintf(stderr,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
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return 0;
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}
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}
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#endif /* HASFPU */
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/* This is NASTY, in that we are assuming the size of specific
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registers: */
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{
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int rn;
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for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) {
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if (rn < 32)
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cpu->register_widths[rn] = GPRLEN;
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cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
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else if ((rn >= FGRIDX) && (rn < (FGRIDX + 32)))
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cpu->register_widths[rn] = GPRLEN;
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cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
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else if ((rn >= 33) && (rn <= 37))
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cpu->register_widths[rn] = GPRLEN;
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cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
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else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89)))
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cpu->register_widths[rn] = 32;
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else
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@ -627,7 +603,7 @@ sim_info (sd,verbose)
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{
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sim_io_printf (sd, "MIPS %d-bit %s endian simulator\n",
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(PROCESSOR_64BIT ? 64 : 32),
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WITH_TARGET_WORD_BITSIZE,
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(CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN ? "Big" : "Little"));
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#if !defined(FASTSIM)
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@ -788,7 +764,7 @@ sim_monitor (SIM_DESC sd,
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case 2: /* Densan monitor: char inbyte(int waitflag) */
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{
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if (A0 == 0) /* waitflag == NOWAIT */
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V0 = (ut_reg)-1;
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V0 = (unsigned_word)-1;
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}
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/* Drop through to case 11 */
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@ -798,10 +774,10 @@ sim_monitor (SIM_DESC sd,
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if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
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{
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sim_io_error(sd,"Invalid return from character read");
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V0 = (ut_reg)-1;
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V0 = (unsigned_word)-1;
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}
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else
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V0 = (ut_reg)tmp;
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V0 = (unsigned_word)tmp;
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break;
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}
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@ -967,7 +943,7 @@ store_word (SIM_DESC sd,
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sim_cpu *cpu,
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address_word cia,
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uword64 vaddr,
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t_reg val)
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signed_word val)
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{
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address_word paddr;
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int uncached;
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@ -994,7 +970,7 @@ store_word (SIM_DESC sd,
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/* Load a word from memory. */
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static t_reg
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static signed_word
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load_word (SIM_DESC sd,
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sim_cpu *cpu,
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address_word cia,
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@ -1054,7 +1030,7 @@ mips16_entry (SIM_DESC sd,
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if (aregs < 5)
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{
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int i;
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t_reg tsp;
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signed_word tsp;
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/* This is the entry pseudo-instruction. */
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@ -1079,7 +1055,7 @@ mips16_entry (SIM_DESC sd,
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else
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{
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int i;
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t_reg tsp;
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signed_word tsp;
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/* This is the exit pseudo-instruction. */
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@ -1099,23 +1075,25 @@ mips16_entry (SIM_DESC sd,
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SP += 32;
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#if defined(HASFPU)
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if (aregs == 5)
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if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
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{
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FGR[0] = WORD64LO (GPR[4]);
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FPR_STATE[0] = fmt_uninterpreted;
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}
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else if (aregs == 6)
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{
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FGR[0] = WORD64LO (GPR[5]);
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FGR[1] = WORD64LO (GPR[4]);
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FPR_STATE[0] = fmt_uninterpreted;
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FPR_STATE[1] = fmt_uninterpreted;
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}
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#endif /* defined(HASFPU) */
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if (aregs == 5)
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{
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FGR[0] = WORD64LO (GPR[4]);
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FPR_STATE[0] = fmt_uninterpreted;
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}
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else if (aregs == 6)
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{
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FGR[0] = WORD64LO (GPR[5]);
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FGR[1] = WORD64LO (GPR[4]);
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FPR_STATE[0] = fmt_uninterpreted;
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FPR_STATE[1] = fmt_uninterpreted;
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}
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}
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PC = RA;
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}
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}
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/*-- trace support ----------------------------------------------------------*/
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@ -1926,8 +1904,6 @@ cache_op (SIM_DESC sd,
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/*-- FPU support routines ---------------------------------------------------*/
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#if defined(HASFPU) /* Only needed when building FPU aware simulators */
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/* Numbers are held in normalized form. The SINGLE and DOUBLE binary
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formats conform to ANSI/IEEE Std 754-1985. */
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/* SINGLE precision floating:
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@ -2846,7 +2822,6 @@ convert (SIM_DESC sd,
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return(result64);
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}
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#endif /* HASFPU */
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/*-- co-processor support routines ------------------------------------------*/
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@ -2867,23 +2842,25 @@ cop_lw (SIM_DESC sd,
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int coproc_reg,
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unsigned int memword)
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{
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switch (coproc_num) {
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#if defined(HASFPU)
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switch (coproc_num)
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{
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case 1:
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if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
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{
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#ifdef DEBUG
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printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
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printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
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#endif
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StoreFPR(coproc_reg,fmt_word,(uword64)memword);
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FPR_STATE[coproc_reg] = fmt_uninterpreted;
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break;
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#endif /* HASFPU */
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StoreFPR(coproc_reg,fmt_word,(uword64)memword);
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FPR_STATE[coproc_reg] = fmt_uninterpreted;
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break;
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}
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default:
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#if 0 /* this should be controlled by a configuration option */
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sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
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sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
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#endif
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break;
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}
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break;
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}
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return;
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}
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@ -2897,11 +2874,12 @@ cop_ld (SIM_DESC sd,
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uword64 memword)
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{
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switch (coproc_num) {
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#if defined(HASFPU)
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case 1:
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StoreFPR(coproc_reg,fmt_uninterpreted,memword);
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break;
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#endif /* HASFPU */
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if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
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{
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StoreFPR(coproc_reg,fmt_uninterpreted,memword);
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break;
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}
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default:
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#if 0 /* this message should be controlled by a configuration option */
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@ -2922,36 +2900,25 @@ cop_sw (SIM_DESC sd,
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{
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unsigned int value = 0;
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switch (coproc_num) {
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#if defined(HASFPU)
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switch (coproc_num)
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{
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case 1:
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#if 1
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{
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FP_formats hold;
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hold = FPR_STATE[coproc_reg];
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FPR_STATE[coproc_reg] = fmt_word;
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value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
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FPR_STATE[coproc_reg] = hold;
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}
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#else
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#if 1
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value = (unsigned int)ValueFPR(coproc_reg,FPR_STATE[coproc_reg]);
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#else
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#ifdef DEBUG
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printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(FPR_STATE[coproc_reg]));
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#endif /* DEBUG */
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value = (unsigned int)ValueFPR(coproc_reg,fmt_single);
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#endif
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#endif
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break;
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#endif /* HASFPU */
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if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
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{
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FP_formats hold;
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hold = FPR_STATE[coproc_reg];
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FPR_STATE[coproc_reg] = fmt_word;
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value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
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FPR_STATE[coproc_reg] = hold;
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break;
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}
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default:
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#if 0 /* should be controlled by configuration option */
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sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
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sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
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#endif
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break;
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}
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break;
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}
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return(value);
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}
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@ -2964,30 +2931,21 @@ cop_sd (SIM_DESC sd,
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int coproc_reg)
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{
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uword64 value = 0;
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switch (coproc_num) {
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#if defined(HASFPU)
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switch (coproc_num)
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{
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case 1:
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#if 1
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value = ValueFPR(coproc_reg,fmt_uninterpreted);
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#else
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#if 1
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value = ValueFPR(coproc_reg,FPR_STATE[coproc_reg]);
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#else
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#ifdef DEBUG
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printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(FPR_STATE[coproc_reg]));
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#endif /* DEBUG */
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value = ValueFPR(coproc_reg,fmt_double);
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#endif
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#endif
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break;
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#endif /* HASFPU */
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if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
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{
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value = ValueFPR(coproc_reg,fmt_uninterpreted);
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break;
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}
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default:
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#if 0 /* should be controlled by configuration option */
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sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
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sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
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#endif
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break;
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}
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break;
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}
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return(value);
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}
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@ -3376,22 +3334,25 @@ sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
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printf("pending_slot_reg[%d] = %d\n",index,PENDING_SLOT_REG[index]);
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printf("pending_slot_value[%d] = 0x%s\n",index,pr_addr(PENDING_SLOT_VALUE[index]));
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#endif /* DEBUG */
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if (PENDING_SLOT_REG[index] == COCIDX) {
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#if defined(HASFPU)
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SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
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#else
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;
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#endif
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} else {
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REGISTERS[PENDING_SLOT_REG[index]] = PENDING_SLOT_VALUE[index];
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#if defined(HASFPU)
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/* The only time we have PENDING updates to FPU
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registers, is when performing binary transfers. This
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means we should update the register type field. */
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if ((PENDING_SLOT_REG[index] >= FGRIDX) && (PENDING_SLOT_REG[index] < (FGRIDX + 32)))
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FPR_STATE[PENDING_SLOT_REG[index] - FGRIDX] = fmt_uninterpreted;
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#endif /* HASFPU */
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}
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if (PENDING_SLOT_REG[index] == COCIDX)
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{
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if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
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{
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SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
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}
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}
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else
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{
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REGISTERS[PENDING_SLOT_REG[index]] = PENDING_SLOT_VALUE[index];
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if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
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{
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/* The only time we have PENDING updates to FPU
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registers, is when performing binary transfers. This
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means we should update the register type field. */
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if ((PENDING_SLOT_REG[index] >= FGRIDX) && (PENDING_SLOT_REG[index] < (FGRIDX + 32)))
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FPR_STATE[PENDING_SLOT_REG[index] - FGRIDX] = fmt_uninterpreted;
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}
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}
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#ifdef DEBUG
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printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG[index],pr_addr(REGISTERS[PENDING_SLOT_REG[index]]));
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#endif /* DEBUG */
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