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2008-11-04 Sterling Augustine <sterling@tensilica.com>
* config/tc-xtensa.c (xtensa_j_opcode): New. (xg_instruction_matches_option_term): Handle "FREEREG" option. (xg_build_to_insn): Likewise. Update renamed tls_reloc reference. (md_begin): Initialize xtensa_j_opcode. (md_assemble): Update renamed tls_reloc reference. Handle "j.l". (xg_assemble_vliw_tokens): Save free_reg info in the frag. (tinsn_immed_from_frag): Get free_reg info back out of the frag. (vinsn_to_insnbuf): Update renamed tls_reloc references. Distinguish extra argument for "FREEREG" from extra TLS argument. * config/tc-xtensa.h (struct xtensa_frag_type): Add free_reg field. * config/xtensa-istack.h (struct tinsn_struct): Rename tls_reloc field to extra_arg. * config/xtensa-relax.c (widen_spec_list): Add rules to relax "j.l". (build_transition): Handle "FREEREG" operand. * config/xtensa-relax.h (enum op_type): Add OP_FREEREG. 2008-11-04 Bob Wilson <bob.wilson@acm.org> * gas/xtensa/all.exp: Run jlong test. * gas/xtensa/jlong.d: New. * gas/xtensa/jlong.s: New.
This commit is contained in:
Bob Wilson
parent
d3fd534293
commit
19e8f41aa4
@ -1,3 +1,21 @@
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2008-11-04 Sterling Augustine <sterling@tensilica.com>
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* config/tc-xtensa.c (xtensa_j_opcode): New.
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(xg_instruction_matches_option_term): Handle "FREEREG" option.
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(xg_build_to_insn): Likewise. Update renamed tls_reloc reference.
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(md_begin): Initialize xtensa_j_opcode.
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(md_assemble): Update renamed tls_reloc reference. Handle "j.l".
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(xg_assemble_vliw_tokens): Save free_reg info in the frag.
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(tinsn_immed_from_frag): Get free_reg info back out of the frag.
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(vinsn_to_insnbuf): Update renamed tls_reloc references.
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Distinguish extra argument for "FREEREG" from extra TLS argument.
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* config/tc-xtensa.h (struct xtensa_frag_type): Add free_reg field.
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* config/xtensa-istack.h (struct tinsn_struct): Rename tls_reloc
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field to extra_arg.
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* config/xtensa-relax.c (widen_spec_list): Add rules to relax "j.l".
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(build_transition): Handle "FREEREG" operand.
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* config/xtensa-relax.h (enum op_type): Add OP_FREEREG.
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2008-10-31 Alan Modra <amodra@bigpond.net.au>
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* po/id.po: Update.
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@ -571,6 +571,7 @@ static xtensa_opcode xtensa_extui_opcode;
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static xtensa_opcode xtensa_movi_opcode;
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static xtensa_opcode xtensa_movi_n_opcode;
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static xtensa_opcode xtensa_isync_opcode;
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static xtensa_opcode xtensa_j_opcode;
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static xtensa_opcode xtensa_jx_opcode;
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static xtensa_opcode xtensa_l32r_opcode;
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static xtensa_opcode xtensa_loop_opcode;
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@ -2730,13 +2731,10 @@ xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf,
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/* The routine xg_instruction_matches_option_term must return TRUE
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when a given option term is true. The meaning of all of the option
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terms is given interpretation by this function. This is needed when
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an option depends on the state of a directive, but there are no such
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options in use right now. */
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terms is given interpretation by this function. */
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static bfd_boolean
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xg_instruction_matches_option_term (TInsn *insn ATTRIBUTE_UNUSED,
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const ReqOrOption *option)
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xg_instruction_matches_option_term (TInsn *insn, const ReqOrOption *option)
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{
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if (strcmp (option->option_name, "realnop") == 0
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|| strncmp (option->option_name, "IsaUse", 6) == 0)
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@ -2745,6 +2743,8 @@ xg_instruction_matches_option_term (TInsn *insn ATTRIBUTE_UNUSED,
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relaxation table. There's no need to reevaluate them now. */
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return TRUE;
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}
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else if (strcmp (option->option_name, "FREEREG") == 0)
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return insn->extra_arg.X_op == O_register;
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else
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{
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as_fatal (_("internal error: unknown option name '%s'"),
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@ -3370,12 +3370,17 @@ xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi)
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assert (op_data < insn->ntok);
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copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
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break;
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case OP_FREEREG:
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if (insn->extra_arg.X_op != O_register)
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return FALSE;
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copy_expr (&targ->tok[op_num], &insn->extra_arg);
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break;
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case OP_LITERAL:
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sym = get_special_literal_symbol ();
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set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
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if (insn->tok[op_data].X_op == O_tlsfunc
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|| insn->tok[op_data].X_op == O_tlsarg)
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copy_expr (&targ->tls_reloc, &insn->tok[op_data]);
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copy_expr (&targ->extra_arg, &insn->tok[op_data]);
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break;
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case OP_LABEL:
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sym = get_special_label_symbol ();
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@ -5103,6 +5108,7 @@ md_begin (void)
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xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi");
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xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n");
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xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync");
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xtensa_j_opcode = xtensa_opcode_lookup (isa, "j");
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xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx");
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xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r");
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xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop");
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@ -5375,7 +5381,7 @@ md_assemble (char *str)
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{
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bfd_reloc_code_real_type reloc;
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char *old_input_line_pointer;
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expressionS *tok = &orig_insn.tls_reloc;
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expressionS *tok = &orig_insn.extra_arg;
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segT t;
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old_input_line_pointer = input_line_pointer;
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@ -5395,6 +5401,28 @@ md_assemble (char *str)
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}
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}
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/* Special case: Check for "j.l" psuedo op. */
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if (orig_insn.opcode == XTENSA_UNDEFINED
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&& strncasecmp (opname, "j.l", 3) == 0)
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{
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if (num_args != 2)
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as_bad (_("wrong number of operands for '%s'"), opname);
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else
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{
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char *old_input_line_pointer;
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expressionS *tok = &orig_insn.extra_arg;
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old_input_line_pointer = input_line_pointer;
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input_line_pointer = arg_strings[num_args - 1];
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expression_maybe_register (xtensa_jx_opcode, 0, tok);
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input_line_pointer = old_input_line_pointer;
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num_args -= 1;
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orig_insn.opcode = xtensa_j_opcode;
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}
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}
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if (orig_insn.opcode == XTENSA_UNDEFINED)
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{
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xtensa_format fmt = xtensa_format_lookup (isa, opname);
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@ -6996,6 +7024,7 @@ xg_assemble_vliw_tokens (vliw_insn *vinsn)
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frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag;
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if (tinsn->literal_space != 0)
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xg_assemble_literal_space (tinsn->literal_space, slot);
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frag_now->tc_frag_data.free_reg[slot] = tinsn->extra_arg;
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if (tinsn->subtype == RELAX_NARROW)
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assert (vinsn->num_slots == 1);
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@ -11505,6 +11534,7 @@ tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot)
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fragP->tc_frag_data.slot_symbols[slot],
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fragP->tc_frag_data.slot_offsets[slot]);
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}
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tinsn->extra_arg = fragP->tc_frag_data.free_reg[slot];
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}
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@ -11626,14 +11656,14 @@ vinsn_to_insnbuf (vliw_insn *vinsn,
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for (slot = 0; slot < vinsn->num_slots; slot++)
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{
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TInsn *tinsn = &vinsn->slots[slot];
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expressionS *tls_reloc = &tinsn->tls_reloc;
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expressionS *extra_arg = &tinsn->extra_arg;
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bfd_boolean tinsn_has_fixup =
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tinsn_to_slotbuf (vinsn->format, slot, tinsn,
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vinsn->slotbuf[slot]);
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xtensa_format_set_slot (isa, fmt, slot,
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insnbuf, vinsn->slotbuf[slot]);
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if (tls_reloc->X_op != O_illegal)
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if (extra_arg->X_op != O_illegal && extra_arg->X_op != O_register)
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{
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if (vinsn->num_slots != 1)
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as_bad (_("TLS relocation not allowed in FLIX bundle"));
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@ -11646,8 +11676,8 @@ vinsn_to_insnbuf (vliw_insn *vinsn,
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else
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fix_new (fragP, frag_offset - fragP->fr_literal,
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xtensa_format_length (isa, fmt),
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tls_reloc->X_add_symbol, tls_reloc->X_add_number,
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FALSE, map_operator_to_reloc (tls_reloc->X_op, FALSE));
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extra_arg->X_add_symbol, extra_arg->X_add_number,
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FALSE, map_operator_to_reloc (extra_arg->X_op, FALSE));
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}
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if (tinsn_has_fixup)
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{
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@ -253,6 +253,10 @@ struct xtensa_frag_type
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int literal_expansion[MAX_SLOTS];
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int unreported_expansion;
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/* For slots that have a free register for relaxation, record that
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register. */
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expressionS free_reg[MAX_SLOTS];
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/* For text fragments that can generate literals at relax time: */
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fragS *literal_frags[MAX_SLOTS];
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enum xtensa_relax_statesE slot_subtypes[MAX_SLOTS];
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@ -49,11 +49,19 @@ typedef struct tinsn_struct
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bfd_boolean loc_directive_seen;
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struct dwarf2_line_info debug_line;
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expressionS tls_reloc;
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/* This field is used for two types of special pseudo ops:
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1. TLS-related operations. Eg: callx8.tls
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2. j.l label, a2
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For the tls-related operations, it will hold a tls-related opcode
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and info to be used in a fixup. For j.l it will hold a
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register to be used during relaxation. */
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expressionS extra_arg;
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/* Filled out by relaxation_requirements: */
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enum xtensa_relax_statesE subtype;
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int literal_space;
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/* Filled out by vinsn_to_insnbuf: */
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symbolS *symbol;
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offsetT offset;
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@ -463,7 +463,14 @@ static string_pattern_pair widen_spec_list[] =
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{"call8 %label,%ar8 ? IsaUseConst16",
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"const16 a8,HI16U(%label); const16 a8,LOW16U(%label); callx8 a8,%ar8"},
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{"call12 %label,%ar12 ? IsaUseConst16",
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"const16 a12,HI16U(%label); const16 a12,LOW16U(%label); callx12 a12,%ar12"}
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"const16 a12,HI16U(%label); const16 a12,LOW16U(%label); callx12 a12,%ar12"},
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/* Expanding j.l with literals. */
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{"j %label ? FREEREG ? IsaUseL32R",
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"LITERAL %label; l32r FREEREG,%LITERAL; jx FREEREG"},
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/* Expanding j.l with const16. */
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{"j %label ? FREEREG ? IsaUseConst16",
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"const16 FREEREG,HI16U(%label); const16 FREEREG,LOW16U(%label); jx FREEREG"},
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};
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#define WIDEN_COUNT (sizeof (widen_spec_list) / sizeof (string_pattern_pair))
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@ -1793,6 +1800,10 @@ build_transition (insn_pattern *initial_insn,
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opcode_name, op->operand_name, to_string);
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append_field_op (bi, op->operand_num, orig_op->operand_num);
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}
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else if (strcmp (op->operand_name, "FREEREG") == 0)
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{
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append_user_fn_field_op (bi, op->operand_num, OP_FREEREG, 0);
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}
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else if (parse_special_fn (op->operand_name,
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&fn_name, &operand_arg_name))
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{
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@ -105,6 +105,7 @@ enum op_type
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OP_OPERAND_LOW16U, /* Low 16 bits of immed. */
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OP_OPERAND_HI16U, /* High 16 bits of immed. */
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OP_LITERAL,
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OP_FREEREG,
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OP_LABEL
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};
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@ -1,3 +1,9 @@
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2008-11-04 Bob Wilson <bob.wilson@acm.org>
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* gas/xtensa/all.exp: Run jlong test.
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* gas/xtensa/jlong.d: New.
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* gas/xtensa/jlong.s: New.
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2008-11-03 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/intel.s: Add tests for cmovpe and cmovpo.
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@ -81,6 +81,7 @@ if [istarget xtensa*-*-*] then {
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run_dump_test "short_branch_offset"
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run_dump_test "pcrel"
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run_dump_test "weak-call"
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run_dump_test "jlong"
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}
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if [info exists errorInfo] then {
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18
gas/testsuite/gas/xtensa/jlong.d
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18
gas/testsuite/gas/xtensa/jlong.d
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@ -0,0 +1,18 @@
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#as:
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#objdump: -d -j .text.1 -j .text.2
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#name: long jump relaxation
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.*: +file format .*xtensa.*
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Disassembly of section \.text\.1:
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00000000 <\.text\.1>:
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# Skip instructions to load a8 since they will vary depending on whether
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# the Xtensa configuration uses L32R or Const16.
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#...
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.*: .* jx a8
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Disassembly of section \.text\.2:
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00000000 <\.text\.2>:
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0: .* j .*
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#...
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7
gas/testsuite/gas/xtensa/jlong.s
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7
gas/testsuite/gas/xtensa/jlong.s
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@ -0,0 +1,7 @@
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.section .text.1
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j.l .Lfar, a8
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.section .text.2
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.Lfar:
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j.l .Lnear, a9
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.word 0
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.Lnear:
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