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Add support for Score target.

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This commit is contained in:
Nick Clifton 2006-09-16 23:51:50 +00:00
parent 0112cd268b
commit 1c0d3aa6ae
54 changed files with 13014 additions and 55 deletions
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15
bfd/ChangeLog
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@ -1,3 +1,18 @@
2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
* cpu-score.c: New file.
* elf32-score.c: New file.
* config.bfd: Add Score target.
* Makefile.am: Add Score files.
* Makefile.in: Regenerate.
* archures.c: Add Score architecture.
* reloc.c: Add Score relocs.
* targets.c: Add Score target vectors.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* configure.in: Add Score target.
* configure: Regenerate.
2006-09-16 Nick Clifton <nickc@redhat.com>
Pedro Alves <pedro_alves@portugalmail.pt>

9
bfd/Makefile.am
View File

@ -103,6 +103,7 @@ ALL_MACHINES = \
cpu-powerpc.lo \
cpu-rs6000.lo \
cpu-s390.lo \
cpu-score.lo \
cpu-sh.lo \
cpu-sparc.lo \
cpu-tic30.lo \
@ -165,6 +166,7 @@ ALL_MACHINES_CFILES = \
cpu-powerpc.c \
cpu-rs6000.c \
cpu-s390.c \
cpu-score.c \
cpu-sh.c \
cpu-sparc.c \
cpu-tic30.c \
@ -271,6 +273,7 @@ BFD32_BACKENDS = \
elf32-pj.lo \
elf32-ppc.lo \
elf32-s390.lo \
elf32-score.lo \
elf32-sh.lo \
elf32-sh-symbian.lo \
elf32-sh64.lo \
@ -447,6 +450,7 @@ BFD32_BACKENDS_CFILES = \
elf32-sh64.c \
elf32-sh64-com.c \
elf32-s390.c \
elf32-score.c \
elf32-sh.c \
elf32-sh-symbian.c \
elfxx-sparc.c \
@ -1058,6 +1062,7 @@ cpu-pj.lo: cpu-pj.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
cpu-powerpc.lo: cpu-powerpc.c $(INCDIR)/filenames.h \
$(INCDIR)/hashtab.h
cpu-rs6000.lo: cpu-rs6000.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
cpu-score.lo: cpu-score.c $(INCDIR)/filenames.h
cpu-s390.lo: cpu-s390.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
cpu-sh.lo: cpu-sh.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
$(srcdir)/../opcodes/sh-opc.h
@ -1436,6 +1441,10 @@ elf32-sh64-com.lo: elf32-sh64-com.c $(INCDIR)/filenames.h \
$(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
$(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h elf32-sh64.h \
$(srcdir)/../opcodes/sh64-opc.h
elf32-score.lo: elf32-score.c $(INCDIR)/filenames.h \
elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h $(INCDIR)/elf/score.h \
$(INCDIR)/elf/reloc-macros.h elf32-target.h
elf32-s390.lo: elf32-s390.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
$(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
$(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/s390.h \

9
bfd/Makefile.in
View File

@ -334,6 +334,7 @@ ALL_MACHINES = \
cpu-powerpc.lo \
cpu-rs6000.lo \
cpu-s390.lo \
cpu-score.lo \
cpu-sh.lo \
cpu-sparc.lo \
cpu-tic30.lo \
@ -396,6 +397,7 @@ ALL_MACHINES_CFILES = \
cpu-powerpc.c \
cpu-rs6000.c \
cpu-s390.c \
cpu-score.c \
cpu-sh.c \
cpu-sparc.c \
cpu-tic30.c \
@ -503,6 +505,7 @@ BFD32_BACKENDS = \
elf32-pj.lo \
elf32-ppc.lo \
elf32-s390.lo \
elf32-score.lo \
elf32-sh.lo \
elf32-sh-symbian.lo \
elf32-sh64.lo \
@ -679,6 +682,7 @@ BFD32_BACKENDS_CFILES = \
elf32-sh64.c \
elf32-sh64-com.c \
elf32-s390.c \
elf32-score.c \
elf32-sh.c \
elf32-sh-symbian.c \
elfxx-sparc.c \
@ -1619,6 +1623,7 @@ cpu-pj.lo: cpu-pj.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
cpu-powerpc.lo: cpu-powerpc.c $(INCDIR)/filenames.h \
$(INCDIR)/hashtab.h
cpu-rs6000.lo: cpu-rs6000.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
cpu-score.lo: cpu-score.c $(INCDIR)/filenames.h
cpu-s390.lo: cpu-s390.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
cpu-sh.lo: cpu-sh.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
$(srcdir)/../opcodes/sh-opc.h
@ -1997,6 +2002,10 @@ elf32-sh64-com.lo: elf32-sh64-com.c $(INCDIR)/filenames.h \
$(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
$(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h elf32-sh64.h \
$(srcdir)/../opcodes/sh64-opc.h
elf32-score.lo: elf32-score.c $(INCDIR)/filenames.h \
elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h $(INCDIR)/elf/score.h \
$(INCDIR)/elf/reloc-macros.h elf32-target.h
elf32-s390.lo: elf32-s390.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
$(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
$(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/s390.h \

3
bfd/archures.c
View File

@ -348,6 +348,7 @@ DESCRIPTION
. bfd_arch_s390, {* IBM s390 *}
.#define bfd_mach_s390_31 31
.#define bfd_mach_s390_64 64
. bfd_arch_score, {* Sunplus score *}
. bfd_arch_openrisc, {* OpenRISC *}
. bfd_arch_mmix, {* Donald Knuth's educational processor. *}
. bfd_arch_xstormy16,
@ -466,6 +467,7 @@ extern const bfd_arch_info_type bfd_powerpc_archs[];
#define bfd_powerpc_arch bfd_powerpc_archs[0]
extern const bfd_arch_info_type bfd_rs6000_arch;
extern const bfd_arch_info_type bfd_s390_arch;
extern const bfd_arch_info_type bfd_score_arch;
extern const bfd_arch_info_type bfd_sh_arch;
extern const bfd_arch_info_type bfd_sparc_arch;
extern const bfd_arch_info_type bfd_tic30_arch;
@ -531,6 +533,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
&bfd_powerpc_arch,
&bfd_rs6000_arch,
&bfd_s390_arch,
&bfd_score_arch,
&bfd_sh_arch,
&bfd_sparc_arch,
&bfd_tic30_arch,

26
bfd/bfd-in2.h
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@ -1968,6 +1968,7 @@ enum bfd_architecture
bfd_arch_s390, /* IBM s390 */
#define bfd_mach_s390_31 31
#define bfd_mach_s390_64 64
bfd_arch_score, /* Sunplus score */
bfd_arch_openrisc, /* OpenRISC */
bfd_arch_mmix, /* Donald Knuth's educational processor. */
bfd_arch_xstormy16,
@ -3760,6 +3761,31 @@ instructions */
BFD_RELOC_390_GOTPLT20,
BFD_RELOC_390_TLS_GOTIE20,
/* Score relocations */
BFD_RELOC_SCORE_DUMMY1,
/* Low 16 bit for load/store */
BFD_RELOC_SCORE_GPREL15,
/* This is a 24-bit reloc with the right 1 bit assumed to be 0 */
BFD_RELOC_SCORE_DUMMY2,
BFD_RELOC_SCORE_JMP,
/* This is a 19-bit reloc with the right 1 bit assumed to be 0 */
BFD_RELOC_SCORE_BRANCH,
/* This is a 11-bit reloc with the right 1 bit assumed to be 0 */
BFD_RELOC_SCORE16_JMP,
/* This is a 8-bit reloc with the right 1 bit assumed to be 0 */
BFD_RELOC_SCORE16_BRANCH,
/* Undocumented Score relocs */
BFD_RELOC_SCORE_GOT15,
BFD_RELOC_SCORE_GOT_LO16,
BFD_RELOC_SCORE_CALL15,
BFD_RELOC_SCORE_DUMMY_HI16,
/* Scenix IP2K - 9-bit register number / data address */
BFD_RELOC_IP2K_FR9,

5
bfd/config.bfd
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@ -1143,6 +1143,11 @@ case "${targ}" in
;;
#endif
score*-*-elf*)
targ_defvec=bfd_elf32_bigscore_vec
targ_selvecs=bfd_elf32_littlescore_vec
;;
#ifdef BFD64
sh64l*-*-elf*)
targ_defvec=bfd_elf32_sh64l_vec

2
bfd/configure vendored
View File

@ -10873,6 +10873,8 @@ do
bfd_elf32_powerpcle_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
bfd_elf32_powerpc_vxworks_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
bfd_elf32_s390_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;;
bfd_elf32_bigscore_vec) tb="$tb elf32-score.lo elf32.lo $elf" ;;
bfd_elf32_littlescore_vec) tb="$tb elf32-score.lo elf32.lo $elf" ;;
# FIXME: We include cofflink.lo not because it's needed for
# bfd_elf32_sh64[l]_vec, but because we include bfd_elf32_sh[l]_vec
# which needs it but does not list it. Should be fixed in right place.

2
bfd/configure.in
View File

@ -663,6 +663,8 @@ do
bfd_elf32_powerpcle_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
bfd_elf32_powerpc_vxworks_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
bfd_elf32_s390_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;;
bfd_elf32_bigscore_vec) tb="$tb elf32-score.lo elf32.lo $elf" ;;
bfd_elf32_littlescore_vec) tb="$tb elf32-score.lo elf32.lo $elf" ;;
# FIXME: We include cofflink.lo not because it's needed for
# bfd_elf32_sh64[l]_vec, but because we include bfd_elf32_sh[l]_vec
# which needs it but does not list it. Should be fixed in right place.

51
bfd/cpu-score.c Normal file
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@ -0,0 +1,51 @@
/* BFD support for the score processor
Copyright 2006 Free Software Foundation, Inc.
Contributed by
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#include "bfd.h"
#include "sysdep.h"
#include "libbfd.h"
const bfd_arch_info_type
bfd_score_arch =
{
32, /* There's 32 bits_per_word. */
32, /* There's 32 bits_per_address. */
8, /* There's 8 bits_per_byte. */
bfd_arch_score, /* One of enum bfd_architecture, defined
in archures.c and provided in
generated header files. */
0, /* Only 1 machine, but #255 for
historical reasons. */
"score", /* The arch_name. */
"score", /* The printable name is the same. */
4, /* Section alignment power; each section
is aligned to (only) 2^4 bytes. */
TRUE, /* This is the default "machine", since
there's only one. */
bfd_default_compatible, /* A default function for testing
"machine" compatibility of two
bfd_arch_info_type. */
bfd_default_scan, /* Check if an bfd_arch_info_type is a
match. */
NULL /* Pointer to next bfd_arch_info_type in
the same family. */
};

3883
bfd/elf32-score.c Normal file
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File diff suppressed because it is too large Load Diff

11
bfd/libbfd.h
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@ -1610,6 +1610,17 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_390_GOT20",
"BFD_RELOC_390_GOTPLT20",
"BFD_RELOC_390_TLS_GOTIE20",
"BFD_RELOC_SCORE_DUMMY1",
"BFD_RELOC_SCORE_GPREL15",
"BFD_RELOC_SCORE_DUMMY2",
"BFD_RELOC_SCORE_JMP",
"BFD_RELOC_SCORE_BRANCH",
"BFD_RELOC_SCORE16_JMP",
"BFD_RELOC_SCORE16_BRANCH",
"BFD_RELOC_SCORE_GOT15",
"BFD_RELOC_SCORE_GOT_LO16",
"BFD_RELOC_SCORE_CALL15",
"BFD_RELOC_SCORE_DUMMY_HI16",
"BFD_RELOC_IP2K_FR9",
"BFD_RELOC_IP2K_BANK",
"BFD_RELOC_IP2K_ADDR16CJP",

37
bfd/reloc.c
View File

@ -3965,6 +3965,43 @@ ENUMX
ENUMDOC
Long displacement extension.
ENUM
BFD_RELOC_SCORE_DUMMY1
ENUMDOC
Score relocations
ENUM
BFD_RELOC_SCORE_GPREL15
ENUMDOC
Low 16 bit for load/store
ENUM
BFD_RELOC_SCORE_DUMMY2
ENUMX
BFD_RELOC_SCORE_JMP
ENUMDOC
This is a 24-bit reloc with the right 1 bit assumed to be 0
ENUM
BFD_RELOC_SCORE_BRANCH
ENUMDOC
This is a 19-bit reloc with the right 1 bit assumed to be 0
ENUM
BFD_RELOC_SCORE16_JMP
ENUMDOC
This is a 11-bit reloc with the right 1 bit assumed to be 0
ENUM
BFD_RELOC_SCORE16_BRANCH
ENUMDOC
This is a 8-bit reloc with the right 1 bit assumed to be 0
ENUM
BFD_RELOC_SCORE_GOT15
ENUMX
BFD_RELOC_SCORE_GOT_LO16
ENUMX
BFD_RELOC_SCORE_CALL15
ENUMX
BFD_RELOC_SCORE_DUMMY_HI16
ENUMDOC
Undocumented Score relocs
ENUM
BFD_RELOC_IP2K_FR9
ENUMDOC

4
bfd/targets.c
View File

@ -624,6 +624,8 @@ extern const bfd_target bfd_elf32_powerpc_vec;
extern const bfd_target bfd_elf32_powerpcle_vec;
extern const bfd_target bfd_elf32_powerpc_vxworks_vec;
extern const bfd_target bfd_elf32_s390_vec;
extern const bfd_target bfd_elf32_bigscore_vec;
extern const bfd_target bfd_elf32_littlescore_vec;
extern const bfd_target bfd_elf32_sh64_vec;
extern const bfd_target bfd_elf32_sh64l_vec;
extern const bfd_target bfd_elf32_sh64lin_vec;
@ -944,6 +946,8 @@ static const bfd_target * const _bfd_target_vector[] = {
&bfd_elf32_powerpc_vxworks_vec,
&bfd_elf32_powerpcle_vec,
&bfd_elf32_s390_vec,
&bfd_elf32_bigscore_vec,
&bfd_elf32_littlescore_vec,
&bfd_elf32_sh_vec,
&bfd_elf32_shblin_vec,
&bfd_elf32_shl_vec,

6
binutils/ChangeLog
View File

@ -1,3 +1,9 @@
2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
* readelf.c: Add support for Score binaries.
* Makefile.am: Update readelf's dependencies.
* Makefile.in: Regenerate.
2006-09-16 Nick Clifton <nickc@redhat.com>
Pedro Alves <pedro_alves@portugalmail.pt>

2
binutils/Makefile.am
View File

@ -540,7 +540,7 @@ readelf.o: readelf.c dwarf.h ../bfd/bfd.h $(INCDIR)/ansidecl.h \
$(INCDIR)/elf/mips.h $(INCDIR)/elf/mmix.h $(INCDIR)/elf/mn10200.h \
$(INCDIR)/elf/mn10300.h $(INCDIR)/elf/mt.h $(INCDIR)/elf/msp430.h \
$(INCDIR)/elf/or32.h $(INCDIR)/elf/pj.h $(INCDIR)/elf/ppc.h \
$(INCDIR)/elf/ppc64.h $(INCDIR)/elf/s390.h $(INCDIR)/elf/sh.h \
$(INCDIR)/elf/ppc64.h $(INCDIR)/elf/s390.h $(INCDIR)/elf/score.h $(INCDIR)/elf/sh.h \
$(INCDIR)/elf/sparc.h $(INCDIR)/elf/v850.h $(INCDIR)/elf/vax.h \
$(INCDIR)/elf/x86-64.h $(INCDIR)/elf/xstormy16.h $(INCDIR)/elf/crx.h \
$(INCDIR)/elf/iq2000.h $(INCDIR)/elf/xtensa.h $(INCDIR)/aout/ar.h \

11
binutils/Makefile.in
View File

@ -235,7 +235,6 @@ EXEEXT = @EXEEXT@
EXEEXT_FOR_BUILD = @EXEEXT_FOR_BUILD@
GENCAT = @GENCAT@
GMSGFMT = @GMSGFMT@
GREP = @GREP@
HDEFINES = @HDEFINES@
INCINTL = @INCINTL@
INSTALL_DATA = @INSTALL_DATA@
@ -282,8 +281,9 @@ VERSION = @VERSION@
WARN_CFLAGS = @WARN_CFLAGS@
XGETTEXT = @XGETTEXT@
YACC = `if [ -f ../bison/bison ]; then echo ../bison/bison -y -L$(srcdir)/../bison/; else echo @YACC@; fi`
YFLAGS = -d
ac_ct_CC = @ac_ct_CC@
ac_ct_RANLIB = @ac_ct_RANLIB@
ac_ct_STRIP = @ac_ct_STRIP@
am__fastdepCC_FALSE = @am__fastdepCC_FALSE@
am__fastdepCC_TRUE = @am__fastdepCC_TRUE@
am__include = @am__include@
@ -300,7 +300,6 @@ build_vendor = @build_vendor@
datadir = @datadir@
datarootdir = @datarootdir@
docdir = @docdir@
dvidir = @dvidir@
exec_prefix = @exec_prefix@
host = @host@
host_alias = @host_alias@
@ -313,15 +312,12 @@ infodir = @infodir@
install_sh = @install_sh@
libdir = @libdir@
libexecdir = @libexecdir@
localedir = @localedir@
localstatedir = @localstatedir@
mandir = @mandir@
mkdir_p = @mkdir_p@
oldincludedir = @oldincludedir@
pdfdir = @pdfdir@
prefix = @prefix@
program_transform_name = @program_transform_name@
psdir = @psdir@
sbindir = @sbindir@
sharedstatedir = @sharedstatedir@
sysconfdir = @sysconfdir@
@ -333,6 +329,7 @@ target_vendor = @target_vendor@
AUTOMAKE_OPTIONS = cygnus dejagnu
SUBDIRS = doc po
tooldir = $(exec_prefix)/$(target_alias)
YFLAGS = -d
AM_CFLAGS = $(WARN_CFLAGS)
# these two are almost the same program
@ -1263,7 +1260,7 @@ readelf.o: readelf.c dwarf.h ../bfd/bfd.h $(INCDIR)/ansidecl.h \
$(INCDIR)/elf/mips.h $(INCDIR)/elf/mmix.h $(INCDIR)/elf/mn10200.h \
$(INCDIR)/elf/mn10300.h $(INCDIR)/elf/mt.h $(INCDIR)/elf/msp430.h \
$(INCDIR)/elf/or32.h $(INCDIR)/elf/pj.h $(INCDIR)/elf/ppc.h \
$(INCDIR)/elf/ppc64.h $(INCDIR)/elf/s390.h $(INCDIR)/elf/sh.h \
$(INCDIR)/elf/ppc64.h $(INCDIR)/elf/s390.h $(INCDIR)/elf/score.h $(INCDIR)/elf/sh.h \
$(INCDIR)/elf/sparc.h $(INCDIR)/elf/v850.h $(INCDIR)/elf/vax.h \
$(INCDIR)/elf/x86-64.h $(INCDIR)/elf/xstormy16.h $(INCDIR)/elf/crx.h \
$(INCDIR)/elf/iq2000.h $(INCDIR)/elf/xtensa.h $(INCDIR)/aout/ar.h \

31
binutils/readelf.c
View File

@ -73,6 +73,7 @@
#include "elf/avr.h"
#include "elf/bfin.h"
#include "elf/cris.h"
#include "elf/crx.h"
#include "elf/d10v.h"
#include "elf/d30v.h"
#include "elf/dlx.h"
@ -86,6 +87,7 @@
#include "elf/i960.h"
#include "elf/ia64.h"
#include "elf/ip2k.h"
#include "elf/iq2000.h"
#include "elf/m32c.h"
#include "elf/m32r.h"
#include "elf/m68k.h"
@ -102,14 +104,13 @@
#include "elf/ppc.h"
#include "elf/ppc64.h"
#include "elf/s390.h"
#include "elf/score.h"
#include "elf/sh.h"
#include "elf/sparc.h"
#include "elf/v850.h"
#include "elf/vax.h"
#include "elf/x86-64.h"
#include "elf/xstormy16.h"
#include "elf/crx.h"
#include "elf/iq2000.h"
#include "elf/xtensa.h"
#include "aout/ar.h"
@ -566,6 +567,7 @@ guess_is_rela (unsigned long e_machine)
case EM_CYGNUS_D10V:
case EM_MIPS:
case EM_MIPS_RS3_LE:
case EM_SCORE:
return FALSE;
/* Targets that use RELA relocations. */
@ -1099,6 +1101,10 @@ dump_relocations (FILE *file,
rtype = elf_s390_reloc_type (type);
break;
case EM_SCORE:
rtype = elf_score_reloc_type (type);
break;
case EM_XSTORMY16:
rtype = elf_xstormy16_reloc_type (type);
break;
@ -1431,6 +1437,23 @@ get_alpha_dynamic_type (unsigned long type)
}
}
static const char *
get_score_dynamic_type (unsigned long type)
{
switch (type)
{
case DT_SCORE_BASE_ADDRESS: return "SCORE_BASE_ADDRESS";
case DT_SCORE_LOCAL_GOTNO: return "SCORE_LOCAL_GOTNO";
case DT_SCORE_SYMTABNO: return "SCORE_SYMTABNO";
case DT_SCORE_GOTSYM: return "SCORE_GOTSYM";
case DT_SCORE_UNREFEXTNO: return "SCORE_UNREFEXTNO";
case DT_SCORE_HIPAGENO: return "SCORE_HIPAGENO";
default:
return NULL;
}
}
static const char *
get_dynamic_type (unsigned long type)
{
@ -1539,6 +1562,9 @@ get_dynamic_type (unsigned long type)
case EM_ALPHA:
result = get_alpha_dynamic_type (type);
break;
case EM_SCORE:
result = get_score_dynamic_type (type);
break;
default:
result = NULL;
break;
@ -1693,6 +1719,7 @@ get_machine_name (unsigned e_machine)
case EM_X86_64: return "Advanced Micro Devices X86-64";
case EM_S390_OLD:
case EM_S390: return "IBM S/390";
case EM_SCORE: return "SUNPLUS S+Core";
case EM_XSTORMY16: return "Sanyo Xstormy16 CPU core";
case EM_OPENRISC:
case EM_OR32: return "OpenRISC";

9
gas/ChangeLog
View File

@ -1,3 +1,12 @@
2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
* config/tc-score.c: New file.
* config/tc-score.h: Newf file.
* configure.tgt: Add Score target.
* Makefile.am: Add Score files.
* Makefile.in: Regenerate.
* NEWS: Mention new target support.
2006-09-16 Paul Brook <paul@codesourcery.com>
* config/tc-arm.c (s_arm_unwind_movsp): Add offset argument.

10
gas/Makefile.am
View File

@ -77,6 +77,7 @@ CPU_TYPES = \
pj \
ppc \
s390 \
score \
sh \
sh64 \
sparc \
@ -264,6 +265,7 @@ TARGET_CPU_CFILES = \
config/tc-pj.c \
config/tc-ppc.c \
config/tc-s390.c \
config/tc-score.c \
config/tc-sh.c \
config/tc-sh64.c \
config/tc-sparc.c \
@ -315,6 +317,7 @@ TARGET_CPU_HFILES = \
config/tc-pj.h \
config/tc-ppc.h \
config/tc-s390.h \
config/tc-score.h \
config/tc-sh.h \
config/tc-sh64.h \
config/tc-sparc.h \
@ -1281,6 +1284,13 @@ DEPTC_s390_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
$(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
struc-symbol.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/s390.h \
$(INCDIR)/elf/s390.h $(INCDIR)/elf/reloc-macros.h
DEPTC_score_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
$(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-score.h \
$(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
$(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h \
dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
$(INCDIR)/opcode/score-inst.h $(INCDIR)/opcode/score-datadep.h
DEPTC_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
$(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
$(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \

11
gas/Makefile.in
View File

@ -306,6 +306,7 @@ CPU_TYPES = \
pj \
ppc \
s390 \
score \
sh \
sh64 \
sparc \
@ -491,6 +492,7 @@ TARGET_CPU_CFILES = \
config/tc-pj.c \
config/tc-ppc.c \
config/tc-s390.c \
config/tc-score.c \
config/tc-sh.c \
config/tc-sh64.c \
config/tc-sparc.c \
@ -542,6 +544,7 @@ TARGET_CPU_HFILES = \
config/tc-pj.h \
config/tc-ppc.h \
config/tc-s390.h \
config/tc-score.h \
config/tc-sh.h \
config/tc-sh64.h \
config/tc-sparc.h \
@ -1081,6 +1084,14 @@ DEPTC_s390_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
struc-symbol.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/s390.h \
$(INCDIR)/elf/s390.h $(INCDIR)/elf/reloc-macros.h
DEPTC_score_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
$(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-score.h \
$(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
$(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h \
dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
$(INCDIR)/opcode/score-inst.h $(INCDIR)/opcode/score-datadep.h
DEPTC_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
$(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
$(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \

1
gas/NEWS
View File

@ -1,4 +1,5 @@
-*- text -*-
* Add support for Score target.
* Support for the Infineon XC16X has been added by KPIT Cummins Infosystems.

6634
gas/config/tc-score.c Normal file
View File

File diff suppressed because it is too large Load Diff

83
gas/config/tc-score.h Normal file
View File

@ -0,0 +1,83 @@
/* tc-score.h -- Score specific file for assembler
Copyright 2006 Free Software Foundation, Inc.
Contributed by:
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef TC_SCORE
#define TC_SCORE
#define TARGET_ARCH bfd_arch_score
#define WORKING_DOT_WORD
#define DIFF_EXPR_OK
#define RELOC_EXPANSION_POSSIBLE
#define MAX_RELOC_EXPANSION 2
#define MAX_MEM_FOR_RS_ALIGN_CODE (3 + 4)
#define md_undefined_symbol(name) NULL
#define TARGET_FORMAT (target_big_endian ? "elf32-bigscore" : "elf32-littlescore")
#define md_relax_frag(segment, fragp, stretch) score_relax_frag (segment, fragp, stretch)
extern int score_relax_frag (asection *, struct frag *, long);
#define md_frag_check(fragp) score_frag_check (fragp)
extern void score_frag_check (fragS *);
#define TC_VALIDATE_FIX(FIXP, SEGTYPE, SKIP) score_validate_fix (FIXP)
extern void score_validate_fix (struct fix *);
#define TC_FORCE_RELOCATION(FIXP) score_force_relocation (FIXP)
extern int score_force_relocation (struct fix *);
#define tc_fix_adjustable(fixp) score_fix_adjustable (fixp)
extern bfd_boolean score_fix_adjustable (struct fix *);
#define elf_tc_final_processing score_elf_final_processing
extern void score_elf_final_processing (void);
struct score_tc_frag_data
{
unsigned int is_insn;
struct fix *fixp;
};
#define TC_FRAG_TYPE struct score_tc_frag_data
#define TC_FRAG_INIT(FRAGP) \
do \
{ \
(FRAGP)->tc_frag_data.is_insn = (((FRAGP)->fr_type == rs_machine_dependent) ? 1 : 0); \
} \
while (0)
#ifdef OBJ_ELF
#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
#else
#define GLOBAL_OFFSET_TABLE_NAME "__GLOBAL_OFFSET_TABLE_"
#endif
enum score_pic_level
{
NO_PIC,
PIC
};
#endif /*TC_SCORE */

4
gas/configure.tgt
View File

@ -62,6 +62,8 @@ case ${cpu} in
rs6000*) cpu_type=ppc ;;
s390x*) cpu_type=s390 arch=s390x ;;
s390*) cpu_type=s390 arch=s390 ;;
score*l) cpu_type=score endian=little ;;
score*) cpu_type=score endian=big ;;
sh5le*) cpu_type=sh64 endian=little ;;
sh5*) cpu_type=sh64 endian=big ;;
sh64le*) cpu_type=sh64 endian=little ;;
@ -315,6 +317,8 @@ case ${generic_target} in
s390-*-linux-*) fmt=elf em=linux ;;
s390-*-tpf*) fmt=elf ;;
score-*-elf) fmt=elf ;;
sh*-*-linux*) fmt=elf em=linux
case ${cpu} in
sh*eb) endian=big ;;

6
gas/testsuite/ChangeLog
View File

@ -1,3 +1,9 @@
2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
* gas/score: New directory.
* gas/elf/section2.e-score: New file.
* gas/elf/elf.exp: Add special case for Score target.
2006-09-16 Paul Brook <paul@codesourcery.com>
* gas/arm/unwind.s: Test two argument form of .movsp.

3
gas/testsuite/gas/elf/elf.exp
View File

@ -50,6 +50,9 @@ if { ([istarget "*-*-*elf*"]
if {[istarget m32r*-*-*]} then {
set target_machine -m32r
}
if {[istarget "score-*-*"]} then {
set target_machine -score
}
if { ([istarget "*arm*-*-*"]
|| [istarget "xscale*-*-*"])
&& ([istarget "*-*-*eabi"]

9
gas/testsuite/gas/elf/section2.e-score Normal file
View File

@ -0,0 +1,9 @@
Symbol table '.symtab' contains 6 entries:
Num: Value Size Type Bind Vis Ndx Name
0: 00000000 0 NOTYPE LOCAL DEFAULT UND
1: 00000000 0 SECTION LOCAL DEFAULT 1
2: 00000000 0 SECTION LOCAL DEFAULT 2
3: 00000000 0 SECTION LOCAL DEFAULT 3
4: 00000000 0 SECTION LOCAL DEFAULT 5
5: 00000000 0 SECTION LOCAL DEFAULT 4

4
include/ChangeLog
View File

@ -1,3 +1,7 @@
2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
* dis-asm.h: Add prototypes for Score disassembler routines.
2006-09-07 H.J. Lu <hongjiu.lu@intel.com>
* bfdlink.h (bfd_elf_dynamic_list): New.

82
include/dis-asm.h
View File

@ -1,6 +1,6 @@
/* Interface between the opcode library and its callers.
Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005
Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
@ -37,7 +37,8 @@ extern "C" {
typedef int (*fprintf_ftype) (void *, const char*, ...) ATTRIBUTE_FPTR_PRINTF_2;
enum dis_insn_type {
enum dis_insn_type
{
dis_noninsn, /* Not a valid instruction */
dis_nonbranch, /* Not a branch instruction */
dis_branch, /* Unconditional branch */
@ -58,7 +59,8 @@ enum dis_insn_type {
It must be initialized before it is first passed; this can be done
by hand, or using one of the initialization macros below. */
typedef struct disassemble_info {
typedef struct disassemble_info
{
fprintf_ftype fprintf_func;
void *stream;
void *application_data;
@ -201,59 +203,63 @@ typedef struct disassemble_info {
target address. Return number of octets processed. */
typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);
extern int print_insn_big_mips (bfd_vma, disassemble_info *);
extern int print_insn_little_mips (bfd_vma, disassemble_info *);
extern int print_insn_i386 (bfd_vma, disassemble_info *);
extern int print_insn_i386_att (bfd_vma, disassemble_info *);
extern int print_insn_i386_intel (bfd_vma, disassemble_info *);
extern int print_insn_ia64 (bfd_vma, disassemble_info *);
extern int print_insn_i370 (bfd_vma, disassemble_info *);
extern int print_insn_m68hc11 (bfd_vma, disassemble_info *);
extern int print_insn_m68hc12 (bfd_vma, disassemble_info *);
extern int print_insn_m68k (bfd_vma, disassemble_info *);
extern int print_insn_z80 (bfd_vma, disassemble_info *);
extern int print_insn_z8001 (bfd_vma, disassemble_info *);
extern int print_insn_z8002 (bfd_vma, disassemble_info *);
extern int print_insn_h8300 (bfd_vma, disassemble_info *);
extern int print_insn_h8300h (bfd_vma, disassemble_info *);
extern int print_insn_h8300s (bfd_vma, disassemble_info *);
extern int print_insn_h8500 (bfd_vma, disassemble_info *);
extern int print_insn_alpha (bfd_vma, disassemble_info *);
extern int print_insn_big_arm (bfd_vma, disassemble_info *);
extern int print_insn_little_arm (bfd_vma, disassemble_info *);
extern int print_insn_sparc (bfd_vma, disassemble_info *);
extern int print_insn_avr (bfd_vma, disassemble_info *);
extern int print_insn_bfin (bfd_vma, disassemble_info *);
extern int print_insn_big_arm (bfd_vma, disassemble_info *);
extern int print_insn_big_mips (bfd_vma, disassemble_info *);
extern int print_insn_big_or32 (bfd_vma, disassemble_info *);
extern int print_insn_big_powerpc (bfd_vma, disassemble_info *);
extern int print_insn_big_score (bfd_vma, disassemble_info *);
extern int print_insn_crx (bfd_vma, disassemble_info *);
extern int print_insn_d10v (bfd_vma, disassemble_info *);
extern int print_insn_d30v (bfd_vma, disassemble_info *);
extern int print_insn_dlx (bfd_vma, disassemble_info *);
extern int print_insn_fr30 (bfd_vma, disassemble_info *);
extern int print_insn_frv (bfd_vma, disassemble_info *);
extern int print_insn_h8300 (bfd_vma, disassemble_info *);
extern int print_insn_h8300h (bfd_vma, disassemble_info *);
extern int print_insn_h8300s (bfd_vma, disassemble_info *);
extern int print_insn_h8500 (bfd_vma, disassemble_info *);
extern int print_insn_hppa (bfd_vma, disassemble_info *);
extern int print_insn_i370 (bfd_vma, disassemble_info *);
extern int print_insn_i386 (bfd_vma, disassemble_info *);
extern int print_insn_i386_att (bfd_vma, disassemble_info *);
extern int print_insn_i386_intel (bfd_vma, disassemble_info *);
extern int print_insn_i860 (bfd_vma, disassemble_info *);
extern int print_insn_i960 (bfd_vma, disassemble_info *);
extern int print_insn_ia64 (bfd_vma, disassemble_info *);
extern int print_insn_ip2k (bfd_vma, disassemble_info *);
extern int print_insn_iq2000 (bfd_vma, disassemble_info *);
extern int print_insn_little_arm (bfd_vma, disassemble_info *);
extern int print_insn_little_mips (bfd_vma, disassemble_info *);
extern int print_insn_little_or32 (bfd_vma, disassemble_info *);
extern int print_insn_little_powerpc (bfd_vma, disassemble_info *);
extern int print_insn_little_score (bfd_vma, disassemble_info *);
extern int print_insn_m32c (bfd_vma, disassemble_info *);
extern int print_insn_m32r (bfd_vma, disassemble_info *);
extern int print_insn_m68hc11 (bfd_vma, disassemble_info *);
extern int print_insn_m68hc12 (bfd_vma, disassemble_info *);
extern int print_insn_m68k (bfd_vma, disassemble_info *);
extern int print_insn_m88k (bfd_vma, disassemble_info *);
extern int print_insn_maxq_little (bfd_vma, disassemble_info *);
extern int print_insn_maxq_big (bfd_vma, disassemble_info *);
extern int print_insn_maxq_little (bfd_vma, disassemble_info *);
extern int print_insn_mcore (bfd_vma, disassemble_info *);
extern int print_insn_mmix (bfd_vma, disassemble_info *);
extern int print_insn_mn10200 (bfd_vma, disassemble_info *);
extern int print_insn_mn10300 (bfd_vma, disassemble_info *);
extern int print_insn_mt (bfd_vma, disassemble_info *);
extern int print_insn_msp430 (bfd_vma, disassemble_info *);
extern int print_insn_mt (bfd_vma, disassemble_info *);
extern int print_insn_ns32k (bfd_vma, disassemble_info *);
extern int print_insn_crx (bfd_vma, disassemble_info *);
extern int print_insn_openrisc (bfd_vma, disassemble_info *);
extern int print_insn_big_or32 (bfd_vma, disassemble_info *);
extern int print_insn_little_or32 (bfd_vma, disassemble_info *);
extern int print_insn_pdp11 (bfd_vma, disassemble_info *);
extern int print_insn_pj (bfd_vma, disassemble_info *);
extern int print_insn_big_powerpc (bfd_vma, disassemble_info *);
extern int print_insn_little_powerpc (bfd_vma, disassemble_info *);
extern int print_insn_rs6000 (bfd_vma, disassemble_info *);
extern int print_insn_s390 (bfd_vma, disassemble_info *);
extern int print_insn_sh (bfd_vma, disassemble_info *);
extern int print_insn_sh64 (bfd_vma, disassemble_info *);
extern int print_insn_sh64x_media (bfd_vma, disassemble_info *);
extern int print_insn_sparc (bfd_vma, disassemble_info *);
extern int print_insn_tic30 (bfd_vma, disassemble_info *);
extern int print_insn_tic4x (bfd_vma, disassemble_info *);
extern int print_insn_tic54x (bfd_vma, disassemble_info *);
@ -261,14 +267,12 @@ extern int print_insn_tic80 (bfd_vma, disassemble_info *);
extern int print_insn_v850 (bfd_vma, disassemble_info *);
extern int print_insn_vax (bfd_vma, disassemble_info *);
extern int print_insn_w65 (bfd_vma, disassemble_info *);
extern int print_insn_xc16x (bfd_vma, disassemble_info *);
extern int print_insn_xstormy16 (bfd_vma, disassemble_info *);
extern int print_insn_xtensa (bfd_vma, disassemble_info *);
extern int print_insn_sh64 (bfd_vma, disassemble_info *);
extern int print_insn_sh64x_media (bfd_vma, disassemble_info *);
extern int print_insn_frv (bfd_vma, disassemble_info *);
extern int print_insn_iq2000 (bfd_vma, disassemble_info *);
extern int print_insn_xc16x (bfd_vma, disassemble_info *);
extern int print_insn_m32c (bfd_vma, disassemble_info *);
extern int print_insn_z80 (bfd_vma, disassemble_info *);
extern int print_insn_z8001 (bfd_vma, disassemble_info *);
extern int print_insn_z8002 (bfd_vma, disassemble_info *);
extern disassembler_ftype arc_get_disassembler (void *);
extern disassembler_ftype cris_get_disassembler (bfd *);
@ -277,9 +281,9 @@ extern void print_mips_disassembler_options (FILE *);
extern void print_ppc_disassembler_options (FILE *);
extern void print_arm_disassembler_options (FILE *);
extern void parse_arm_disassembler_option (char *);
extern int get_arm_regname_num_options (void);
extern int set_arm_regname_option (int);
extern int get_arm_regnames (int, const char **, const char **, const char *const **);
extern int get_arm_regname_num_options (void);
extern int set_arm_regname_option (int);
extern int get_arm_regnames (int, const char **, const char **, const char *const **);
extern bfd_boolean arm_symbol_is_valid (asymbol *, struct disassemble_info *);
/* Fetch the disassembler for a given BFD, if that support is available. */

5
include/elf/ChangeLog
View File

@ -1,3 +1,8 @@
2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
* score.h: New file.
* common.h: Add Score machine number.
2006-07-10 Jakub Jelinek <jakub@redhat.com>
* common.h (SHT_GNU_HASH, DT_GNU_HASH): Define.

1
include/elf/common.h
View File

@ -185,6 +185,7 @@
#define EM_BLACKFIN 106 /* ADI Blackfin */
#define EM_ALTERA_NIOS2 113 /* Altera Nios II soft-core processor */
#define EM_CRX 114 /* National Semiconductor CRX */
#define EM_SCORE 135 /* Sunplus Score */
/* If it is necessary to assign new unofficial EM_* values, please pick large
random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision

124
include/elf/score.h Normal file
View File

@ -0,0 +1,124 @@
/* Score ELF support for BFD.
Copyright 2006 Free Software Foundation, Inc.
Contributed by
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation,
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef _ELF_SCORE_H
#define _ELF_SCORE_H
#include "elf/reloc-macros.h"
#define SCORE_SIMULATOR_ACTIVE 1
#define OPC_PTMASK 0xc0000000 /* Parity-bit Mask */
#define OPC16_PTMASK 0x00008000
/* The parity-bit denotes. */
#define OPC_32 0xc0000000 /* denotes 32b instruction, (default) */
#define OPC_16 0x00000000 /* denotes 16b instruction */
#define OPC_PE 0x8000 /* denotes parallel-execution instructions */
#define EF_SCORE_HASENTRY 0x02
#define GP_DISP_LABEL "_gp_disp"
/* Processor specific flags for the ELF header e_flags field. */
/* Fix data dependency. */
#define EF_SCORE_FIXDEP 0x00000001
/* File contains position independent code. */
#define EF_SCORE_PIC 0x00000002
/* Defined and allocated common symbol. Value is virtual address. If
relocated, alignment must be preserved. */
#define SHN_SCORE_TEXT 0xff01
#define SHN_SCORE_DATA 0xff02
/* Small common symbol. */
#define SHN_SCORE_SCOMMON 0xff03
/* Processor specific section flags. */
/* This section must be in the global data area. */
#define SHF_SCORE_GPREL 0x10000000
/* This section should be merged. */
#define SHF_SCORE_MERGE 0x20000000
/* This section contains address data of size implied by section
element size. */
#define SHF_SCORE_ADDR 0x40000000
/* This section contains string data. */
#define SHF_SCORE_STRING 0x80000000
/* This section may not be stripped. */
#define SHF_SCORE_NOSTRIP 0x08000000
/* This section is local to threads. */
#define SHF_SCORE_LOCAL 0x04000000
/* Linker should generate implicit weak names for this section. */
#define SHF_SCORE_NAMES 0x02000000
/* Section contais text/data which may be replicated in other sections.
Linker should retain only one copy. */
#define SHF_SCORE_NODUPES 0x01000000
/* Processor specific dynamic array tags. */
/* Base address of the segment. */
#define DT_SCORE_BASE_ADDRESS 0x70000001
/* Number of local global offset table entries. */
#define DT_SCORE_LOCAL_GOTNO 0x70000002
/* Number of entries in the .dynsym section. */
#define DT_SCORE_SYMTABNO 0x70000003
/* Index of first dynamic symbol in global offset table. */
#define DT_SCORE_GOTSYM 0x70000004
/* Index of first external dynamic symbol not referenced locally. */
#define DT_SCORE_UNREFEXTNO 0x70000005
/* Number of page table entries in global offset table. */
#define DT_SCORE_HIPAGENO 0x70000006
/* Processor specific section types. */
/* Relocation types. */
START_RELOC_NUMBERS (elf_score_reloc_type)
RELOC_NUMBER (R_SCORE_NONE, 0)
RELOC_NUMBER (R_SCORE_HI16, 1)
RELOC_NUMBER (R_SCORE_LO16, 2)
RELOC_NUMBER (R_SCORE_DUMMY1, 3)
RELOC_NUMBER (R_SCORE_24, 4)
RELOC_NUMBER (R_SCORE_PC19, 5)
RELOC_NUMBER (R_SCORE16_11, 6)
RELOC_NUMBER (R_SCORE16_PC8, 7)
RELOC_NUMBER (R_SCORE_ABS32, 8)
RELOC_NUMBER (R_SCORE_ABS16, 9)
RELOC_NUMBER (R_SCORE_DUMMY2, 10)
RELOC_NUMBER (R_SCORE_GP15, 11)
RELOC_NUMBER (R_SCORE_GNU_VTINHERIT, 12)
RELOC_NUMBER (R_SCORE_GNU_VTENTRY, 13)
RELOC_NUMBER (R_SCORE_GOT15, 14)
RELOC_NUMBER (R_SCORE_GOT_LO16, 15)
RELOC_NUMBER (R_SCORE_CALL15, 16)
RELOC_NUMBER (R_SCORE_GPREL32, 17)
RELOC_NUMBER (R_SCORE_REL32, 18)
RELOC_NUMBER (R_SCORE_DUMMY_HI16, 19)
END_RELOC_NUMBERS (R_SCORE_max)
#endif /* _ELF_SCORE_H */

5
include/opcode/ChangeLog
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@ -1,3 +1,8 @@
2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
* score-datadep.h: New file.
* score-inst.h: New file.
2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,

282
include/opcode/score-datadep.h Normal file
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@ -0,0 +1,282 @@
/* score-datadep.h -- Score Instructions data dependency table
Copyright 2006 Free Software Foundation, Inc.
Contributed by:
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
#ifndef SCORE_DATA_DEPENDENCY_H
#define SCORE_DATA_DEPENDENCY_H
#define INSN_NAME_LEN 16
enum insn_type_for_dependency
{
D_pce,
D_cond_br,
D_cond_mv,
D_cached,
D_cachei,
D_ldst,
D_ldcombine,
D_mtcr,
D_mfcr,
D_mfsr,
D_mftlb,
D_mtptlb,
D_mtrtlb,
D_stlb,
D_all_insn
};
struct insn_to_dependency
{
char *insn_name;
enum insn_type_for_dependency type;
};
struct data_dependency
{
enum insn_type_for_dependency pre_insn_type;
char pre_reg[6];
enum insn_type_for_dependency cur_insn_type;
char cur_reg[6];
int bubblenum_7;
int bubblenum_5;
int warn_or_error; /* warning - 0; error - 1 */
};
static const struct insn_to_dependency insn_to_dependency_table[] =
{
/* pce instruction. */
{"pce", D_pce},
/* conditional branch instruction. */
{"bcs", D_cond_br},
{"bcc", D_cond_br},
{"bgtu", D_cond_br},
{"bleu", D_cond_br},
{"beq", D_cond_br},
{"bne", D_cond_br},
{"bgt", D_cond_br},
{"ble", D_cond_br},
{"bge", D_cond_br},
{"blt", D_cond_br},
{"bmi", D_cond_br},
{"bpl", D_cond_br},
{"bvs", D_cond_br},
{"bvc", D_cond_br},
{"bcsl", D_cond_br},
{"bccl", D_cond_br},
{"bgtul", D_cond_br},
{"bleul", D_cond_br},
{"beql", D_cond_br},
{"bnel", D_cond_br},
{"bgtl", D_cond_br},
{"blel", D_cond_br},
{"bgel", D_cond_br},
{"bltl", D_cond_br},
{"bmil", D_cond_br},
{"bpll", D_cond_br},
{"bvsl", D_cond_br},
{"bvcl", D_cond_br},
{"bcs!", D_cond_br},
{"bcc!", D_cond_br},
{"bgtu!", D_cond_br},
{"bleu!", D_cond_br},
{"beq!", D_cond_br},
{"bne!", D_cond_br},
{"bgt!", D_cond_br},
{"ble!", D_cond_br},
{"bge!", D_cond_br},
{"blt!", D_cond_br},
{"bmi!", D_cond_br},
{"bpl!", D_cond_br},
{"bvs!", D_cond_br},
{"bvc!", D_cond_br},
{"brcs", D_cond_br},
{"brcc", D_cond_br},
{"brgtu", D_cond_br},
{"brleu", D_cond_br},
{"breq", D_cond_br},
{"brne", D_cond_br},
{"brgt", D_cond_br},
{"brle", D_cond_br},
{"brge", D_cond_br},
{"brlt", D_cond_br},
{"brmi", D_cond_br},
{"brpl", D_cond_br},
{"brvs", D_cond_br},
{"brvc", D_cond_br},
{"brcsl", D_cond_br},
{"brccl", D_cond_br},
{"brgtul", D_cond_br},
{"brleul", D_cond_br},
{"breql", D_cond_br},
{"brnel", D_cond_br},
{"brgtl", D_cond_br},
{"brlel", D_cond_br},
{"brgel", D_cond_br},
{"brltl", D_cond_br},
{"brmil", D_cond_br},
{"brpll", D_cond_br},
{"brvsl", D_cond_br},
{"brvcl", D_cond_br},
{"brcs!", D_cond_br},
{"brcc!", D_cond_br},
{"brgtu!", D_cond_br},
{"brleu!", D_cond_br},
{"breq!", D_cond_br},
{"brne!", D_cond_br},
{"brgt!", D_cond_br},
{"brle!", D_cond_br},
{"brge!", D_cond_br},
{"brlt!", D_cond_br},
{"brmi!", D_cond_br},
{"brpl!", D_cond_br},
{"brvs!", D_cond_br},
{"brvc!", D_cond_br},
{"brcsl!", D_cond_br},
{"brccl!", D_cond_br},
{"brgtul!", D_cond_br},
{"brleul!", D_cond_br},
{"breql!", D_cond_br},
{"brnel!", D_cond_br},
{"brgtl!", D_cond_br},
{"brlel!", D_cond_br},
{"brgel!", D_cond_br},
{"brltl!", D_cond_br},
{"brmil!", D_cond_br},
{"brpll!", D_cond_br},
{"brvsl!", D_cond_br},
{"brvcl!", D_cond_br},
/* conditional move instruction. */
{"mvcs", D_cond_mv},
{"mvcc", D_cond_mv},
{"mvgtu", D_cond_mv},
{"mvleu", D_cond_mv},
{"mveq", D_cond_mv},
{"mvne", D_cond_mv},
{"mvgt", D_cond_mv},
{"mvle", D_cond_mv},
{"mvge", D_cond_mv},
{"mvlt", D_cond_mv},
{"mvmi", D_cond_mv},
{"mvpl", D_cond_mv},
{"mvvs", D_cond_mv},
{"mvvc", D_cond_mv},
/* move spectial instruction. */
{"mtcr", D_mtcr},
{"mftlb", D_mftlb},
{"mtptlb", D_mtptlb},
{"mtrtlb", D_mtrtlb},
{"stlb", D_stlb},
{"mfcr", D_mfcr},
{"mfsr", D_mfsr},
/* cache instruction. */
{"cache 8", D_cached},
{"cache 9", D_cached},
{"cache 10", D_cached},
{"cache 11", D_cached},
{"cache 12", D_cached},
{"cache 13", D_cached},
{"cache 14", D_cached},
{"cache 24", D_cached},
{"cache 26", D_cached},
{"cache 27", D_cached},
{"cache 29", D_cached},
{"cache 30", D_cached},
{"cache 31", D_cached},
{"cache 0", D_cachei},
{"cache 1", D_cachei},
{"cache 2", D_cachei},
{"cache 3", D_cachei},
{"cache 4", D_cachei},
{"cache 16", D_cachei},
{"cache 17", D_cachei},
/* load/store instruction. */
{"lb", D_ldst},
{"lbu", D_ldst},
{"lbu!", D_ldst},
{"lbup!", D_ldst},
{"lh", D_ldst},
{"lhu", D_ldst},
{"lh!", D_ldst},
{"lhp!", D_ldst},
{"lw", D_ldst},
{"lw!", D_ldst},
{"lwp!", D_ldst},
{"sb", D_ldst},
{"sb!", D_ldst},
{"sbp!", D_ldst},
{"sh", D_ldst},
{"sh!", D_ldst},
{"shp!", D_ldst},
{"sw", D_ldst},
{"sw!", D_ldst},
{"swp!", D_ldst},
{"alw", D_ldst},
{"asw", D_ldst},
{"push!", D_ldst},
{"pushhi!", D_ldst},
{"pop!", D_ldst},
{"pophi!", D_ldst},
{"ldc1", D_ldst},
{"ldc2", D_ldst},
{"ldc3", D_ldst},
{"stc1", D_ldst},
{"stc2", D_ldst},
{"stc3", D_ldst},
{"scb", D_ldst},
{"scw", D_ldst},
{"sce", D_ldst},
/* load combine instruction. */
{"lcb", D_ldcombine},
{"lcw", D_ldcombine},
{"lce", D_ldcombine},
};
static const struct data_dependency data_dependency_table[] =
{
/* Condition register. */
{D_mtcr, "cr1", D_pce, "", 2, 1, 1},
{D_mtcr, "cr1", D_cond_br, "", 1, 0, 1},
{D_mtcr, "cr1", D_cond_mv, "", 1, 0, 1},
/* Status regiser. */
{D_mtcr, "cr0", D_all_insn, "", 5, 4, 0},
/* CCR regiser. */
{D_mtcr, "cr4", D_all_insn, "", 6, 5, 0},
/* EntryHi/EntryLo register. */
{D_mftlb, "", D_mtptlb, "", 1, 1, 1},
{D_mftlb, "", D_mtrtlb, "", 1, 1, 1},
{D_mftlb, "", D_stlb, "", 1, 1,1},
{D_mftlb, "", D_mfcr, "cr11", 1, 1, 1},
{D_mftlb, "", D_mfcr, "cr12", 1, 1, 1},
/* Index register. */
{D_stlb, "", D_mtptlb, "", 1, 1, 1},
{D_stlb, "", D_mftlb, "", 1, 1, 1},
{D_stlb, "", D_mfcr, "cr8", 2, 2, 1},
/* Cache. */
{D_cached, "", D_ldst, "", 1, 1, 0},
{D_cached, "", D_ldcombine, "", 1, 1, 0},
{D_cachei, "", D_all_insn, "", 5, 4, 0},
/* Load combine. */
{D_ldcombine, "", D_mfsr, "sr1", 3, 3, 1},
};
#endif

506
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/* score-inst.h -- Score Instructions Table
Copyright 2006 Free Software Foundation, Inc.
Contributed by:
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#ifndef SCORE_INST_H
#define SCORE_INST_H
#define LDST_UNALIGN_MASK 0x0000007f
#define UA_LCB 0x00000060
#define UA_LCW 0x00000062
#define UA_LCE 0x00000066
#define UA_SCB 0x00000068
#define UA_SCW 0x0000006a
#define UA_SCE 0x0000006e
#define UA_LL 0x0000000c
#define UA_SC 0x0000000e
#define LDST16_RR_MASK 0x0000000f
#define N16_LW 8
#define N16_LH 9
#define N16_POP 10
#define N16_LBU 11
#define N16_SW 12
#define N16_SH 13
#define N16_PUSH 14
#define N16_SB 15
#define LDST16_RI_MASK 0x7007
#define N16_LWP 0x7000
#define N16_LHP 0x7001
#define N16_LBUP 0x7003
#define N16_SWP 0x7004
#define N16_SHP 0x7005
#define N16_SBP 0x7007
#define N16_LIU 0x5000
#define OPC_PSEUDOLDST_MASK 0x00000007
enum
{
INSN_LW = 0,
INSN_LH = 1,
INSN_LHU = 2,
INSN_LB = 3,
INSN_SW = 4,
INSN_SH = 5,
INSN_LBU = 6,
INSN_SB = 7,
};
/* Sub opcdoe opcode. */
enum
{
INSN16_LBU = 11,
INSN16_LH = 9,
INSN16_LW = 8,
INSN16_SB = 15,
INSN16_SH = 13,
INSN16_SW = 12,
};
enum
{
LDST_NOUPDATE = 0,
LDST_PRE = 1,
LDST_POST = 2,
};
enum score_insn_type
{
Rd_I4,
Rd_I5,
Rd_rvalueBP_I5,
Rd_lvalueBP_I5,
Rd_Rs_I5,
x_Rs_I5,
x_I5_x,
Rd_I8,
Rd_Rs_I14,
I15,
Rd_I16,
Rd_rvalueRs_SI10,
Rd_lvalueRs_SI10,
Rd_rvalueRs_preSI12,
Rd_rvalueRs_postSI12,
Rd_lvalueRs_preSI12,
Rd_lvalueRs_postSI12,
Rd_Rs_SI14,
Rd_rvalueRs_SI15,
Rd_lvalueRs_SI15,
Rd_SI16,
PC_DISP8div2,
PC_DISP11div2,
PC_DISP19div2,
PC_DISP24div2,
Rd_Rs_Rs,
x_Rs_x,
x_Rs_Rs,
Rd_Rs_x,
Rd_x_Rs,
Rd_x_x,
Rd_Rs,
Rd_HighRs,
Rd_lvalueRs,
Rd_rvalueRs,
Rd_lvalue32Rs,
Rd_rvalue32Rs,
x_Rs,
NO_OPD,
NO16_OPD,
OP5_rvalueRs_SI15,
I5_Rs_Rs_I5_OP5,
x_rvalueRs_post4,
Rd_rvalueRs_post4,
Rd_x_I5,
Rd_lvalueRs_post4,
x_lvalueRs_post4,
Rd_LowRs,
Rd_Rs_Rs_imm,
Insn_Type_PCE,
Insn_Type_SYN,
Insn_GP,
Insn_PIC,
};
enum score_data_type
{
_IMM4 = 0,
_IMM5,
_IMM8,
_IMM14,
_IMM15,
_IMM16,
_SIMM10 = 6,
_SIMM12,
_SIMM14,
_SIMM15,
_SIMM16,
_SIMM14_NEG = 11,
_IMM16_NEG,
_SIMM16_NEG,
_IMM20,
_IMM25,
_DISP8div2 = 16,
_DISP11div2,
_DISP19div2,
_DISP24div2,
_VALUE,
_VALUE_HI16,
_VALUE_LO16,
_VALUE_LDST_LO16 = 23,
_SIMM16_LA,
_IMM5_RSHIFT_1,
_IMM5_RSHIFT_2,
_SIMM16_LA_POS,
_IMM5_RANGE_8_31,
_IMM10_RSHIFT_2,
_GP_IMM15 = 30,
_GP_IMM14 = 31,
_SIMM16_pic = 42, /* Index in score_df_range. */
_IMM16_LO16_pic = 43,
_IMM16_pic = 44,
};
#define REG_TMP 1
#define OP_REG_TYPE (1 << 6)
#define OP_IMM_TYPE (1 << 7)
#define OP_SH_REGD (OP_REG_TYPE |20)
#define OP_SH_REGS1 (OP_REG_TYPE |15)
#define OP_SH_REGS2 (OP_REG_TYPE |10)
#define OP_SH_I (OP_IMM_TYPE | 1)
#define OP_SH_RI15 (OP_IMM_TYPE | 0)
#define OP_SH_I12 (OP_IMM_TYPE | 3)
#define OP_SH_DISP24 (OP_IMM_TYPE | 1)
#define OP_SH_DISP19_p1 (OP_IMM_TYPE |15)
#define OP_SH_DISP19_p2 (OP_IMM_TYPE | 1)
#define OP_SH_I5 (OP_IMM_TYPE |10)
#define OP_SH_I10 (OP_IMM_TYPE | 5)
#define OP_SH_COPID (OP_IMM_TYPE | 5)
#define OP_SH_TRAPI5 (OP_IMM_TYPE |15)
#define OP_SH_I15 (OP_IMM_TYPE |10)
#define OP16_SH_REGD (OP_REG_TYPE | 8)
#define OP16_SH_REGS1 (OP_REG_TYPE | 4)
#define OP16_SH_I45 (OP_IMM_TYPE | 3)
#define OP16_SH_I8 (OP_IMM_TYPE | 0)
#define OP16_SH_DISP8 (OP_IMM_TYPE | 0)
#define OP16_SH_DISP11 (OP_IMM_TYPE | 1)
struct datafield_range
{
int data_type;
int bits;
int range[2];
};
struct datafield_range score_df_range[] =
{
{_IMM4, 4, {0, (1 << 4) - 1}}, /* ( 0 ~ 15 ) */
{_IMM5, 5, {0, (1 << 5) - 1}}, /* ( 0 ~ 31 ) */
{_IMM8, 8, {0, (1 << 8) - 1}}, /* ( 0 ~ 255 ) */
{_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 16383) */
{_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */
{_IMM16, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */
{_SIMM10, 10, {-(1 << 9), (1 << 9) - 1}}, /* ( -512 ~ 511 ) */
{_SIMM12, 12, {-(1 << 11), (1 << 11) - 1}}, /* ( -2048 ~ 2047 ) */
{_SIMM14, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8192 ~ 8191 ) */
{_SIMM15, 15, {-(1 << 14), (1 << 14) - 1}}, /* (-16384 ~ 16383) */
{_SIMM16, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
{_SIMM14_NEG, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8191 ~ 8192 ) */
{_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* (-65535 ~ 0 ) */
{_SIMM16_NEG, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
{_IMM20, 20, {0, (1 << 20) - 1}},
{_IMM25, 25, {0, (1 << 25) - 1}},
{_DISP8div2, 8, {-(1 << 8), (1 << 8) - 1}}, /* ( -256 ~ 255 ) */
{_DISP11div2, 11, {0, 0}},
{_DISP19div2, 19, {-(1 << 19), (1 << 19) - 1}}, /* (-524288 ~ 524287) */
{_DISP24div2, 24, {0, 0}},
{_VALUE, 32, {0, ((unsigned int)1 << 31) - 1}},
{_VALUE_HI16, 16, {0, (1 << 16) - 1}},
{_VALUE_LO16, 16, {0, (1 << 16) - 1}},
{_VALUE_LDST_LO16, 16, {0, (1 << 16) - 1}},
{_SIMM16_LA, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
{_IMM5_RSHIFT_1, 5, {0, (1 << 6) - 1}}, /* ( 0 ~ 63 ) */
{_IMM5_RSHIFT_2, 5, {0, (1 << 7) - 1}}, /* ( 0 ~ 127 ) */
{_SIMM16_LA_POS, 16, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */
{_IMM5_RANGE_8_31, 5, {8, 31}}, /* But for cop0 the valid data : (8 ~ 31). */
{_IMM10_RSHIFT_2, 10, {-(1 << 11), (1 << 11) - 1}}, /* For ldc#, stc#. */
{_SIMM10, 10, {0, (1 << 10) - 1}}, /* ( -1024 ~ 1023 ) */
{_SIMM12, 12, {0, (1 << 12) - 1}}, /* ( -2048 ~ 2047 ) */
{_SIMM14, 14, {0, (1 << 14) - 1}}, /* ( -8192 ~ 8191 ) */
{_SIMM15, 15, {0, (1 << 15) - 1}}, /* (-16384 ~ 16383) */
{_SIMM16, 16, {0, (1 << 16) - 1}}, /* (-65536 ~ 65536) */
{_SIMM14_NEG, 14, {0, (1 << 16) - 1}}, /* ( -8191 ~ 8192 ) */
{_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
{_SIMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
{_IMM20, 20, {0, (1 << 20) - 1}}, /* (-32768 ~ 32767) */
{_IMM25, 25, {0, (1 << 25) - 1}}, /* (-32768 ~ 32767) */
{_GP_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 65535) */
{_GP_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 65535) */
{_SIMM16_pic, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
{_IMM16_LO16_pic, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
{_IMM16_pic, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */
};
struct shift_bitmask
{
int opd_type;
int opd_num;
struct datafield_range *df_range;
int sh[4];
long fieldbits[4];
};
struct shift_bitmask score_sh_bits_map[] =
{
{
Rd_I4, 2, &score_df_range[_IMM4],
{OP16_SH_REGD, OP16_SH_I45, 0, 0},
{0xf, 0xf, 0, 0},
},
{
Rd_I5, 2, &score_df_range[_IMM5],
{OP16_SH_REGD, OP16_SH_I45, 0, 0},
{0xf, 0x1f, 0, 0},
},
{
Rd_rvalueBP_I5, 2, &score_df_range[_IMM5],
{OP16_SH_REGD, OP16_SH_I45, 0, 0},
{0xf, 0x1f, 0, 0},
},
{
Rd_lvalueBP_I5, 2, &score_df_range[_IMM5],
{OP16_SH_REGD, OP16_SH_I45, 0, 0},
{0xf, 0x1f, 0, 0},
},
{
Rd_Rs_I5, 3, &score_df_range[_IMM5],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I5, 0},
{0x1f, 0x1f, 0x1f, 0},
},
{
x_Rs_I5, 2, &score_df_range[_IMM5],
{OP_SH_REGS1, OP_SH_I5, 0, 0},
{0x1f, 0x1f, 0, 0},
},
{
x_I5_x, 1, &score_df_range[_IMM5],
{OP_SH_TRAPI5, 0, 0, 0},
{0x1f, 0, 0, 0},
},
{
Rd_I8, 2, &score_df_range[_IMM8],
{OP16_SH_REGD, OP16_SH_I8, 0, 0},
{0xf, 0xff, 0, 0},
},
{
Rd_Rs_I14, 3, &score_df_range[_IMM14],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
{0x1f, 0x1f, 0x3fff, 0},
},
{
I15, 1, &score_df_range[_IMM15],
{OP_SH_I15, 0, 0, 0},
{0x7fff, 0, 0, 0},
},
{
Rd_I16, 2, &score_df_range[_IMM16],
{OP_SH_REGD, OP_SH_I, 0, 0},
{0x1f, 0xffff, 0, 0},
},
{
Rd_rvalueRs_SI10, 3, &score_df_range[_SIMM10],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
{0x1f, 0x1f, 0x3ff, 0},
},
{
Rd_lvalueRs_SI10, 3, &score_df_range[_SIMM10],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
{0x1f, 0x1f, 0x3ff, 0},
},
{
Rd_rvalueRs_preSI12, 3, &score_df_range[_SIMM12],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
{0xf, 0xf, 0xfff, 0},
},
{
Rd_rvalueRs_postSI12, 3, &score_df_range[_SIMM12],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
{0xf, 0xf, 0xfff, 0},
},
{
Rd_lvalueRs_preSI12, 3, &score_df_range[_SIMM12],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
{0xf, 0xf, 0xfff, 0},
},
{
Rd_lvalueRs_postSI12, 3, &score_df_range[_SIMM12],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
{0xf, 0xf, 0xfff, 0},
},
{
Rd_Rs_SI14, 3, &score_df_range[_SIMM14],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
{0x1f, 0x1f, 0x3fff, 0},
},
{
Rd_rvalueRs_SI15, 3, &score_df_range[_SIMM15],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
{0x1f, 0x1f, 0x7fff, 0},
},
{
Rd_lvalueRs_SI15, 3, &score_df_range[_SIMM15],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
{0x1f, 0x1f, 0x7fff, 0},
},
{
Rd_SI16, 2, &score_df_range[_SIMM16],
{OP_SH_REGD, OP_SH_I, 0, 0},
{0x1f, 0xffff, 0, 0},
},
{
PC_DISP8div2, 1, &score_df_range[_DISP8div2],
{OP16_SH_DISP8, 0, 0, 0},
{0xff, 0, 0, 0},
},
{
PC_DISP11div2, 1, &score_df_range[_DISP11div2],
{OP16_SH_DISP11, 0, 0, 0},
{0x7ff, 0, 0, 0},
},
{
PC_DISP19div2, 2, &score_df_range[_DISP19div2],
{OP_SH_DISP19_p1, OP_SH_DISP19_p2, 0, 0},
{0x3ff, 0x1ff, 0, 0},
},
{
PC_DISP24div2, 1, &score_df_range[_DISP24div2],
{OP_SH_DISP24, 0, 0, 0},
{0xffffff, 0, 0, 0},
},
{
Rd_Rs_Rs, 3, NULL,
{OP_SH_REGD, OP_SH_REGS1, OP_SH_REGS2, 0},
{0x1f, 0x1f, 0x1f, 0}
},
{
Rd_Rs_x, 2, NULL,
{OP_SH_REGD, OP_SH_REGS1, 0, 0},
{0x1f, 0x1f, 0, 0},
},
{
Rd_x_Rs, 2, NULL,
{OP_SH_REGD, OP_SH_REGS2, 0, 0},
{0x1f, 0x1f, 0, 0},
},
{
Rd_x_x, 1, NULL,
{OP_SH_REGD, 0, 0, 0},
{0x1f, 0, 0, 0},
},
{
x_Rs_Rs, 2, NULL,
{OP_SH_REGS1, OP_SH_REGS2, 0, 0},
{0x1f, 0x1f, 0, 0},
},
{
x_Rs_x, 1, NULL,
{OP_SH_REGS1, 0, 0, 0},
{0x1f, 0, 0, 0},
},
{
Rd_Rs, 2, NULL,
{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
{0xf, 0xf, 0, 0},
},
{
Rd_HighRs, 2, NULL,
{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
{0xf, 0xf, 0x1f, 0},
},
{
Rd_rvalueRs, 2, NULL,
{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
{0xf, 0xf, 0, 0},
},
{
Rd_lvalueRs, 2, NULL,
{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
{0xf, 0xf, 0, 0}
},
{
Rd_lvalue32Rs, 2, NULL,
{OP_SH_REGD, OP_SH_REGS1, 0, 0},
{0x1f, 0x1f, 0, 0},
},
{
Rd_rvalue32Rs, 2, NULL,
{OP_SH_REGD, OP_SH_REGS1, 0, 0},
{0x1f, 0x1f, 0, 0},
},
{
x_Rs, 1, NULL,
{OP16_SH_REGS1, 0, 0, 0},
{0xf, 0, 0, 0},
},
{
NO_OPD, 0, NULL,
{0, 0, 0, 0},
{0, 0, 0, 0},
},
{
NO16_OPD, 0, NULL,
{0, 0, 0, 0},
{0, 0, 0, 0},
},
};
struct asm_opcode
{
/* Instruction name. */
const char *template;
/* Instruction Opcode. */
unsigned long value;
/* Instruction bit mask. */
unsigned long bitmask;
/* Relax instruction opcode. 0x8000 imply no relaxation. */
unsigned long relax_value;
/* Instruction type. */
enum score_insn_type type;
/* Function to call to parse args. */
void (*parms) (char *);
};
enum insn_class
{
INSN_CLASS_16,
INSN_CLASS_32,
INSN_CLASS_PCE,
INSN_CLASS_SYN
};
#endif

9
ld/ChangeLog
View File

@ -1,3 +1,12 @@
2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
* emulparams/scoreelf.sh: New file.
* emultempl/scoreelf.em: New file.
* Makefile.am: Add Score files.
* Makefile.in: Regenerate.
* configure.tgt: Add Score target.
* NEWS: Mention new target support.
2006-09-16 Nick Clifton <nickc@redhat.com>
Pedro Alves <pedro_alves@portugalmail.pt>

5
ld/Makefile.am
View File

@ -340,6 +340,7 @@ ALL_EMULATIONS = \
eppcpe.o \
eppclynx.o \
eriscix.o \
escoreelf.o \
esh.o \
eshelf32.o \
eshlelf32.o \
@ -1466,6 +1467,10 @@ eppclynx.c: $(srcdir)/emulparams/ppclynx.sh \
eriscix.c: $(srcdir)/emulparams/riscix.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}
${GENSCRIPTS} riscix "$(tdir_riscix)"
escoreelf.c: $(srcdir)/emulparams/scoreelf.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/scoreelf.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} scoreelf "$(tdir_scoreelf)"
esh.c: $(srcdir)/emulparams/sh.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/sh.sc ${GEN_DEPENDS}
${GENSCRIPTS} sh "$(tdir_sh)"

5
ld/Makefile.in
View File

@ -564,6 +564,7 @@ ALL_EMULATIONS = \
eppcpe.o \
eppclynx.o \
eriscix.o \
escoreelf.o \
esh.o \
eshelf32.o \
eshlelf32.o \
@ -2277,6 +2278,10 @@ eppclynx.c: $(srcdir)/emulparams/ppclynx.sh \
eriscix.c: $(srcdir)/emulparams/riscix.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}
${GENSCRIPTS} riscix "$(tdir_riscix)"
escoreelf.c: $(srcdir)/emulparams/scoreelf.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/scoreelf.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} scoreelf "$(tdir_scoreelf)"
esh.c: $(srcdir)/emulparams/sh.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/sh.sc ${GEN_DEPENDS}
${GENSCRIPTS} sh "$(tdir_sh)"

2
ld/NEWS
View File

@ -1,4 +1,6 @@
-*- text -*-
* Add support for Score target.
* ELF: Add --dynamic-list option to specify a list of global symbols
whose references shouldn't be bound to the definition within the
shared library, or a list of symbols which should be added to the

1
ld/configure.tgt
View File

@ -445,6 +445,7 @@ s390-*-linux*) targ_emul=elf_s390
tdir_elf64_s390=`echo ${targ_alias} | sed -e 's/s390/s390x/'`
fi
;;
score-*-elf) targ_emul=scoreelf ;;
sh-*-linux*) targ_emul=shlelf_linux
targ_extra_emuls=shelf_linux
targ_extra_libpath=shelf_linux ;;

31
ld/emulparams/scoreelf.sh Normal file
View File

@ -0,0 +1,31 @@
MACHINE=
SCRIPT_NAME=elf
TEMPLATE_NAME=elf32
OUTPUT_FORMAT="elf32-bigscore"
BIG_OUTPUT_FORMAT="elf32-bigscore"
LITTLE_OUTPUT_FORMAT="elf32-littlescore"
GROUP="-lm -lc -lglsim -lgcc -lstdc++"
TEXT_START_ADDR=0x00000000
MAXPAGESIZE=256
NONPAGED_TEXT_START_ADDR=0x0400000
SHLIB_TEXT_START_ADDR=0x5ffe0000
OTHER_GOT_SYMBOLS='
_gp = ALIGN(16) + 0x3ff0;
'
OTHER_BSS_START_SYMBOLS='_bss_start__ = . + ALIGN(4);'
OTHER_BSS_END_SYMBOLS='_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;'
DATA_START_SYMBOLS='_fdata = . ;'
SDATA_START_SYMBOLS='_sdata_begin = . ;'
OTHER_BSS_SYMBOLS='
_bss_start = ALIGN(4) ;
'
# This sets the stack to the top of the simulator memory (2^19 bytes).
STACK_ADDR=0x8000000
ARCH=score
MACHINE=
ENTRY=_start
EMBEDDED=yes
GENERATE_SHLIB_SCRIPT=yes

74
ld/emultempl/scoreelf.em Normal file
View File

@ -0,0 +1,74 @@
# This shell script emits a C file. -*- C -*-
# Copyright 2006 Free Software Foundation, Inc.
# Contributed by:
# Mei Ligang (ligang@sunnorth.com.cn)
# Pei-Lin Tsai (pltsai@sunplus.com)
# This file is part of GLD, the Gnu Linker.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
# 02110-1301, USA.
#
# This file is sourced from elf32.em, and defines extra score-elf
# specific routines.
#
cat >>e${EMULATION_NAME}.c <<EOF
static void
gld${EMULATION_NAME}_before_parse ()
{
#ifndef TARGET_ /* I.e., if not generic. */
ldfile_set_output_arch ("`echo ${ARCH}`");
#endif /* not TARGET_ */
config.dynamic_link = ${DYNAMIC_LINK-true};
config.has_shared = `if test -n "$GENERATE_SHLIB_SCRIPT" ; then echo true ; else echo false ; fi`;
}
static void
score_elf_after_open (void)
{
if (strstr (bfd_get_target (output_bfd), "score") == NULL)
{
/* The score backend needs special fields in the output hash structure.
These will only be created if the output format is an score format,
hence we do not support linking and changing output formats at the
same time. Use a link followed by objcopy to change output formats. */
einfo ("%F%X%P: error: cannot change output format whilst linking S+core binaries\n");
return;
}
/* Call the standard elf routine. */
gld${EMULATION_NAME}_after_open ();
}
EOF
# Define some shell vars to insert bits of code into the standard elf
# parse_args and list_options functions.
#
PARSE_AND_LIST_PROLOGUE=''
PARSE_AND_LIST_SHORTOPTS=
PARSE_AND_LIST_LONGOPTS=''
PARSE_AND_LIST_OPTIONS=''
PARSE_AND_LIST_ARGS_CASES=''
# We have our own after_open and before_allocation functions, but they call
# the standard routines, so give them a different name.
LDEMUL_AFTER_OPEN=score_elf_after_open
# Replace the elf before_parse function with our own.
LDEMUL_BEFORE_PARSE=gld"${EMULATION_NAME}"_before_parse

6
ld/testsuite/ChangeLog
View File

@ -1,3 +1,9 @@
2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
* ld-elf/merge.d: Add special case for Score target.
* ld-elfcomm/elfcomm.exp: Likewise.
* ld-srec/srec.exp: Likewise.
2006-09-15 H.J. Lu <hongjiu.lu@intel.com>
* ld-scripts/overlay-size.t: Discard .reginfo sections.

2
ld/testsuite/ld-elf/merge.d
View File

@ -2,7 +2,7 @@
#ld: -T merge.ld
#objdump: -s
#xfail: "arc-*-*" "avr-*-*" "bfin-*-*" "cris*-*-*" "crx-*-*" "d10v-*-*" "d30v-*-*"
#xfail: "dlx-*-*" "fr30-*-*" "frv-*-*" "hppa*-*-*" "h8300-*-*"
#xfail: "dlx-*-*" "fr30-*-*" "frv-*-*" "hppa*-*-*" "h8300-*-*" "score-*-*"
#xfail: "i370-*-*" "i860-*-*" "i960-*-*" "ip2k-*-*" "iq2000-*-*"
#xfail: "mcore-*-*" "mn102*-*-*" "mips*-*-*" "ms1-*-*" "msp430-*-*"
#xfail: "or32-*-*" "pj-*-*" "sparc*-*-*" "vax-*-*" "xstormy16-*-*" "xtensa-*-*"

9
ld/testsuite/ld-elfcomm/elfcomm.exp
View File

@ -1,5 +1,5 @@
# Expect script for common symbol tests
# Copyright 2003, 2005 Free Software Foundation, Inc.
# Copyright 2003, 2005, 2006 Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@ -38,6 +38,13 @@ if { [which $CC] == 0 } {
untested $test1c2
return
}
if { [istarget score-*-*] } {
untested $test1w1
untested $test1w2
untested $test1c1
untested $test1c2
return
}
proc dump_common1 { testname } {
global exec_output

4
ld/testsuite/ld-srec/srec.exp
View File

@ -1,6 +1,6 @@
# Test linking directly to S-records.
# By Ian Lance Taylor, Cygnus Support.
# Copyright 1999, 2000, 2001, 2002, 2003
# Copyright 1999, 2000, 2001, 2002, 2003, 2006
# Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify
@ -391,6 +391,7 @@ setup_xfail "ia64-*-*"
# emulation tries to write pe-specific information to the PE headers
# in the output bfd, but it's not a PE bfd (it's an srec bfd)
setup_xfail "*-*-cygwin*" "*-*-mingw*" "*-*-pe*" "*-*-winnt*"
setup_xfail "score-*-*"
run_srec_test $test1 "tmpdir/sr1.o tmpdir/sr2.o"
@ -422,5 +423,6 @@ setup_xfail "alpha*-*-netbsd*"
setup_xfail "hppa*-*-*"
setup_xfail "ia64-*-*"
setup_xfail "*-*-cygwin*" "*-*-mingw*" "*-*-pe*" "*-*-winnt*"
setup_xfail "score-*-*"
run_srec_test $test2 "tmpdir/sr3.o"

10
opcodes/ChangeLog
View File

@ -1,3 +1,13 @@
2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
* score-dis.c: New file.
* score-opc.h: New file.
* Makefile.am: Add Score files.
* Makefile.in: Regenerate.
* configure.in: Add support for Score target.
* configure: Regenerate.
* disassemble.c: Add support for Score target.
2006-09-16 Nick Clifton <nickc@redhat.com>
Pedro Alves <pedro_alves@portugalmail.pt>

8
opcodes/Makefile.am
View File

@ -41,6 +41,7 @@ HFILES = \
mcore-opc.h \
mt-desc.h mt-opc.h \
openrisc-desc.h openrisc-opc.h \
score-opc.h \
sh-opc.h \
sh64-opc.h \
sysdep.h \
@ -162,6 +163,7 @@ CFILES = \
s390-mkopc.c \
s390-opc.c \
s390-dis.c \
score-dis.c \
sh-dis.c \
sh64-dis.c \
sh64-opc.c \
@ -293,6 +295,7 @@ ALL_MACHINES = \
ppc-opc.lo \
s390-dis.lo \
s390-opc.lo \
score-dis.lo \
sh-dis.lo \
sh64-dis.lo \
sh64-opc.lo \
@ -936,6 +939,11 @@ s390-opc.lo: s390-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/s390.h \
s390-dis.lo: s390-dis.c $(INCDIR)/ansidecl.h sysdep.h \
config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \
$(INCDIR)/opcode/s390.h
score-dis.lo: score-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h score-opc.h \
$(INCDIR)/bfdlink.h opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
$(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/score.h \
$(INCDIR)/elf/reloc-macros.h
sh-dis.lo: sh-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
sh-opc.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/dis-asm.h
sh64-dis.lo: sh64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \

8
opcodes/Makefile.in
View File

@ -254,6 +254,7 @@ HFILES = \
mcore-opc.h \
mt-desc.h mt-opc.h \
openrisc-desc.h openrisc-opc.h \
score-opc.h \
sh-opc.h \
sh64-opc.h \
sysdep.h \
@ -376,6 +377,7 @@ CFILES = \
s390-mkopc.c \
s390-opc.c \
s390-dis.c \
score-dis.c \
sh-dis.c \
sh64-dis.c \
sh64-opc.c \
@ -507,6 +509,7 @@ ALL_MACHINES = \
ppc-opc.lo \
s390-dis.lo \
s390-opc.lo \
score-dis.lo \
sh-dis.lo \
sh64-dis.lo \
sh64-opc.lo \
@ -1473,6 +1476,11 @@ s390-opc.lo: s390-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/s390.h \
s390-dis.lo: s390-dis.c $(INCDIR)/ansidecl.h sysdep.h \
config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \
$(INCDIR)/opcode/s390.h
score-dis.lo: score-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h score-opc.h \
$(INCDIR)/bfdlink.h opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
$(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/score.h \
$(INCDIR)/elf/reloc-macros.h
sh-dis.lo: sh-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
sh-opc.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/dis-asm.h
sh64-dis.lo: sh64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \

6
opcodes/configure vendored
View File

@ -5230,8 +5230,9 @@ INCINTL=
XGETTEXT=
GMSGFMT=
POSUB=
if test -f ../intl/config.intl; then
. ../intl/config.intl
if test -f ../intl/config.intl; then
. ../intl/config.intl
fi
echo "$as_me:$LINENO: checking whether NLS is requested" >&5
echo $ECHO_N "checking whether NLS is requested... $ECHO_C" >&6
@ -6571,6 +6572,7 @@ if test x${all_targets} = xfalse ; then
bfd_romp_arch) ;;
bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
bfd_s390_arch) ta="$ta s390-dis.lo s390-opc.lo" ;;
bfd_score_arch) ta="$ta score-dis.lo" ;;
bfd_sh_arch)
# We can't decide what we want just from the CPU family.
# We want SH5 support unless a specific version of sh is

1
opcodes/configure.in
View File

@ -201,6 +201,7 @@ if test x${all_targets} = xfalse ; then
bfd_romp_arch) ;;
bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
bfd_s390_arch) ta="$ta s390-dis.lo s390-opc.lo" ;;
bfd_score_arch) ta="$ta score-dis.lo" ;;
bfd_sh_arch)
# We can't decide what we want just from the CPU family.
# We want SH5 support unless a specific version of sh is

11
opcodes/disassemble.c
View File

@ -1,6 +1,6 @@
/* Select disassembly routine for specified architecture.
Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2004, 2005 Free Software Foundation, Inc.
2004, 2005, 2006 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@ -64,6 +64,7 @@
#define ARCH_powerpc
#define ARCH_rs6000
#define ARCH_s390
#define ARCH_score
#define ARCH_sh
#define ARCH_sparc
#define ARCH_tic30
@ -326,6 +327,14 @@ disassembler (abfd)
disassemble = print_insn_s390;
break;
#endif
#ifdef ARCH_score
case bfd_arch_score:
if (bfd_big_endian (abfd))
disassemble = print_insn_big_score;
else
disassemble = print_insn_little_score;
break;
#endif
#ifdef ARCH_sh
case bfd_arch_sh:
disassemble = print_insn_sh;

504
opcodes/score-dis.c Normal file
View File

@ -0,0 +1,504 @@
/* Instruction printing code for Score
Copyright 2006 Free Software Foundation, Inc.
Contributed by:
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
This file is part of libopcodes.
This program is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#include "sysdep.h"
#include "dis-asm.h"
#define DEFINE_TABLE
#include "score-opc.h"
#include "opintl.h"
#include "bfd.h"
/* FIXME: This shouldn't be done here. */
#include "elf-bfd.h"
#include "elf/internal.h"
#include "elf/score.h"
#ifndef streq
#define streq(a,b) (strcmp ((a), (b)) == 0)
#endif
#ifndef strneq
#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
#endif
#ifndef NUM_ELEM
#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
#endif
typedef struct
{
const char *name;
const char *description;
const char *reg_names[32];
} score_regname;
static score_regname regnames[] =
{
{"gcc", "Select register names used by GCC",
{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
"r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20",
"r21", "r22", "r23", "r24", "r25", "r26", "r27", "gp", "r29", "r30", "r31"}},
};
static unsigned int regname_selected = 0;
#define NUM_SCORE_REGNAMES NUM_ELEM (regnames)
#define score_regnames regnames[regname_selected].reg_names
/* Print one instruction from PC on INFO->STREAM.
Return the size of the instruction. */
static int
print_insn_score32 (bfd_vma pc, struct disassemble_info *info, long given)
{
struct score_opcode *insn;
void *stream = info->stream;
fprintf_ftype func = info->fprintf_func;
for (insn = score_opcodes; insn->assembler; insn++)
{
if ((insn->mask & 0xffff0000) && (given & insn->mask) == insn->value)
{
char *c;
for (c = insn->assembler; *c; c++)
{
if (*c == '%')
{
switch (*++c)
{
case 'j':
{
int target;
if (info->flags & INSN_HAS_RELOC)
pc = 0;
target = (pc & 0xfe000000) | (given & 0x01fffffe);
(*info->print_address_func) (target, info);
}
break;
case 'b':
{
/* Sign-extend a 20-bit number. */
#define SEXT20(x) ((((x) & 0xfffff) ^ (~ 0x7ffff)) + 0x80000)
int disp = ((given & 0x01ff8000) >> 5) | (given & 0x3fe);
int target = (pc + SEXT20 (disp));
(*info->print_address_func) (target, info);
}
break;
case '0':
case '1':
case '2':
case '3':
case '4':
case '5':
case '6':
case '7':
case '8':
case '9':
{
int bitstart = *c++ - '0';
int bitend = 0;
while (*c >= '0' && *c <= '9')
bitstart = (bitstart * 10) + *c++ - '0';
switch (*c)
{
case '-':
c++;
while (*c >= '0' && *c <= '9')
bitend = (bitend * 10) + *c++ - '0';
if (!bitend)
abort ();
switch (*c)
{
case 'r':
{
long reg;
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
func (stream, "%s", score_regnames[reg]);
}
break;
case 'd':
{
long reg;
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
func (stream, "%ld", reg);
}
break;
case 'i':
{
long reg;
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
reg = ((reg ^ (1 << (bitend - bitstart))) -
(1 << (bitend - bitstart)));
if (((given & insn->mask) == 0x0c00000a) /* ldc1 */
|| ((given & insn->mask) == 0x0c000012) /* ldc2 */
|| ((given & insn->mask) == 0x0c00001c) /* ldc3 */
|| ((given & insn->mask) == 0x0c00000b) /* stc1 */
|| ((given & insn->mask) == 0x0c000013) /* stc2 */
|| ((given & insn->mask) == 0x0c00001b)) /* stc3 */
reg <<= 2;
func (stream, "%ld", reg);
}
break;
case 'x':
{
long reg;
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
func (stream, "%lx", reg);
}
break;
default:
abort ();
}
break;
case '`':
c++;
if ((given & (1 << bitstart)) == 0)
func (stream, "%c", *c);
break;
case '\'':
c++;
if ((given & (1 << bitstart)) != 0)
func (stream, "%c", *c);
break;
default:
abort ();
}
break;
default:
abort ();
}
}
}
else
func (stream, "%c", *c);
}
return 4;
}
}
#if (SCORE_SIMULATOR_ACTIVE)
func (stream, _("<illegal instruction>"));
return 4;
#endif
abort ();
}
static void
print_insn_parallel_sym (struct disassemble_info *info)
{
void *stream = info->stream;
fprintf_ftype func = info->fprintf_func;
/* 10: 0000 nop!
4 space + 1 colon + 1 space + 1 tab + 8 opcode + 2 space + 1 tab.
FIXME: the space number is not accurate. */
func (stream, "%s", " ||\n \t \t");
}
/* Print one instruction from PC on INFO->STREAM.
Return the size of the instruction. */
static int
print_insn_score16 (bfd_vma pc, struct disassemble_info *info, long given)
{
struct score_opcode *insn;
void *stream = info->stream;
fprintf_ftype func = info->fprintf_func;
given &= 0xffff;
for (insn = score_opcodes; insn->assembler; insn++)
{
if (!(insn->mask & 0xffff0000) && (given & insn->mask) == insn->value)
{
char *c = insn->assembler;
info->bytes_per_chunk = 2;
info->bytes_per_line = 4;
given &= 0xffff;
for (; *c; c++)
{
if (*c == '%')
{
switch (*++c)
{
case 'j':
{
int target;
if (info->flags & INSN_HAS_RELOC)
pc = 0;
target = (pc & 0xfffff000) | (given & 0x00000ffe);
(*info->print_address_func) (target, info);
}
break;
case 'b':
{
/* Sign-extend a 9-bit number. */
#define SEXT9(x) ((((x) & 0x1ff) ^ (~ 0xff)) + 0x100)
int disp = (given & 0xff) << 1;
int target = (pc + SEXT9 (disp));
(*info->print_address_func) (target, info);
}
break;
case '0':
case '1':
case '2':
case '3':
case '4':
case '5':
case '6':
case '7':
case '8':
case '9':
{
int bitstart = *c++ - '0';
int bitend = 0;
while (*c >= '0' && *c <= '9')
bitstart = (bitstart * 10) + *c++ - '0';
switch (*c)
{
case '-':
{
long reg;
c++;
while (*c >= '0' && *c <= '9')
bitend = (bitend * 10) + *c++ - '0';
if (!bitend)
abort ();
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
switch (*c)
{
case 'R':
func (stream, "%s", score_regnames[reg + 16]);
break;
case 'r':
func (stream, "%s", score_regnames[reg]);
break;
case 'd':
if (*(c + 1) == '\0')
func (stream, "%ld", reg);
else
{
c++;
if (*c == '1')
func (stream, "%ld", reg << 1);
else if (*c == '2')
func (stream, "%ld", reg << 2);
}
break;
case 'x':
if (*(c + 1) == '\0')
func (stream, "%lx", reg);
else
{
c++;
if (*c == '1')
func (stream, "%lx", reg << 1);
else if (*c == '2')
func (stream, "%lx", reg << 2);
}
break;
case 'i':
reg = ((reg ^ (1 << bitend)) - (1 << bitend));
func (stream, "%ld", reg);
break;
default:
abort ();
}
}
break;
case '\'':
c++;
if ((given & (1 << bitstart)) != 0)
func (stream, "%c", *c);
break;
default:
abort ();
}
}
break;
default:
abort ();
}
}
else
func (stream, "%c", *c);
}
return 2;
}
}
#if (SCORE_SIMULATOR_ACTIVE)
func (stream, _("<illegal instruction>"));
return 2;
#endif
/* No match. */
abort ();
}
/* NOTE: There are no checks in these routines that
the relevant number of data bytes exist. */
static int
print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
{
unsigned char b[4];
long given;
long ridparity;
int status;
bfd_boolean insn_pce_p = FALSE;
bfd_boolean insn_16_p = FALSE;
info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
if (pc & 0x2)
{
info->bytes_per_chunk = 2;
status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
b[3] = b[2] = 0;
insn_16_p = TRUE;
}
else
{
info->bytes_per_chunk = 4;
status = info->read_memory_func (pc, (bfd_byte *) & b[0], 4, info);
if (status != 0)
{
info->bytes_per_chunk = 2;
status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
b[3] = b[2] = 0;
insn_16_p = TRUE;
}
}
if (status != 0)
{
info->memory_error_func (status, pc, info);
return -1;
}
if (little)
{
given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
}
else
{
given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
}
if ((given & 0x80008000) == 0x80008000)
{
insn_pce_p = FALSE;
insn_16_p = FALSE;
}
else if ((given & 0x8000) == 0x8000)
{
insn_pce_p = TRUE;
}
else
{
insn_16_p = TRUE;
}
/* 16 bit instruction. */
if (insn_16_p)
{
if (little)
{
given = b[0] | (b[1] << 8);
}
else
{
given = (b[0] << 8) | b[1];
}
status = print_insn_score16 (pc, info, given);
}
/* pce instruction. */
else if (insn_pce_p)
{
long other;
given = (given & 0xFFFF0000) >> 16;
other = given & 0xFFFF;
status = print_insn_score16 (pc, info, given);
print_insn_parallel_sym (info);
status += print_insn_score16 (pc, info, other);
/* disassemble_bytes() will output 4 byte per chunk for pce instructio. */
info->bytes_per_chunk = 4;
}
/* 32 bit instruction. */
else
{
/* Get rid of parity. */
ridparity = (given & 0x7FFF);
ridparity |= (given & 0x7FFF0000) >> 1;
given = ridparity;
status = print_insn_score32 (pc, info, given);
}
return status;
}
int
print_insn_big_score (bfd_vma pc, struct disassemble_info *info)
{
return print_insn (pc, info, FALSE);
}
int
print_insn_little_score (bfd_vma pc, struct disassemble_info *info)
{
return print_insn (pc, info, TRUE);
}

487
opcodes/score-opc.h Normal file
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@ -0,0 +1,487 @@
/* Copyright 2006 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
struct score_opcode
{
unsigned long value;
unsigned long mask; /* Recognise instruction if (op & mask) == value. */
char *assembler; /* Disassembly string. */
};
/* Note: There is a partial ordering in this table - it must be searched from
the top to obtain a correct match. */
static struct score_opcode score_opcodes[] =
{
/* Score Instructions. */
{0x3800000a, 0x3e007fff, "abs\t\t%20-24r, %15-19r"},
{0x3800004b, 0x3e007fff, "abs.s\t\t%20-24r, %15-19r"},
{0x00000010, 0x3e0003ff, "add\t\t%20-24r, %15-19r, %10-14r"},
{0x00000011, 0x3e0003ff, "add.c\t\t%20-24r, %15-19r, %10-14r"},
{0x38000048, 0x3e0003ff, "add.s\t\t%20-24r, %15-19r, %10-14r"},
{0x00000012, 0x3e0003ff, "addc\t\t%20-24r, %15-19r, %10-14r"},
{0x00000013, 0x3e0003ff, "addc.c\t\t%20-24r, %15-19r, %10-14r"},
{0x02000000, 0x3e0e0001, "addi\t\t%20-24r, %1-16i"},
{0x02000001, 0x3e0e0001, "addi.c\t\t%20-24r, %1-16i"},
{0x0a000000, 0x3e0e0001, "addis\t\t%20-24r, %1-16d(0x%1-16x)"},
{0x0a000001, 0x3e0e0001, "addis.c\t\t%20-24r, %1-16d(0x%1-16x)"},
{0x10000000, 0x3e000001, "addri\t\t%20-24r, %15-19r, %1-14i"},
{0x10000001, 0x3e000001, "addri.c\t\t%20-24r, %15-19r, %1-14i"},
{0x00000009, 0x0000700f, "addc!\t\t%8-11r, %4-7r"},
{0x00002000, 0x0000700f, "add!\t\t%8-11r, %4-7r"},
{0x00006000, 0x00007087, "addei!\t\t%8-11r, %3-6d"},
{0x00000020, 0x3e0003ff, "and\t\t%20-24r, %15-19r, %10-14r"},
{0x00000021, 0x3e0003ff, "and.c\t\t%20-24r, %15-19r, %10-14r"},
{0x02080000, 0x3e0e0001, "andi\t\t%20-24r, 0x%1-16x"},
{0x02080001, 0x3e0e0001, "andi.c\t\t%20-24r, 0x%1-16x"},
{0x0a080000, 0x3e0e0001, "andis\t\t%20-24r, 0x%1-16x"},
{0x0a080001, 0x3e0e0001, "andis.c\t\t%20-24r, 0x%1-16x"},
{0x18000000, 0x3e000001, "andri\t\t%20-24r, %15-19r, 0x%1-14x"},
{0x18000001, 0x3e000001, "andri.c\t\t%20-24r, %15-19r,0x%1-14x"},
{0x00002004, 0x0000700f, "and!\t\t%8-11r, %4-7r"},
{0x08000000, 0x3e007c01, "bcs\t\t0x%b" },
{0x08000400, 0x3e007c01, "bcc\t\t0x%b" },
{0x08003800, 0x3e007c01, "bcnz\t\t0x%b" },
{0x08000001, 0x3e007c01, "bcsl\t\t0x%b" },
{0x08000401, 0x3e007c01, "bccl\t\t0x%b" },
{0x08003801, 0x3e007c01, "bcnzl\t\t0x%b" },
{0x00004000, 0x00007f00, "bcs!\t\t0x%b" },
{0x00004100, 0x00007f00, "bcc!\t\t0x%b" },
{0x00004e00, 0x00007f00, "bcnz!\t\t0x%b" },
{0x08001000, 0x3e007c01, "beq\t\t0x%b" },
{0x08001001, 0x3e007c01, "beql\t\t0x%b" },
{0x00004400, 0x00007f00, "beq!\t\t0x%b" },
{0x08000800, 0x3e007c01, "bgtu\t\t0x%b" },
{0x08001800, 0x3e007c01, "bgt\t\t0x%b" },
{0x08002000, 0x3e007c01, "bge\t\t0x%b" },
{0x08000801, 0x3e007c01, "bgtul\t\t0x%b" },
{0x08001801, 0x3e007c01, "bgtl\t\t0x%b" },
{0x08002001, 0x3e007c01, "bgel\t\t0x%b" },
{0x00004200, 0x00007f00, "bgtu!\t\t0x%b" },
{0x00004600, 0x00007f00, "bgt!\t\t0x%b" },
{0x00004800, 0x00007f00, "bge!\t\t0x%b" },
{0x00000029, 0x3e0003ff, "bitclr.c\t%20-24r, %15-19r, 0x%10-14x"},
{0x0000002b, 0x3e0003ff, "bitset.c\t%20-24r, %15-19r, 0x%10-14x"},
{0x0000002d, 0x3e0003ff, "bittst.c\t%15-19r, 0x%10-14x"},
{0x0000002f, 0x3e0003ff, "bittgl.c\t%20-24r, %15-19r, 0x%10-14x"},
{0x00006004, 0x00007007, "bitclr!\t\t%8-11r, 0x%3-7x"},
{0x3800000c, 0x3e0003ff, "bitrev\t\t%20-24r, %15-19r,%10-14r"},
{0x00006005, 0x00007007, "bitset!\t\t%8-11r, 0x%3-7x"},
{0x00006006, 0x00007007, "bittst!\t\t%8-11r, 0x%3-7x"},
{0x00006007, 0x00007007, "bittgl!\t\t%8-11r, 0x%3-7x"},
{0x08000c00, 0x3e007c01, "bleu\t\t0x%b" },
{0x08001c00, 0x3e007c01, "ble\t\t0x%b" },
{0x08002400, 0x3e007c01, "blt\t\t0x%b" },
{0x08000c01, 0x3e007c01, "bleul\t\t0x%b" },
{0x08001c01, 0x3e007c01, "blel\t\t0x%b" },
{0x08002401, 0x3e007c01, "bltl\t\t0x%b" },
{0x08003c01, 0x3e007c01, "bl\t\t0x%b" },
{0x00004300, 0x00007f00, "bleu!\t\t0x%b" },
{0x00004700, 0x00007f00, "ble!\t\t0x%b" },
{0x00004900, 0x00007f00, "blt!\t\t0x%b" },
{0x08002800, 0x3e007c01, "bmi\t\t0x%b" },
{0x08002801, 0x3e007c01, "bmil\t\t0x%b" },
{0x00004a00, 0x00007f00, "bmi!\t\t0x%b" },
{0x08001400, 0x3e007c01, "bne\t\t0x%b" },
{0x08001401, 0x3e007c01, "bnel\t\t0x%b" },
{0x00004500, 0x00007f00, "bne!\t\t0x%b" },
{0x08002c00, 0x3e007c01, "bpl\t\t0x%b" },
{0x08002c01, 0x3e007c01, "bpll\t\t0x%b" },
{0x00004b00, 0x00007f00, "bpl!\t\t0x%b" },
{0x00000008, 0x3e007fff, "brcs\t\t%15-19r" },
{0x00000408, 0x3e007fff, "brcc\t\t%15-19r" },
{0x00000808, 0x3e007fff, "brgtu\t\t%15-19r" },
{0x00000c08, 0x3e007fff, "brleu\t\t%15-19r" },
{0x00001008, 0x3e007fff, "breq\t\t%15-19r" },
{0x00001408, 0x3e007fff, "brne\t\t%15-19r" },
{0x00001808, 0x3e007fff, "brgt\t\t%15-19r" },
{0x00001c08, 0x3e007fff, "brle\t\t%15-19r" },
{0x00002008, 0x3e007fff, "brge\t\t%15-19r" },
{0x00002408, 0x3e007fff, "brlt\t\t%15-19r" },
{0x00002808, 0x3e007fff, "brmi\t\t%15-19r" },
{0x00002c08, 0x3e007fff, "brpl\t\t%15-19r" },
{0x00003008, 0x3e007fff, "brvs\t\t%15-19r" },
{0x00003408, 0x3e007fff, "brvc\t\t%15-19r" },
{0x00003808, 0x3e007fff, "brcnz\t\t%15-19r" },
{0x00003c08, 0x3e007fff, "br\t\t%15-19r" },
{0x00000009, 0x3e007fff, "brcsl\t\t%15-19r" },
{0x00000409, 0x3e007fff, "brccl\t\t%15-19r" },
{0x00000809, 0x3e007fff, "brgtul\t\t%15-19r" },
{0x00000c09, 0x3e007fff, "brleul\t\t%15-19r" },
{0x00001009, 0x3e007fff, "breql\t\t%15-19r" },
{0x00001409, 0x3e007fff, "brnel\t\t%15-19r" },
{0x00001809, 0x3e007fff, "brgtl\t\t%15-19r" },
{0x00001c09, 0x3e007fff, "brlel\t\t%15-19r" },
{0x00002009, 0x3e007fff, "brgel\t\t%15-19r" },
{0x00002409, 0x3e007fff, "brltl\t\t%15-19r" },
{0x00002809, 0x3e007fff, "brmil\t\t%15-19r" },
{0x00002c09, 0x3e007fff, "brpll\t\t%15-19r" },
{0x00003009, 0x3e007fff, "brvsl\t\t%15-19r" },
{0x00003409, 0x3e007fff, "brvcl\t\t%15-19r" },
{0x00003809, 0x3e007fff, "brcnzl\t\t%15-19r" },
{0x00003c09, 0x3e007fff, "brl\t\t%15-19r" },
{0x00000004, 0x00007f0f, "brcs!\t\t%4-7r" },
{0x00000104, 0x00007f0f, "brcc!\t\t%4-7r" },
{0x00000204, 0x00007f0f, "brgtu!\t\t%4-7r" },
{0x00000304, 0x00007f0f, "brleu!\t\t%4-7r" },
{0x00000404, 0x00007f0f, "breq!\t\t%4-7r" },
{0x00000504, 0x00007f0f, "brne!\t\t%4-7r" },
{0x00000604, 0x00007f0f, "brgt!\t\t%4-7r" },
{0x00000704, 0x00007f0f, "brle!\t\t%4-7r" },
{0x00000804, 0x00007f0f, "brge!\t\t%4-7r" },
{0x00000904, 0x00007f0f, "brlt!\t\t%4-7r" },
{0x00000a04, 0x00007f0f, "brmi!\t\t%4-7r" },
{0x00000b04, 0x00007f0f, "brpl!\t\t%4-7r" },
{0x00000c04, 0x00007f0f, "brvs!\t\t%4-7r" },
{0x00000d04, 0x00007f0f, "brvc!\t\t%4-7r" },
{0x00000e04, 0x00007f0f, "brcnz!\t\t%4-7r" },
{0x00000f04, 0x00007f0f, "br!\t\t%4-7r" },
{0x0000000c, 0x00007f0f, "brcsl!\t\t%4-7r" },
{0x0000010c, 0x00007f0f, "brccl!\t\t%4-7r" },
{0x0000020c, 0x00007f0f, "brgtul!\t\t%4-7r" },
{0x0000030c, 0x00007f0f, "brleul!\t\t%4-7r" },
{0x0000040c, 0x00007f0f, "breql!\t\t%4-7r" },
{0x0000050c, 0x00007f0f, "brnel!\t\t%4-7r" },
{0x0000060c, 0x00007f0f, "brgtl!\t\t%4-7r" },
{0x0000070c, 0x00007f0f, "brlel!\t\t%4-7r" },
{0x0000080c, 0x00007f0f, "brgel!\t\t%4-7r" },
{0x0000090c, 0x00007f0f, "brltl!\t\t%4-7r" },
{0x00000a0c, 0x00007f0f, "brmil!\t\t%4-7r" },
{0x00000b0c, 0x00007f0f, "brpll!\t\t%4-7r" },
{0x00000c0c, 0x00007f0f, "brvsl!\t\t%4-7r" },
{0x00000d0c, 0x00007f0f, "brvcl!\t\t%4-7r" },
{0x00000e0c, 0x00007f0f, "brcnzl!\t\t%4-7r" },
{0x00000f0c, 0x00007f0f, "brl!\t\t%4-7r" },
{0x08003000, 0x3e007c01, "bvs\t\t0x%b" },
{0x08003400, 0x3e007c01, "bvc\t\t0x%b" },
{0x08003001, 0x3e007c01, "bvsl\t\t0x%b" },
{0x08003401, 0x3e007c01, "bvcl\t\t0x%b" },
{0x00004c00, 0x00007f00, "bvs!\t\t0x%b" },
{0x00004d00, 0x00007f00, "bvc!\t\t0x%b" },
{0x00004f00, 0x00007f00, "b!\t\t0x%b" },
{0x08003c00, 0x3e007c01, "b\t\t0x%b" },
{0x30000000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30100000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30200000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30300000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30400000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30800000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30900000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30a00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30b00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30c00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30d00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x30e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x31000000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x31100000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x31800000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x31a00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x31b00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x31c00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x31d00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x31e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x31f00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
{0x38000000, 0x3ff003ff, "mad\t\t%15-19r, %10-14r"},
{0x38000020, 0x3ff003ff, "madu\t\t%15-19r, %10-14r"},
{0x38000080, 0x3ff003ff, "mad.f\t\t%15-19r, %10-14r"},
{0x38000001, 0x3ff003ff, "msb\t\t%15-19r, %10-14r"},
{0x38000021, 0x3ff003ff, "msbu\t\t%15-19r, %10-14r"},
{0x38000081, 0x3ff003ff, "msb.f\t\t%15-19r, %10-14r"},
{0x38000102, 0x3ff003ff, "mazl\t\t%15-19r, %10-14r"},
{0x38000182, 0x3ff003ff, "mazl.f\t\t%15-19r, %10-14r"},
{0x38000002, 0x3ff003ff, "madl\t\t%15-19r, %10-14r"},
{0x380000c2, 0x3ff003ff, "madl.fs\t\t%15-19r, %10-14r"},
{0x38000303, 0x3ff003ff, "mazh\t\t%15-19r, %10-14r"},
{0x38000383, 0x3ff003ff, "mazh.f\t\t%15-19r, %10-14r"},
{0x38000203, 0x3ff003ff, "madh\t\t%15-19r, %10-14r"},
{0x380002c3, 0x3ff003ff, "madh.fs\t\t%15-19r, %10-14r"},
{0x38000007, 0x3e0003ff, "max\t\t%20-24r, %15-19r, %10-14r"},
{0x38000006, 0x3e0003ff, "min\t\t%20-24r, %15-19r, %10-14r"},
{0x38000104, 0x3ff003ff, "mszl\t\t%15-19r, %10-14r"},
{0x38000184, 0x3ff003ff, "mszl.f\t\t%15-19r, %10-14r"},
{0x38000004, 0x3ff003ff, "msbl\t\t%15-19r, %10-14r"},
{0x380000c4, 0x3ff003ff, "msbl.fs\t\t%15-19r, %10-14r"},
{0x38000305, 0x3ff003ff, "mszh\t\t%15-19r, %10-14r"},
{0x38000385, 0x3ff003ff, "mszh.f\t\t%15-19r, %10-14r"},
{0x38000205, 0x3ff003ff, "msbh\t\t%15-19r, %10-14r"},
{0x380002c5, 0x3ff003ff, "msbh.fs\t\t%15-19r, %10-14r"},
{0x3800004e, 0x3e0003ff, "sll.s\t\t%20-24r, %15-19r, %10-14r"},
{0x38000049, 0x3e0003ff, "sub.s\t\t%20-24r, %15-19r, %10-14r"},
{0x3800000d, 0x3e007fff, "clz\t\t%20-24r, %15-19r"},
{0x38000000, 0x3e000000, "ceinst\t\t%20-24d, %15-19r, %10-14r, %5-9d, %0-4d"},
{0x00000019, 0x3ff003ff, "cmpteq.c\t\t%15-19r, %10-14r"},
{0x00100019, 0x3ff003ff, "cmptmi.c\t\t%15-19r, %10-14r"},
{0x00300019, 0x3ff003ff, "cmp.c\t\t%15-19r, %10-14r"},
{0x0000001b, 0x3ff07fff, "cmpzteq.c\t%15-19r"},
{0x0010001b, 0x3ff07fff, "cmpztmi.c\t%15-19r"},
{0x0030001b, 0x3ff07fff, "cmpz.c\t\t%15-19r"},
{0x02040001, 0x3e0e0001, "cmpi.c\t\t%20-24r, %1-16i"},
{0x00002003, 0x0000700f, "cmp!\t\t%8-11r, %4-7r"},
{0x0c00000c, 0x3e00001f, "cop1\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"},
{0x0c000014, 0x3e00001f, "cop2\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"},
{0x0c00001c, 0x3e00001f, "cop3\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"},
{0x00000044, 0x3e0003ff, "div\t\t%15-19r, %10-14r"},
{0x00000046, 0x3e0003ff, "divu\t\t%15-19r, %10-14r"},
{0x0c0000a4, 0x3e0003ff, "drte" },
{0x00000058, 0x3e0003ff, "extsb\t\t%20-24r, %15-19r"},
{0x00000059, 0x3e0003ff, "extsb.c\t\t%20-24r, %15-19r"},
{0x0000005a, 0x3e0003ff, "extsh\t\t%20-24r, %15-19r"},
{0x0000005b, 0x3e0003ff, "extsh.c\t\t%20-24r, %15-19r"},
{0x0000005c, 0x3e0003ff, "extzb\t\t%20-24r, %15-19r"},
{0x0000005d, 0x3e0003ff, "extzb.c\t\t%20-24r, %15-19r"},
{0x0000005e, 0x3e0003ff, "extzh\t\t%20-24r, %15-19r"},
{0x0000005f, 0x3e0003ff, "extzh.c\t\t%20-24r, %15-19r"},
{0x04000001, 0x3e000001, "jl\t\t0x%j"},
{0x00003001, 0x00007001, "jl!\t\t0x%j" },
{0x00003000, 0x00007001, "j!\t\t0x%j" },
{0x04000000, 0x3e000001, "j\t\t0x%j"},
{0x26000000, 0x3e000000, "lb\t\t%20-24r, [%15-19r, %0-14i]"},
{0x2c000000, 0x3e000000, "lbu\t\t%20-24r, [%15-19r, %0-14i]"},
{0x06000003, 0x3e000007, "lb\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x06000006, 0x3e000007, "lbu\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x0e000003, 0x3e000007, "lb\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x0e000006, 0x3e000007, "lbu\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x0000200b, 0x0000700f, "lbu!\t\t%8-11r, [%4-7r]"},
{0x00007003, 0x00007007, "lbup!\t\t%8-11r, %3-7d"},
{0x00000060, 0x3e0003ff, "lcb\t\t[%15-19r]+"},
{0x00000062, 0x3e0003ff, "lcw\t\t%20-24r, [%15-19r]+"},
{0x00000066, 0x3e0003ff, "lce\t\t%20-24r, [%15-19r]+"},
{0x0c00000a, 0x3e00001f, "ldc1\t\tc%15-19r, [%20-24r, %5-14i]"},
{0x0c000012, 0x3e00001f, "ldc2\t\tc%15-19r, [%20-24r, %5-14i]"},
{0x0c00001a, 0x3e00001f, "ldc3\t\tc%15-19r, [%20-24r, %5-14i]"},
{0x22000000, 0x3e000000, "lh\t\t%20-24r, [%15-19r, %0-14i]"},
{0x24000000, 0x3e000000, "lhu\t\t%20-24r, [%15-19r, %0-14i]"},
{0x06000001, 0x3e000007, "lh\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x06000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x0e000001, 0x3e000007, "lh\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x0e000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x00002009, 0x0000700f, "lh!\t\t%8-11r, [%4-7r]"},
{0x00007001, 0x00007007, "lhp!\t\t%8-11r, %3-7d1"},
{0x020c0000, 0x3e0e0000, "ldi\t\t%20-24r, 0x%1-16x(%1-16i)"},
{0x0a0c0000, 0x3e0e0000, "ldis\t\t%20-24r, 0x%1-16x(%1-16i)"},
{0x00005000, 0x00007000, "ldiu!\t\t%8-11r, %0-7d"},
{0x0000000c, 0x3e0003ff, "alw\t\t%20-24r, [%15-19r]"},
{0x20000000, 0x3e000000, "lw\t\t%20-24r, [%15-19r, %0-14i]"},
{0x06000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x0e000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x00002008, 0x0000700f, "lw!\t\t%8-11r, [%4-7r]"},
{0x00007000, 0x00007007, "lwp!\t\t%8-11r, %3-7d2"},
{0x0000100b, 0x0000700f, "madh.fs!\t\t%8-11r, %4-7r"},
{0x0000100a, 0x0000700f, "madl.fs!\t\t%8-11r, %4-7r"},
{0x00001005, 0x0000700f, "madu!\t\t%8-11r, %4-7r"},
{0x00001004, 0x0000700f, "mad.f!\t\t%8-11r, %4-7r"},
{0x00001009, 0x0000700f, "mazh.f!\t\t%8-11r, %4-7r"},
{0x00001008, 0x0000700f, "mazl.f!\t\t%8-11r, %4-7r"},
{0x00000448, 0x3e007fff, "mfcel\t\t%20-24r"},
{0x00001001, 0x00007f0f, "mfcel!\t\t%4-7r"},
{0x00000848, 0x3e007fff, "mfceh\t\t%20-24r"},
{0x00001101, 0x00007f0f, "mfceh!\t\t%4-7r"},
{0x00000c48, 0x3e007fff, "mfcehl\t\t%20-24r, %15-19r"},
{0x00000048, 0x3e0003ff, "mfce\t\t%20-24r, er%10-14d"},
{0x00000050, 0x3e0003ff, "mfsr\t\t%20-24r, sr%10-14d"},
{0x0c000001, 0x3e00001f, "mfcr\t\t%20-24r, c%15-19r"},
{0x0c000009, 0x3e00001f, "mfc1\t\t%20-24r, c%15-19r"},
{0x0c000011, 0x3e00001f, "mfc2\t\t%20-24r, c%15-19r"},
{0x0c000019, 0x3e00001f, "mfc3\t\t%20-24r, c%15-19r"},
{0x0c00000f, 0x3e00001f, "mfcc1\t\t%20-24r, c%15-19r"},
{0x0c000017, 0x3e00001f, "mfcc2\t\t%20-24r, c%15-19r"},
{0x0c00001f, 0x3e00001f, "mfcc3\t\t%20-24r, c%15-19r"},
{0x00000002, 0x0000700f, "mhfl!\t\t%8-11R, %4-7r"},
{0x00000001, 0x0000700f, "mlfh!\t\t%8-11r, %4-7R"},
{0x00001006, 0x0000700f, "msb.f!\t\t%8-11r, %4-7r"},
{0x0000100f, 0x0000700f, "msbh.fs!\t\t%8-11r, %4-7r"},
{0x0000100e, 0x0000700f, "msbl.fs!\t\t%8-11r, %4-7r"},
{0x00001007, 0x0000700f, "msbu!\t\t%8-11r, %4-7r"},
{0x0000100d, 0x0000700f, "mszh.f!\t\t%8-11r, %4-7r"},
{0x0000100c, 0x0000700f, "mszl.f!\t\t%8-11r, %4-7r"},
{0x0000044a, 0x3e007fff, "mtcel\t\t%20-24r"},
{0x00001000, 0x00007f0f, "mtcel!\t\t%4-7r"},
{0x0000084a, 0x3e007fff, "mtceh\t\t%20-24r"},
{0x00001100, 0x00007f0f, "mtceh!\t\t%4-7r"},
{0x00000c4a, 0x3e007fff, "mtcehl\t\t%20-24r, %15-19r"},
{0x0000004a, 0x3e0003ff, "mtce\t\t%20-24r, er%10-14d"},
{0x00000052, 0x3e0003ff, "mtsr\t\t%15-19r, sr%10-14d"},
{0x0c000000, 0x3e00001f, "mtcr\t\t%20-24r, c%15-19r"},
{0x0c000008, 0x3e00001f, "mtc1\t\t%20-24r, c%15-19r"},
{0x0c000010, 0x3e00001f, "mtc2\t\t%20-24r, c%15-19r"},
{0x0c000018, 0x3e00001f, "mtc3\t\t%20-24r, c%15-19r"},
{0x0c00000e, 0x3e00001f, "mtcc1\t\t%20-24r, c%15-19r"},
{0x0c000016, 0x3e00001f, "mtcc2\t\t%20-24r, c%15-19r"},
{0x0c00001e, 0x3e00001f, "mtcc3\t\t%20-24r, c%15-19r"},
{0x00000040, 0x3e0003ff, "mul\t\t%15-19r, %10-14r"},
{0x00000040, 0x3e0003ff, "maz\t\t%15-19r, %10-14r"},
{0x00000041, 0x3e0003ff, "mul.f\t\t%15-19r, %10-14r"},
{0x00000041, 0x3e0003ff, "maz.f\t\t%15-19r, %10-14r"},
{0x00001002, 0x0000700f, "mul.f!\t\t%8-11r, %4-7r"},
{0x00000042, 0x3e0003ff, "mulu\t\t%15-19r, %10-14r"},
{0x00000042, 0x3e0003ff, "mazu\t\t%15-19r, %10-14r"},
{0x00001003, 0x0000700f, "mulu!\t\t%8-11r, %4-7r"},
{0x00000056, 0x3e007fff, "mvcs\t\t%20-24r, %15-19r"},
{0x00000456, 0x3e007fff, "mvcc\t\t%20-24r, %15-19r"},
{0x00000856, 0x3e007fff, "mvgtu\t\t%20-24r, %15-19r"},
{0x00000c56, 0x3e007fff, "mvleu\t\t%20-24r, %15-19r"},
{0x00001056, 0x3e007fff, "mveq\t\t%20-24r, %15-19r"},
{0x00001456, 0x3e007fff, "mvne\t\t%20-24r, %15-19r"},
{0x00001856, 0x3e007fff, "mvgt\t\t%20-24r, %15-19r"},
{0x00001c56, 0x3e007fff, "mvle\t\t%20-24r, %15-19r"},
{0x00002056, 0x3e007fff, "mvge\t\t%20-24r, %15-19r"},
{0x00002456, 0x3e007fff, "mvlt\t\t%20-24r, %15-19r"},
{0x00002856, 0x3e007fff, "mvmi\t\t%20-24r, %15-19r"},
{0x00002c56, 0x3e007fff, "mvpl\t\t%20-24r, %15-19r"},
{0x00003056, 0x3e007fff, "mvvs\t\t%20-24r, %15-19r"},
{0x00003456, 0x3e007fff, "mvvc\t\t%20-24r, %15-19r"},
{0x00003c56, 0x3e007fff, "mv\t\t%20-24r, %15-19r"},
{0x00000003, 0x0000700f, "mv!\t\t%8-11r, %4-7r"},
{0x0000001e, 0x3e0003ff, "neg\t\t%20-24r, %10-14r" },
{0x0000001f, 0x3e0003ff, "neg.c\t\t%20-24r, %10-14r" },
{0x00002002, 0x0000700f, "neg!\t\t%8-11r, %4-7r"},
{0x00000000, 0x3e0003ff, "nop" },
{0x00000024, 0x3e0003ff, "not\t\t%20-24r, %15-19r" },
{0x00000025, 0x3e0003ff, "not.c\t\t%20-24r, %15-19r" },
{0x00000000, 0x0000700f, "nop!" },
{0x00002006, 0x0000700f, "not!\t\t%8-11r, %4-7r"},
{0x00000022, 0x3e0003ff, "or\t\t%20-24r, %15-19r, %10-14r"},
{0x00000023, 0x3e0003ff, "or.c\t\t%20-24r, %15-19r, %10-14r"},
{0x020a0000, 0x3e0e0001, "ori\t\t%20-24r, 0x%1-16x"},
{0x020a0001, 0x3e0e0001, "ori.c\t\t%20-24r, 0x%1-16x"},
{0x0a0a0000, 0x3e0e0001, "oris\t\t%20-24r, 0x%1-16x"},
{0x0a0a0001, 0x3e0e0001, "oris.c\t\t%20-24r, 0x%1-16x"},
{0x1a000000, 0x3e000001, "orri\t\t%20-24r, %15-19r, 0x%1-14x"},
{0x1a000001, 0x3e000001, "orri.c\t\t%20-24r, %15-19r, 0x%1-14x"},
{0x00002005, 0x0000700f, "or!\t\t%8-11r, %4-7r"},
{0x0000000a, 0x3e0003ff, "pflush"},
{0x0000208a, 0x0000708f, "pop!\t\t%8-11R, [%4-6r]"},
{0x0000200a, 0x0000700f, "pop!\t\t%8-11r, [%4-7r]"},
{0x0000208e, 0x0000708f, "push!\t\t%8-11R, [%4-6r]"},
{0x0000200e, 0x0000700f, "push!\t\t%8-11r, [%4-7r]"},
{0x00000038, 0x3e0003ff, "ror\t\t%20-24r, %15-19r, %10-14r"},
{0x00000039, 0x3e0003ff, "ror.c\t\t%20-24r, %15-19r, %10-14r"},
{0x0000003b, 0x3e0003ff, "rorc.c\t\t%20-24r, %15-19r, %10-14r"},
{0x0000003c, 0x3e0003ff, "rol\t\t%20-24r, %15-19r, %10-14r"},
{0x0000003d, 0x3e0003ff, "rol.c\t\t%20-24r, %15-19r, %10-14r"},
{0x0000003f, 0x3e0003ff, "rolc.c\t\t%20-24r, %15-19r, %10-14r"},
{0x00000078, 0x3e0003ff, "rori\t\t%20-24r, %15-19r, %10-14d"},
{0x00000079, 0x3e0003ff, "rori.c\t\t%20-24r, %15-19r, %10-14d"},
{0x0000007b, 0x3e0003ff, "roric.c\t\t%20-24r, %15-19r, %10-14d"},
{0x0000007c, 0x3e0003ff, "roli\t\t%20-24r, %15-19r, %10-14d"},
{0x0000007d, 0x3e0003ff, "roli.c\t\t%20-24r, %15-19r, %10-14d"},
{0x0000007f, 0x3e0003ff, "rolic.c\t\t%20-24r, %15-19r, %10-14d"},
{0x0c000084, 0x3e0003ff, "rte" },
{0x2e000000, 0x3e000000, "sb\t\t%20-24r, [%15-19r, %0-14i]"},
{0x06000007, 0x3e000007, "sb\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x0e000007, 0x3e000007, "sb\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x0000200f, 0x0000700f, "sb!\t\t%8-11r, [%4-7r]"},
{0x00007007, 0x00007007, "sbp!\t\t%8-11r, %3-7d"},
{0x0000000e, 0x3e0003ff, "asw\t\t%20-24r, [%15-19r]"},
{0x00000068, 0x3e0003ff, "scb\t\t%20-24r, [%15-19r]+"},
{0x0000006a, 0x3e0003ff, "scw\t\t%20-24r, [%15-19r]+"},
{0x0000006e, 0x3e0003ff, "sce\t\t[%15-19r]+"},
{0x00000006, 0x3e0003ff, "sdbbp\t\t%15-19d"},
{0x00006002, 0x00007007, "sdbbp!\t\t%3-7d"},
{0x2a000000, 0x3e000000, "sh\t\t%20-24r, [%15-19r, %0-14i]"},
{0x06000005, 0x3e000007, "sh\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x0e000005, 0x3e000007, "sh\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x0000200d, 0x0000700f, "sh!\t\t%8-11r, [%4-7r]"},
{0x00007005, 0x00007007, "shp!\t\t%8-11r, %3-7d1"},
{0x0c0000c4, 0x3e0003ff, "sleep" },
{0x00000030, 0x3e0003ff, "sll\t\t%20-24r, %15-19r, %10-14r"},
{0x00000031, 0x3e0003ff, "sll.c\t\t%20-24r, %15-19r, %10-14r"},
{0x00000070, 0x3e0003ff, "slli\t\t%20-24r, %15-19r, %10-14d"},
{0x00000071, 0x3e0003ff, "slli.c\t\t%20-24r, %15-19r, %10-14d"},
{0x00000008, 0x0000700f, "sll!\t\t%8-11r, %4-7r"},
{0x00006001, 0x00007007, "slli!\t\t%8-11r, %3-7d"},
{0x00000034, 0x3e0003ff, "srl\t\t%20-24r, %15-19r, %10-14r"},
{0x00000035, 0x3e0003ff, "srl.c\t\t%20-24r, %15-19r, %10-14r"},
{0x00000036, 0x3e0003ff, "sra\t\t%20-24r, %15-19r, %10-14r"},
{0x00000037, 0x3e0003ff, "sra.c\t\t%20-24r, %15-19r, %10-14r"},
{0x00000074, 0x3e0003ff, "srli\t\t%20-24r, %15-19r, %10-14d"},
{0x00000075, 0x3e0003ff, "srli.c\t\t%20-24r, %15-19r, %10-14d"},
{0x00000076, 0x3e0003ff, "srai\t\t%20-24r, %15-19r, %10-14d"},
{0x00000077, 0x3e0003ff, "srai.c\t\t%20-24r, %15-19r, %10-14d"},
{0x0000000a, 0x0000700f, "srl!\t\t%8-11r, %4-7r"},
{0x00006003, 0x00007007, "srli!\t\t%8-11r, %3-7d"},
{0x0000000b, 0x0000700f, "sra!\t\t%8-11r, %4-7r"},
{0x0c00000b, 0x3e00001f, "stc1\t\tc%15-19r, [%20-24r, %5-14i]"},
{0x0c000013, 0x3e00001f, "stc2\t\tc%15-19r, [%20-24r, %5-14i]"},
{0x0c00001b, 0x3e00001f, "stc3\t\tc%15-19r, [%20-24r, %5-14i]"},
{0x00000014, 0x3e0003ff, "sub\t\t%20-24r, %15-19r, %10-14r"},
{0x00000015, 0x3e0003ff, "sub.c\t\t%20-24r, %15-19r, %10-14r"},
{0x00000016, 0x3e0003ff, "subc\t\t%20-24r, %15-19r, %10-14r"},
{0x00000017, 0x3e0003ff, "subc.c\t\t%20-24r, %15-19r, %10-14r"},
{0x00002001, 0x0000700f, "sub!\t\t%8-11r, %4-7r"},
{0x00006080, 0x00007087, "subei!\t\t%8-11r, %3-6d"},
{0x28000000, 0x3e000000, "sw\t\t%20-24r, [%15-19r, %0-14i]"},
{0x06000004, 0x3e000007, "sw\t\t%20-24r, [%15-19r, %3-14i]+"},
{0x0e000004, 0x3e000007, "sw\t\t%20-24r, [%15-19r]+, %3-14i"},
{0x0000200c, 0x0000700f, "sw!\t\t%8-11r, [%4-7r]"},
{0x00007004, 0x00007007, "swp!\t\t%8-11r, %3-7d2"},
{0x00000002, 0x3e0003ff, "syscall\t\t%10-24d"},
{0x00000054, 0x3e007fff, "tcs" },
{0x00000454, 0x3e007fff, "tcc" },
{0x00003854, 0x3e007fff, "tcnz" },
{0x00000005, 0x00007f0f, "tcs!" },
{0x00000105, 0x00007f0f, "tcc!" },
{0x00000e05, 0x00007f0f, "tcnz!" },
{0x00001054, 0x3e007fff, "teq" },
{0x00000405, 0x00007f0f, "teq!" },
{0x00000854, 0x3e007fff, "tgtu" },
{0x00001854, 0x3e007fff, "tgt" },
{0x00002054, 0x3e007fff, "tge" },
{0x00000205, 0x00007f0f, "tgtu!" },
{0x00000605, 0x00007f0f, "tgt!" },
{0x00000805, 0x00007f0f, "tge!" },
{0x00000c54, 0x3e007fff, "tleu" },
{0x00001c54, 0x3e007fff, "tle" },
{0x00002454, 0x3e007fff, "tlt" },
{0x0c000004, 0x3e0003ff, "stlb" },
{0x0c000024, 0x3e0003ff, "mftlb" },
{0x0c000044, 0x3e0003ff, "mtptlb" },
{0x0c000064, 0x3e0003ff, "mtrtlb" },
{0x00000305, 0x00007f0f, "tleu!" },
{0x00000705, 0x00007f0f, "tle!" },
{0x00000905, 0x00007f0f, "tlt!" },
{0x00002854, 0x3e007fff, "tmi" },
{0x00000a05, 0x00007f0f, "tmi!" },
{0x00001454, 0x3e007fff, "tne" },
{0x00000505, 0x00007f0f, "tne!" },
{0x00002c54, 0x3e007fff, "tpl" },
{0x00000b05, 0x00007f0f, "tpl!" },
{0x00000004, 0x3e007fff, "trapcs\t\t%15-19d"},
{0x00000404, 0x3e007fff, "trapcc\t\t%15-19d"},
{0x00000804, 0x3e007fff, "trapgtu\t\t%15-19d"},
{0x00000c04, 0x3e007fff, "trapleu\t\t%15-19d"},
{0x00001004, 0x3e007fff, "trapeq\t\t%15-19d"},
{0x00001404, 0x3e007fff, "trapne\t\t%15-19d"},
{0x00001804, 0x3e007fff, "trapgt\t\t%15-19d"},
{0x00001c04, 0x3e007fff, "traple\t\t%15-19d"},
{0x00002004, 0x3e007fff, "trapge\t\t%15-19d"},
{0x00002404, 0x3e007fff, "traplt\t\t%15-19d"},
{0x00002804, 0x3e007fff, "trapmi\t\t%15-19d"},
{0x00002c04, 0x3e007fff, "trappl\t\t%15-19d"},
{0x00003004, 0x3e007fff, "trapvs\t\t%15-19d"},
{0x00003404, 0x3e007fff, "trapvc\t\t%15-19d"},
{0x00003c04, 0x3e007fff, "trap\t\t%15-19d"},
{0x00003c54, 0x3e007fff, "tset" },
{0x00000f05, 0x00007f0f, "tset!" },
{0x00003054, 0x3e007fff, "tvs" },
{0x00003454, 0x3e007fff, "tvc" },
{0x00000c05, 0x00007f0f, "tvs!" },
{0x00000d05, 0x00007f0f, "tvc!" },
{0x00000026, 0x3e0003ff, "xor\t\t%20-24r, %15-19r, %10-14r"},
{0x00000027, 0x3e0003ff, "xor.c\t\t%20-24r, %15-19r, %10-14r"},
{0x00002007, 0x0000700f, "xor!\t\t%8-11r, %4-7r"}
};