mirror of
https://github.com/darlinghq/darling-gdb.git
synced 2025-02-14 14:29:10 +00:00
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (do_load_left, do_load_right): Move to be immediately
following do_load.
(do_store_left, do_store_right): Move to be immediately following
do_store.
This commit is contained in:
Chris Demetriou
parent
603a98e7a1
commit
1c47a468ec
@ -1,3 +1,10 @@
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2002-02-27 Chris Demetriou <cgd@broadcom.com>
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* mips.igen (do_load_left, do_load_right): Move to be immediately
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following do_load.
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(do_store_left, do_store_right): Move to be immediately following
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do_store.
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2002-02-27 Chris Demetriou <cgd@broadcom.com>
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* mips.igen (mipsV): New model name. Also, add it to
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@ -1429,6 +1429,92 @@
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return (memval >> (8 * byte));
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}
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:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
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{
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address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
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address_word reverseendian = (ReverseEndian ? -1 : 0);
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address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
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unsigned int byte;
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unsigned int word;
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address_word paddr;
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int uncached;
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unsigned64 memval;
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address_word vaddr;
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int nr_lhs_bits;
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int nr_rhs_bits;
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unsigned_word lhs_mask;
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unsigned_word temp;
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vaddr = base + offset;
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AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
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paddr = (paddr ^ (reverseendian & mask));
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if (BigEndianMem == 0)
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paddr = paddr & ~access;
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/* compute where within the word/mem we are */
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byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
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word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
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nr_lhs_bits = 8 * byte + 8;
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nr_rhs_bits = 8 * access - 8 * byte;
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/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
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/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
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(long) ((unsigned64) vaddr >> 32), (long) vaddr,
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(long) ((unsigned64) paddr >> 32), (long) paddr,
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word, byte, nr_lhs_bits, nr_rhs_bits); */
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LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
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if (word == 0)
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{
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/* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
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temp = (memval << nr_rhs_bits);
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}
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else
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{
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/* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
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temp = (memval >> nr_lhs_bits);
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}
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lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
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rt = (rt & ~lhs_mask) | (temp & lhs_mask);
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/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
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(long) ((unsigned64) memval >> 32), (long) memval,
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(long) ((unsigned64) temp >> 32), (long) temp,
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(long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
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(long) (rt >> 32), (long) rt); */
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return rt;
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}
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:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
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{
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address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
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address_word reverseendian = (ReverseEndian ? -1 : 0);
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address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
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unsigned int byte;
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address_word paddr;
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int uncached;
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unsigned64 memval;
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address_word vaddr;
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vaddr = base + offset;
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AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
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/* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
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paddr = (paddr ^ (reverseendian & mask));
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if (BigEndianMem != 0)
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paddr = paddr & ~access;
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byte = ((vaddr & mask) ^ (bigendiancpu & mask));
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/* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
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LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
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/* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
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(long) paddr, byte, (long) paddr, (long) memval); */
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{
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unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
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rt &= ~screen;
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rt |= (memval >> (8 * byte)) & screen;
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}
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return rt;
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}
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100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
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"lb r<RT>, <OFFSET>(r<BASE>)"
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@ -1667,63 +1753,6 @@
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}
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:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
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{
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address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
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address_word reverseendian = (ReverseEndian ? -1 : 0);
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address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
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unsigned int byte;
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unsigned int word;
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address_word paddr;
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int uncached;
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unsigned64 memval;
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address_word vaddr;
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int nr_lhs_bits;
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int nr_rhs_bits;
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unsigned_word lhs_mask;
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unsigned_word temp;
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vaddr = base + offset;
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AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
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paddr = (paddr ^ (reverseendian & mask));
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if (BigEndianMem == 0)
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paddr = paddr & ~access;
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/* compute where within the word/mem we are */
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byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
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word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
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nr_lhs_bits = 8 * byte + 8;
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nr_rhs_bits = 8 * access - 8 * byte;
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/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
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/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
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(long) ((unsigned64) vaddr >> 32), (long) vaddr,
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(long) ((unsigned64) paddr >> 32), (long) paddr,
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word, byte, nr_lhs_bits, nr_rhs_bits); */
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LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
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if (word == 0)
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{
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/* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
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temp = (memval << nr_rhs_bits);
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}
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else
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{
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/* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
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temp = (memval >> nr_lhs_bits);
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}
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lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
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rt = (rt & ~lhs_mask) | (temp & lhs_mask);
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/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
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(long) ((unsigned64) memval >> 32), (long) memval,
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(long) ((unsigned64) temp >> 32), (long) temp,
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(long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
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(long) (rt >> 32), (long) rt); */
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return rt;
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}
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100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
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"lwl r<RT>, <OFFSET>(r<BASE>)"
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*mipsI:
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@ -1739,37 +1768,6 @@
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}
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:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
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{
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address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
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address_word reverseendian = (ReverseEndian ? -1 : 0);
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address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
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unsigned int byte;
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address_word paddr;
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int uncached;
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unsigned64 memval;
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address_word vaddr;
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vaddr = base + offset;
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AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
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/* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
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paddr = (paddr ^ (reverseendian & mask));
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if (BigEndianMem != 0)
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paddr = paddr & ~access;
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byte = ((vaddr & mask) ^ (bigendiancpu & mask));
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/* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
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LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
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/* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
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(long) paddr, byte, (long) paddr, (long) memval); */
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{
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unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
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rt &= ~screen;
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rt |= (memval >> (8 * byte)) & screen;
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}
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return rt;
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}
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100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
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"lwr r<RT>, <OFFSET>(r<BASE>)"
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*mipsI:
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@ -2063,6 +2061,7 @@
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}
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}
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:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
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{
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address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
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@ -2086,6 +2085,72 @@
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StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
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}
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:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
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{
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address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
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address_word reverseendian = (ReverseEndian ? -1 : 0);
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address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
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unsigned int byte;
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unsigned int word;
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address_word paddr;
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int uncached;
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unsigned64 memval;
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address_word vaddr;
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int nr_lhs_bits;
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int nr_rhs_bits;
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vaddr = base + offset;
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AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
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paddr = (paddr ^ (reverseendian & mask));
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if (BigEndianMem == 0)
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paddr = paddr & ~access;
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/* compute where within the word/mem we are */
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byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
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word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
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nr_lhs_bits = 8 * byte + 8;
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nr_rhs_bits = 8 * access - 8 * byte;
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/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
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/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
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(long) ((unsigned64) vaddr >> 32), (long) vaddr,
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(long) ((unsigned64) paddr >> 32), (long) paddr,
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word, byte, nr_lhs_bits, nr_rhs_bits); */
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if (word == 0)
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{
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memval = (rt >> nr_rhs_bits);
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}
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else
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{
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memval = (rt << nr_lhs_bits);
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}
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/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
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(long) ((unsigned64) rt >> 32), (long) rt,
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(long) ((unsigned64) memval >> 32), (long) memval); */
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StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
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}
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:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
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{
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address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
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address_word reverseendian = (ReverseEndian ? -1 : 0);
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address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
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unsigned int byte;
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address_word paddr;
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int uncached;
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unsigned64 memval;
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address_word vaddr;
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vaddr = base + offset;
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AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
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paddr = (paddr ^ (reverseendian & mask));
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if (BigEndianMem != 0)
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paddr &= ~access;
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byte = ((vaddr & mask) ^ (bigendiancpu & mask));
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memval = (rt << (byte * 8));
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StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
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}
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101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
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"sb r<RT>, <OFFSET>(r<BASE>)"
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@ -2556,53 +2621,6 @@
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}
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:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
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{
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address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
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address_word reverseendian = (ReverseEndian ? -1 : 0);
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address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
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unsigned int byte;
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unsigned int word;
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address_word paddr;
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int uncached;
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unsigned64 memval;
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address_word vaddr;
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int nr_lhs_bits;
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int nr_rhs_bits;
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vaddr = base + offset;
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AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
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paddr = (paddr ^ (reverseendian & mask));
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if (BigEndianMem == 0)
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paddr = paddr & ~access;
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/* compute where within the word/mem we are */
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byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
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word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
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nr_lhs_bits = 8 * byte + 8;
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nr_rhs_bits = 8 * access - 8 * byte;
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/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
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/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
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(long) ((unsigned64) vaddr >> 32), (long) vaddr,
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(long) ((unsigned64) paddr >> 32), (long) paddr,
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word, byte, nr_lhs_bits, nr_rhs_bits); */
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if (word == 0)
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{
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memval = (rt >> nr_rhs_bits);
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}
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else
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{
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memval = (rt << nr_lhs_bits);
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}
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/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
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(long) ((unsigned64) rt >> 32), (long) rt,
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(long) ((unsigned64) memval >> 32), (long) memval); */
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StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
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}
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101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
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"swl r<RT>, <OFFSET>(r<BASE>)"
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*mipsI:
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@ -2618,27 +2636,6 @@
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}
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:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
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{
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address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
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address_word reverseendian = (ReverseEndian ? -1 : 0);
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address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
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unsigned int byte;
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address_word paddr;
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int uncached;
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unsigned64 memval;
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address_word vaddr;
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vaddr = base + offset;
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AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
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paddr = (paddr ^ (reverseendian & mask));
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if (BigEndianMem != 0)
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paddr &= ~access;
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byte = ((vaddr & mask) ^ (bigendiancpu & mask));
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memval = (rt << (byte * 8));
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StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
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}
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101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
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"swr r<RT>, <OFFSET>(r<BASE>)"
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*mipsI:
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