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* config/tc-arc.c (byte_order): Provide explicit initial value.
This commit is contained in:
David Edelsohn
parent
403d21d28f
commit
2356dab3bc
@ -16,7 +16,7 @@
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include <stdio.h>
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#include <ctype.h>
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@ -31,7 +31,6 @@ static arc_insn arc_insert_operand PARAMS ((arc_insn,
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const struct arc_operand *, int,
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const struct arc_operand_value *,
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offsetT, char *, unsigned int));
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static int delay_slot_type PARAMS ((arc_insn));
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static void arc_common PARAMS ((int));
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static void arc_cpu PARAMS ((int));
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/*static void arc_rename PARAMS ((int));*/
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@ -77,7 +76,7 @@ const char FLT_CHARS[] = "rRsSfFdD";
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/* Byte order. */
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extern int target_big_endian;
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const char *arc_target_format = DEFAULT_TARGET_FORMAT;
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static int byte_order;
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static int byte_order = DEFAULT_BYTE_ORDER;
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/* One of bfd_mach_arc_xxx. */
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static int arc_mach_type = bfd_mach_arc_base;
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@ -278,18 +277,6 @@ arc_insert_operand (insn, operand, mods, reg, val, file, line)
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return insn;
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}
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/* Return the delay slot type for INSN (or -1 if it isn't a branch). */
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/* ??? This is a quick hack. May wish to later generalize this concept
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to record all suffixes the insn contains (for various warnings, etc.). */
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static int
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delay_slot_type (arc_insn insn)
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{
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if ((insn >> 27) >= 4 && (insn >> 27) <= 7)
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return (insn & 0x60) >> 5;
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return -1;
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}
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/* We need to keep a list of fixups. We can't simply generate them as
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we go, because that would require us to first create the frag, and
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that would screw up references to ``.''. */
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@ -301,7 +288,9 @@ struct arc_fixup
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expressionS exp;
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};
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#define MAX_INSN_FIXUPS 5
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#define MAX_FIXUPS 5
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#define MAX_SUFFIXES 5
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/* This routine is called for each instruction to be assembled. */
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@ -329,17 +318,20 @@ md_assemble (str)
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/* The instructions are stored in lists hashed by the first letter (though
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we needn't care how they're hashed). Get the first in the list. */
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opcode = arc_opcode_asm_list (str);
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opcode = arc_opcode_lookup_asm (str);
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/* Keep looking until we find a match. */
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start = str;
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for ( ; opcode != NULL; opcode = ARC_OPCODE_NEXT_ASM (opcode))
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{
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int past_opcode_p;
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int past_opcode_p, fc, num_suffixes;
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char *syn;
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struct arc_fixup fixups[MAX_INSN_FIXUPS];
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int fc,limm_reloc_p;
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struct arc_fixup fixups[MAX_FIXUPS];
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/* Used as a sanity check. If we need a limm reloc, make sure we ask
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for an extra 4 bytes from frag_more. */
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int limm_reloc_p;
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const struct arc_operand_value *insn_suffixes[MAX_SUFFIXES];
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/* Is this opcode supported by the selected cpu? */
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if (! arc_opcode_supported (opcode))
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@ -351,9 +343,7 @@ md_assemble (str)
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insn = opcode->value;
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fc = 0;
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past_opcode_p = 0;
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/* Used as a sanity check. If we need a limm reloc, make sure we ask
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for an extra 4 bytes from frag_more. */
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num_suffixes = 0;
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limm_reloc_p = 0;
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/* We don't check for (*str != '\0') here because we want to parse
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@ -471,7 +461,7 @@ md_assemble (str)
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suffix_end = arc_suffixes + arc_suffixes_count;
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for (suffix = suf;
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suffix < suffix_end && strcmp (suffix->name, suf->name) == 0;
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suffix++)
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++suffix)
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{
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if (arc_operands[suffix->type].fmt == *syn)
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{
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@ -490,9 +480,14 @@ md_assemble (str)
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}
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++syn;
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if (!found)
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/* There's nothing to do except go on to try the next one.
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??? This test can be deleted when we're done. */
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;
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; /* Wrong type. Just go on to try next insn entry. */
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else
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{
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if (num_suffixes == MAX_SUFFIXES)
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as_bad ("too many suffixes");
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else
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insn_suffixes[num_suffixes++] = suffix;
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}
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}
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else
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/* This is either a register or an expression of some kind. */
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@ -548,7 +543,7 @@ md_assemble (str)
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else
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{
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/* We need to generate a fixup for this expression. */
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if (fc >= MAX_INSN_FIXUPS)
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if (fc >= MAX_FIXUPS)
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as_fatal ("too many fixups");
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fixups[fc].exp = exp;
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@ -605,6 +600,7 @@ md_assemble (str)
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}
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/* If we're at the end of the syntax string, we're done. */
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/* FIXME: try to move this to a separate function. */
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if (*syn == '\0')
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{
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int i;
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@ -625,18 +621,53 @@ md_assemble (str)
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/* Is there a limm value? */
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limm_p = arc_opcode_limm_p (&limm);
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/* Putting an insn with a limm value in a delay slot is supposed to
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be legal, but let's warn the user anyway. Ditto for 8 byte jumps
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with delay slots. */
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/* Perform various error and warning tests. */
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{
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static int in_delay_slot_p = 0;
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int this_insn_delay_slot_type = delay_slot_type (insn);
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static int prev_insn_needs_cc_nop_p = 0;
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/* delay slot type seen */
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int delay_slot_type = ARC_DELAY_NONE;
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/* conditional execution flag seen */
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int conditional = 0;
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/* 1 if condition codes are being set */
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int cc_set_p = 0;
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/* 1 if conditional branch, including `b' "branch always" */
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int cond_branch_p = opcode->flags & ARC_OPCODE_COND_BRANCH;
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int need_cc_nop_p = 0;
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for (i = 0; i < num_suffixes; ++i)
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{
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switch (arc_operands[insn_suffixes[i]->type].fmt)
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{
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case 'n' :
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delay_slot_type = insn_suffixes[i]->value;
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break;
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case 'q' :
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conditional = insn_suffixes[i]->value;
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break;
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case 'f' :
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cc_set_p = 1;
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break;
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}
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}
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/* Putting an insn with a limm value in a delay slot is supposed to
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be legal, but let's warn the user anyway. Ditto for 8 byte
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jumps with delay slots. */
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if (in_delay_slot_p && limm_p)
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as_warn ("8 byte instruction in delay slot");
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if (this_insn_delay_slot_type > 0 && limm_p)
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if (delay_slot_type != ARC_DELAY_NONE && limm_p)
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as_warn ("8 byte jump instruction with delay slot");
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in_delay_slot_p = (this_insn_delay_slot_type > 0) && !limm_p;
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in_delay_slot_p = (delay_slot_type != ARC_DELAY_NONE) && !limm_p;
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/* Warn when a conditional branch immediately follows a set of
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the condition codes. Note that this needn't be done if the
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insn that sets the condition codes uses a limm. */
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if (cond_branch_p && conditional != 0 /* 0 = "always" */
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&& prev_insn_needs_cc_nop_p)
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as_warn ("conditional branch follows set of flags");
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prev_insn_needs_cc_nop_p = cc_set_p && !limm_p;
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}
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/* Write out the instruction.
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@ -1167,8 +1198,10 @@ md_pcrel_from (fixP)
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{
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if (fixP->fx_addsy != (symbolS *) NULL
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&& ! S_IS_DEFINED (fixP->fx_addsy))
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/* Return offset from PC to delay slot. Offsets are from there. */
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return 4;
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{
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/* The symbol is undefined. Let the linker figure it out. */
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return 0;
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}
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/* Return the address of the delay slot. */
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return fixP->fx_frag->fr_address + fixP->fx_where + fixP->fx_size;
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@ -1243,9 +1276,10 @@ get_arc_exp_reloc_type (data_p, default_type, exp, expnew)
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that, we determine the correct reloc code and put it back in the fixup. */
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int
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md_apply_fix (fixP, valueP)
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md_apply_fix3 (fixP, valueP, seg)
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fixS *fixP;
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valueT *valueP;
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segT seg;
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{
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/*char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;*/
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valueT value;
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@ -1267,7 +1301,16 @@ md_apply_fix (fixP, valueP)
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fixP->fx_done = 1;
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}
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else if (fixP->fx_pcrel)
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value = *valueP;
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{
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value = *valueP;
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/* ELF relocations are against symbols.
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If this symbol is in a different section then we need to leave it for
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the linker to deal with. Unfortunately, md_pcrel_from can't tell,
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so we have to undo it's effects here. */
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if (S_IS_DEFINED (fixP->fx_addsy)
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&& S_GET_SEGMENT (fixP->fx_addsy) != seg)
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value += md_pcrel_from (fixP);
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}
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else
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{
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value = fixP->fx_offset;
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@ -1413,10 +1456,11 @@ tc_gen_reloc (section, fixP)
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fixP->fx_r_type, bfd_get_reloc_code_name (fixP->fx_r_type));
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return NULL;
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}
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reloc->addend = fixP->fx_addnumber;
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assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
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reloc->addend = fixP->fx_addnumber;
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return reloc;
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}
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