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[ARC] Add ldbit for nps
This commit adds the ldbit instruction for the NPS-400. The ldbit instruction uses the same encoding as the ld instruction, but sets the ZZ field to 11 (which is a reserved setting), and sets the AA field to 1 or 2 for the x2 and x4 flags respectively.
This commit is contained in:
Graham Markall
Andrew Burgess
parent
9ba75c8847
commit
28215275a6
@ -1,3 +1,8 @@
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2016-06-13 Graham Markall <graham.markall@embecosm.com>
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* testsuite/gas/arc/nps400-6.s: Add tests of ldbit.
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* testsuite/gas/arc/nps400-6.d: Likewise.
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2016-06-13 Graham Markall <graham.markall@embecosm.com>
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* testsuite/gas/arc/nps400-6.s: Add tests of hash, tr, utf8, e4by, and
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@ -308,3 +308,51 @@ Disassembly of section .text:
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604: 595d 0000 e4by r0,r1,r2,0,0,0,0x4
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608: 5cbd 394c e4by r7,r12,r13,0x1,0x2,0x3,0x4
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60c: 5cbd a7ff e4by r20,r12,r13,0x7,0x7,0x7,0x7
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610: 1100 0980 ldbit.di r0,\[r1\]
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614: 1101 0980 ldbit.di r0,\[r1,1\]
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618: 12ff 8981 ldbit.di r1,\[r2,-1\]
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61c: 1601 7983 ffff ffff ldbit.di r3,\[0xffffffff,1\]
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624: 1600 7984 1234 5678 ldbit.di r4,\[0x12345678\]
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62c: 2636 81c5 ldbit.di r5,\[r6,r7\]
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630: 2136 9f88 ffff ffff ldbit.di r8,\[r9,0xffffffff\]
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638: 2636 f2ca ffff ffff ldbit.di r10,\[0xffffffff,r11\]
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640: 1100 09c0 ldbit.di.cl r0,\[r1\]
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644: 1101 09c0 ldbit.di.cl r0,\[r1,1\]
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648: 12ff 89c1 ldbit.di.cl r1,\[r2,-1\]
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64c: 1601 79c3 ffff ffff ldbit.di.cl r3,\[0xffffffff,1\]
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654: 1600 79c4 1234 5678 ldbit.di.cl r4,\[0x12345678\]
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65c: 2637 81c5 ldbit.di.cl r5,\[r6,r7\]
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660: 2137 9f88 ffff ffff ldbit.di.cl r8,\[r9,0xffffffff\]
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668: 2637 f2ca ffff ffff ldbit.di.cl r10,\[0xffffffff,r11\]
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670: 1100 0b80 ldbit.x2.di r0,\[r1\]
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674: 1101 0b80 ldbit.x2.di r0,\[r1,1\]
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678: 12ff 8b81 ldbit.x2.di r1,\[r2,-1\]
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67c: 1601 7b83 ffff ffff ldbit.x2.di r3,\[0xffffffff,1\]
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684: 1600 7b84 1234 5678 ldbit.x2.di r4,\[0x12345678\]
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68c: 2676 81c5 ldbit.x2.di r5,\[r6,r7\]
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690: 2176 9f88 ffff ffff ldbit.x2.di r8,\[r9,0xffffffff\]
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698: 2676 f2ca ffff ffff ldbit.x2.di r10,\[0xffffffff,r11\]
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6a0: 1100 0bc0 ldbit.x2.di.cl r0,\[r1\]
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6a4: 1101 0bc0 ldbit.x2.di.cl r0,\[r1,1\]
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6a8: 12ff 8bc1 ldbit.x2.di.cl r1,\[r2,-1\]
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6ac: 1601 7bc3 ffff ffff ldbit.x2.di.cl r3,\[0xffffffff,1\]
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6b4: 1600 7bc4 1234 5678 ldbit.x2.di.cl r4,\[0x12345678\]
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6bc: 2677 81c5 ldbit.x2.di.cl r5,\[r6,r7\]
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6c0: 2177 9f88 ffff ffff ldbit.x2.di.cl r8,\[r9,0xffffffff\]
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6c8: 2677 f2ca ffff ffff ldbit.x2.di.cl r10,\[0xffffffff,r11\]
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6d0: 1100 0d80 ldbit.x4.di r0,\[r1\]
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6d4: 1101 0d80 ldbit.x4.di r0,\[r1,1\]
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6d8: 12ff 8d81 ldbit.x4.di r1,\[r2,-1\]
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6dc: 1601 7d83 ffff ffff ldbit.x4.di r3,\[0xffffffff,1\]
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6e4: 1600 7d84 1234 5678 ldbit.x4.di r4,\[0x12345678\]
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6ec: 26b6 81c5 ldbit.x4.di r5,\[r6,r7\]
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6f0: 21b6 9f88 ffff ffff ldbit.x4.di r8,\[r9,0xffffffff\]
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6f8: 26b6 f2ca ffff ffff ldbit.x4.di r10,\[0xffffffff,r11\]
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700: 1100 0dc0 ldbit.x4.di.cl r0,\[r1\]
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704: 1101 0dc0 ldbit.x4.di.cl r0,\[r1,1\]
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708: 12ff 8dc1 ldbit.x4.di.cl r1,\[r2,-1\]
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70c: 1601 7dc3 ffff ffff ldbit.x4.di.cl r3,\[0xffffffff,1\]
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714: 1600 7dc4 1234 5678 ldbit.x4.di.cl r4,\[0x12345678\]
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71c: 26b7 81c5 ldbit.x4.di.cl r5,\[r6,r7\]
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720: 21b7 9f88 ffff ffff ldbit.x4.di.cl r8,\[r9,0xffffffff\]
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728: 26b7 f2ca ffff ffff ldbit.x4.di.cl r10,\[0xffffffff,r11\]
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@ -208,3 +208,21 @@
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e4by r0,r1,r2,0,0,0,4
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e4by r7,r12,r13,1,2,3,4
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e4by r20,r12,r13,7,7,7,7
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.macro ldbit_test mnem
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\mnem\() r0,[r1]
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\mnem\() r0,[r1,1]
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\mnem\() r1,[r2,-1]
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\mnem\() r3,[0xffffffff,1]
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\mnem\() r4,[0x12345678]
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\mnem\() r5,[r6,r7]
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\mnem\() r8,[r9,0xffffffff]
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\mnem\() r10,[0xffffffff,r11]
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.endm
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ldbit_test ldbit.di
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ldbit_test ldbit.di.cl
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ldbit_test ldbit.x2.di
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ldbit_test ldbit.x2.di.cl
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ldbit_test ldbit.x4.di
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ldbit_test ldbit.x4.di.cl
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@ -1,3 +1,8 @@
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2016-06-13 Graham Markall <graham.markall@embecosm.com>
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* arc-nps400-tbl.h: Add ldbit instruction.
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* arc-opc.c: Add flag classes required for ldbit.
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2016-06-13 Graham Markall <graham.markall@embecosm.com>
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* arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
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@ -503,6 +503,27 @@ HASH_P(3, 0xC)
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/* addf<.f> 0,limm,u6 0011111001100011F111uuuuuu111110 */
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{ "addf", 0x3e63703e, 0xffff703f, ARC_OPCODE_NPS400, DPI, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
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/* ldbit<.x2|.x4>.di<.cl> a,[b] 00010bbb00000000SBBB10011XAAAAAA */
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{ "ldbit", 0x10000980, 0xf8ff8980, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, RB, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }},
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/* ldbit<.x2|.x4>.di<.cl> a,[b,s9] 00010bbbssssssssSBBB10011XAAAAAA */
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{ "ldbit", 0x10000980, 0xf8000980, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }},
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/* ldbit<.x2|.x4>.di<.cl> a,[limm] 0001011000000000011110011XAAAAAA */
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{ "ldbit", 0x16007980, 0xfffff980, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, LIMM, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }},
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/* ldbit<.x2|.x4>.di<.cl> a,[limm,s9] 00010110ssssssssS11110011XAAAAAA */
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{ "ldbit", 0x16007980, 0xff007980, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }},
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/* ldbit<.x2|.x4>.di<.cl> a,[b,c] 00100bbb0011011X1BBBCCCCCCAAAAAA */
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{ "ldbit", 0x20368000, 0xf83e8000, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, RB, RC, BRAKETdup }, { C_NPS_LDBIT_X_2, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL2 }},
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/* ldbit<.x2|.x4>.di<.cl> a,[b,limm] 00100bbb0011011X1BBB111110AAAAAA */
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{ "ldbit", 0x20368f80, 0xf83e8fc0, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, RB, LIMM, BRAKETdup }, { C_NPS_LDBIT_X_2, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL2 }},
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/* ldbit<.x2|.x4>.di<.cl> a,[limm,c] 001001100011011X1111CCCCCCAAAAAA */
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{ "ldbit", 0x2636f000, 0xff3ef000, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, LIMM, RC, BRAKETdup }, { C_NPS_LDBIT_X_2, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL2 }},
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/**** Pipeline Control Instructions ****/
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/* schd<.rw|.rd> */
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@ -1387,6 +1387,27 @@ const struct arc_flag_operand arc_flag_operands[] =
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#define F_NPS_P3 (F_NPS_P2 + 1)
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{ "p3", 0, 0, 0, 1 },
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#define F_NPS_LDBIT_DI (F_NPS_P3 + 1)
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{ "di", 0, 0, 0, 1 },
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#define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1)
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{ "cl", 1, 1, 6, 1 },
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#define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1)
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{ "cl", 1, 1, 16, 1 },
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#define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1)
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{ "x2", 1, 2, 9, 1 },
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#define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1)
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{ "x2", 1, 2, 22, 1 },
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#define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1)
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{ "x4", 2, 2, 9, 1 },
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#define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1)
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{ "x4", 2, 2, 22, 1 },
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};
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const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
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@ -1511,6 +1532,21 @@ const struct arc_flag_class arc_flag_classes[] =
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#define C_NPS_P3 (C_NPS_P2 + 1)
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{ F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }},
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#define C_NPS_LDBIT_DI (C_NPS_P3 + 1)
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{ F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }},
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#define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1)
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{ F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }},
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#define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1)
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{ F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }},
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#define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1)
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{ F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }},
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#define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1)
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{ F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }},
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};
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const unsigned char flags_none[] = { 0 };
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