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https://github.com/darlinghq/darling-gdb.git
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* simops.c Implement remaining 3 byte instructions.
Moving right along...
This commit is contained in:
Jeff Law
parent
f5f13c1d73
commit
2e35551c74
@ -1,5 +1,7 @@
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Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c Implement remaining 3 byte instructions.
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* simops.c: Implement remaining 2 byte instructions. Call
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abort for instructions we're not implementing now.
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@ -134,16 +134,19 @@ void OP_F2F2 ()
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State.regs[REG_MDR] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
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}
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/* mov */
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/* mov (am), dn */
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void OP_70 ()
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{
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State.regs[REG_D0 + ((insn & 0xc) >> 2)]
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= load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
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}
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/* mov */
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/* mov (d8,am), dn */
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void OP_F80000 ()
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{
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State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
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= load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
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+ SEXT8 (insn & 0xff)), 4);
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}
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/* mov */
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@ -176,7 +179,7 @@ void OP_FCB40000 ()
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/* mov (di,am), dn */
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void OP_F300 ()
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{
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State.regs[REG_D0 + ((insn & 0x30) >> 8)]
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State.regs[REG_D0 + ((insn & 0x300) >> 8)]
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= load_mem ((State.regs[REG_A0 + (insn & 0x3)]
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+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
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}
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@ -199,9 +202,12 @@ void OP_F000 ()
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= load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
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}
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/* mov */
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/* mov (d8,am), an */
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void OP_F82000 ()
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{
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State.regs[REG_A0 + ((insn & 0xc00) >> 10)]
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= load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
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+ SEXT8 (insn & 0xff)), 4);
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}
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/* mov */
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@ -234,7 +240,7 @@ void OP_FCB00000 ()
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/* mov (di,am), an*/
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void OP_F380 ()
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{
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State.regs[REG_A0 + ((insn & 0x30) >> 8)]
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State.regs[REG_A0 + ((insn & 0x300) >> 8)]
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= load_mem ((State.regs[REG_A0 + (insn & 0x3)]
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+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
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}
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@ -249,9 +255,12 @@ void OP_FCA00000 ()
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{
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}
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/* mov */
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/* mov (d8,am), sp */
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void OP_F8F000 ()
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{
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State.regs[REG_SP]
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= load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
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+ SEXT8 (insn & 0xff)), 4);
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}
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/* mov dm, (an) */
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@ -261,9 +270,12 @@ void OP_60 ()
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State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
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}
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/* mov */
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/* mov dm, (d8,an) */
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void OP_F81000 ()
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{
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store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
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+ SEXT8 (insn & 0xff)), 4,
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State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
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}
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/* mov */
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@ -298,7 +310,7 @@ void OP_F340 ()
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{
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store_mem ((State.regs[REG_A0 + (insn & 0x3)]
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+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
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State.regs[REG_D0 + ((insn & 0x30) >> 8)]);
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State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
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}
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/* mov dm, (abs16) */
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@ -319,9 +331,12 @@ void OP_F010 ()
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State.regs[REG_A0 + ((insn & 0xc) >> 2)]);
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}
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/* mov */
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/* mov am, (d8,an) */
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void OP_F83000 ()
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{
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store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
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+ SEXT8 (insn & 0xff)), 4,
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State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
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}
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/* mov */
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@ -356,7 +371,7 @@ void OP_F3C0 ()
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{
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store_mem ((State.regs[REG_A0 + (insn & 0x3)]
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+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
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State.regs[REG_A0 + ((insn & 0x30) >> 8)]);
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State.regs[REG_A0 + ((insn & 0x300) >> 8)]);
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}
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/* mov */
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@ -369,9 +384,11 @@ void OP_FC800000 ()
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{
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}
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/* mov */
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/* mov sp, (d8,an) */
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void OP_F8F400 ()
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{
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store_mem (State.regs[REG_A0 + ((insn & 0x300) >> 8)] + SEXT8 (insn & 0xff),
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4, State.regs[REG_SP]);
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}
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/* mov imm16, dn */
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@ -413,9 +430,12 @@ void OP_F040 ()
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= load_mem (State.regs[REG_A0 + (insn & 0x3)], 1);
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}
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/* movbu */
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/* movbu (d8,am), dn */
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void OP_F84000 ()
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{
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State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
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= load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
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+ SEXT8 (insn & 0xff)), 1);
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}
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/* movbu */
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@ -428,9 +448,11 @@ void OP_FC400000 ()
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{
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}
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/* movbu */
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/* movbu (d8,sp), dn */
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void OP_F8B800 ()
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{
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State.regs[REG_D0 + ((insn & 0x300) >> 8)]
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= load_mem ((State.regs[REG_SP] + SEXT8 (insn & 0xff)), 1);
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}
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/* movbu */
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@ -446,7 +468,7 @@ void OP_FCB80000 ()
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/* movbu (di,am), dn */
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void OP_F400 ()
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{
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State.regs[REG_D0 + ((insn & 0x30) >> 8)]
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State.regs[REG_D0 + ((insn & 0x300) >> 8)]
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= load_mem ((State.regs[REG_A0 + (insn & 0x3)]
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+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1);
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}
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@ -469,9 +491,12 @@ void OP_F050 ()
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State.regs[REG_D0 + (insn & 0x3)]);
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}
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/* movbu */
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/* movbu dm, (d8,an) */
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void OP_F85000 ()
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{
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store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
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+ SEXT8 (insn & 0xff)), 1,
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State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
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}
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/* movbu */
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@ -484,9 +509,11 @@ void OP_FC500000 ()
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{
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}
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/* movbu */
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/* movbu dm, (d8,sp) */
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void OP_F89200 ()
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{
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store_mem ((State.regs[REG_SP] + SEXT8 (insn & 0xff)), 1,
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State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
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}
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/* movbu */
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@ -504,7 +531,7 @@ void OP_F440 ()
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{
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store_mem ((State.regs[REG_A0 + (insn & 0x3)]
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+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1,
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State.regs[REG_D0 + ((insn & 0x30) >> 8)]);
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State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
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}
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/* movbu dm, (abs16) */
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@ -525,9 +552,12 @@ void OP_F060 ()
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= load_mem (State.regs[REG_A0 + (insn & 0x3)], 2);
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}
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/* movhu */
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/* movhu (d8,am), dn */
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void OP_F86000 ()
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{
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State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
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= load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
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+ SEXT8 (insn & 0xff)), 2);
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}
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/* movhu */
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@ -540,9 +570,11 @@ void OP_FC600000 ()
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{
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}
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/* movhu */
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/* movhu (d8,sp) dn */
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void OP_F8BC00 ()
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{
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State.regs[REG_D0 + ((insn & 0x300) >> 8)]
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= load_mem ((State.regs[REG_SP] + SEXT8 (insn & 0xff)), 2);
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}
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/* movhu */
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@ -558,7 +590,7 @@ void OP_FCBC0000 ()
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/* movhu (di,am), dn */
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void OP_F480 ()
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{
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State.regs[REG_D0 + ((insn & 0x30) >> 8)]
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State.regs[REG_D0 + ((insn & 0x300) >> 8)]
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= load_mem ((State.regs[REG_A0 + (insn & 0x3)]
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+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2);
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}
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@ -581,9 +613,12 @@ void OP_F070 ()
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State.regs[REG_D0 + (insn & 0x3)]);
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}
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/* movhu */
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/* movhu dm, (d8,an) */
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void OP_F87000 ()
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{
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store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
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+ SEXT8 (insn & 0xff)), 2,
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State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
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}
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/* movhu */
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@ -596,9 +631,11 @@ void OP_FC700000 ()
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{
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}
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/* movhu */
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/* movhu dm,(d8,sp) */
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void OP_F89300 ()
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{
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store_mem ((State.regs[REG_SP] + SEXT8 (insn & 0xff)), 2,
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State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
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}
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/* movhu */
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@ -616,7 +653,7 @@ void OP_F4C0 ()
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{
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store_mem ((State.regs[REG_A0 + (insn & 0x3)]
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+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2,
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State.regs[REG_D0 + ((insn & 0x30) >> 8)]);
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State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
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}
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/* movhu dm, (abs16) */
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@ -1559,9 +1596,16 @@ void OP_F200 ()
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PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
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}
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/* and */
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/* and imm8, dn */
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void OP_F8E000 ()
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{
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int n, z;
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State.regs[REG_D0 + ((insn & 0x300) >> 8)] &= (insn & 0xff);
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z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
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n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x8000000) != 0;
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
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}
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/* and */
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@ -1591,9 +1635,16 @@ void OP_F210 ()
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PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
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}
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/* or */
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/* or imm8, dn */
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void OP_F8E400 ()
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{
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int n, z;
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State.regs[REG_D0 + ((insn & 0x300) >> 8)] |= insn & 0xff;
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z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
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n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x8000000) != 0;
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
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}
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/* or */
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@ -1645,9 +1696,18 @@ void OP_F230 ()
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PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
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}
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/* btst */
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/* btst imm8, dn */
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void OP_F8EC00 ()
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{
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unsigned long temp;
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int z, n;
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temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
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temp &= (insn & 0xff);
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n = (temp & 0x80000000) != 0;
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z = (temp == 0);
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
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}
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/* btst */
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@ -1718,7 +1778,7 @@ void OP_FAF40000 ()
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{
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}
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/* asr */
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/* asr dm, dn */
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void OP_F2B0 ()
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{
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long temp;
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@ -1734,12 +1794,23 @@ void OP_F2B0 ()
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PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
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}
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/* asr */
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/* asr imm8, dn */
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void OP_F8C800 ()
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{
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long temp;
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int z, n, c;
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temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
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c = temp & 1;
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temp >>= (insn & 0xff);
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State.regs[REG_D0 + ((insn & 0x300) >> 8)] = temp;
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z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
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n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x8000000) != 0;
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PSW &= ~(PSW_Z | PSW_N | PSW_C);
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PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
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}
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/* lsr */
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/* lsr dm, dn */
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void OP_F2A0 ()
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{
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int z, n, c;
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@ -1753,12 +1824,20 @@ void OP_F2A0 ()
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PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
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}
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/* lsr */
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/* lsr dm, dn */
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void OP_F8C400 ()
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{
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int z, n, c;
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c = State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 1;
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State.regs[REG_D0 + ((insn & 0x300) >> 8)] >>= (insn & 0xff);
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z = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] == 0);
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n = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] & 0x8000000) != 0;
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PSW &= ~(PSW_Z | PSW_N | PSW_C);
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PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
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}
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/* asl */
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/* asl dm, dn */
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void OP_F290 ()
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{
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int n, z;
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@ -1771,9 +1850,16 @@ void OP_F290 ()
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PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
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}
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/* asl */
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/* asl imm8, dn */
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void OP_F8C000 ()
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{
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int n, z;
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State.regs[REG_D0 + ((insn & 0x300) >> 8)] <<= (insn & 0xff);
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z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
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n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x8000000) != 0;
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PSW &= ~(PSW_Z | PSW_N);
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PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
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}
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/* asl2 dn */
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