Add support for Andes NDS32:

BFD:
	* Makefile.am (BFD32_BACKENDS, BFD32_BACKENDS_CFILES): Add nds32
	files.
	* Makefile.in: Regenerate.
	* archures.c (bfd_nds32_arch): Add nds32 target.
	* bfd-in2.h: Regenerate.
	* config.bfd (nds32*le-*-linux): Add bfd_elf32_nds32lelin_vec
	and bfd_elf32_nds32belin_vec.
	(nds32*be-*-linux*): Likewise.
	(nds32*le-*-*): Add bfd_elf32_nds32le_vec and bfd_elf32_nds32be_vec.
	(nds32*be-*-*): Likewise.
	* configure.in (bfd_elf32_nds32be_vec): Add elf32-nds32.lo.
	(bfd_elf32_nds32le_vec): Likewise.
	(bfd_elf32_nds32belin_vec): Likewise.
	(bfd_elf32_nds32lelin_vec): Likewise.
	* configure: Regenerate.
	* cpu-nds32.c: New file for nds32.
	* elf-bfd.h: Add NDS32_ELF_DATA.
	* elf32-nds32.c: New file for nds32.
	* elf32-nds32.h: New file for nds32.
	* libbfd.h: Regenerate.
	* reloc.c: Add relocations for nds32.
	* targets.c (bfd_elf32_nds32be_vec): New declaration for nds32.
	(bfd_elf32_nds32le_vec): Likewise.
	(bfd_elf32_nds32belin_vec): Likewise.
	(bfd_elf32_nds32lelin_vec): Likewise.

BINUTILS:
	* readelf.c: Include elf/nds32.h
	(guess_is_rela): Add case for EM_NDS32.
	(dump_relocations): Add case for EM_NDS32.
	(decode_NDS32_machine_flags): New.
	(get_machine_flags): Add case for EM_NDS32.
	(is_32bit_abs_reloc): Likewise.
	(is_16bit_abs_reloc): Likewise.
	(process_nds32_specific): New.
	(process_arch_specific): Add case for EM_NDS32.
	* NEWS: Announce Andes nds32 support.
	* MAINTAINERS: Add nds32 maintainers.
  TESTSUITE:
	* binutils-all/objdump.exp: Add NDS32 cpu.
	* binutils-all/readelf.r: Skip extra reloc created by NDS32.

GAS:
	* Makefile.am (TARGET_CPU_CFILES): Add config/tc-nds32.c.
	(TARGET_CPU_HFILES): Add config/tc-nds32.h.
	* Makefile.in: Regenerate.
	* configure.in (nds32): Add nds32 target extension config support.
	* configure.tgt : Add case for nds32-*-elf* and nds32-*-linux*.
	* configure: Regenerate.
	* config/tc-nds32.c: New file for nds32.
	* config/tc-nds32.h: New file for nds32.
	* doc/Makefile.am (CPU_DOCS): Add c-nds32.texi.
	* doc/Makefile.in: Regenerate.
	* doc/as.texinfo: Add nds32 options.
	* doc/all.texi: Set NDS32.
	* doc/c-nds32.texi: New file dor nds32 document.
	* NEWS: Announce Andes nds32 support.
  TESTSUITE:
	* gas/all/gas.exp: Add expected failures for NDS32.
	* gas/elf/elf.exp: Likewise.
	* gas/lns/lns.exp: Use alternate test.
	* gas/macros/irp.d: Skip for NDS32.
	* gas/macros/macros.exp: Skip some tests for the NDS32.
	* gas/macros/rept.d: Skip for NDS32.
	* gas/macros/test3.d: Skip for NDS32.
	* gas/nds32: New directory.
	* gas/nds32/alu-1.s: New test.
	* gas/nds32/alu-1.d: Likewise.
	* gas/nds32/alu-2.s: Likewise.
	* gas/nds32/alu-2.d: Likewise.
	* gas/nds32/br-1.d: Likewise.
	* gas/nds32/br-1.s: Likewise.
	* gas/nds32/br-2.d: Likewise.
	* gas/nds32/br-2.s: Likewise.
	* gas/nds32/ji-jr.d: Likewise.
	* gas/nds32/ji-jr.s: Likewise.
	* gas/nds32/ls.d: Likewise.
	* gas/nds32/ls.s: Likewise.
	* gas/nds32/lsi.d: Likewise.
	* gas/nds32/lsi.s: Likewise.
	* gas/nds32/to-16bit-v1.d: Likewise.
	* gas/nds32/to-16bit-v1.s: Likewise.
	* gas/nds32/to-16bit-v2.d: Likewise.
	* gas/nds32/to-16bit-v2.s: Likewise.
	* gas/nds32/to-16bit-v3.d: Likewise.
	* gas/nds32/to-16bit-v3.s: Likewise.
	* gas/nds32/nds32.exp: New test driver.

LD:
	* Makefile.am (ALL_EMULATION_SOURCES): Add nds32 target.
	* Makefile.in: Regenerate.
	* configure.tgt: Add case for nds32*le-*-elf*, nds32*be-*-elf*,
	nds32*le-*-linux-gnu*, and nds32*be-*-linux-gnu*.
	* emulparams/nds32belf.sh: New file for nds32.
	* emulparams/nds32belf_linux.sh: Likewise.
	* emulparams/nds32belf16m.sh: Likewise.
	* emulparams/nds32elf.sh: Likewise.
	* emulparams/nds32elf_linux.sh: Likewise.
	* emulparams/nds32elf16m.sh: Likewise.
	* emultempl/nds32elf.em: Likewise.
	* scripttempl/nds32elf.sc}: Likewise.
	* gen-doc.texi: Set NDS32.
	* ld.texinfo: Set NDS32.
	* NEWS: Announce Andes nds32 support.
  TESTSUITE:
	* lib/ld-lib.exp: Add NDS32 to list of targets that do not support
	shared library generation.
	* ld-nds32: New directory.
	* ld-nds32/branch.d: New test.
	* ld-nds32/branch.ld: New test.
	* ld-nds32/branch.s: New test.
	* ld-nds32/diff.d: New test.
	* ld-nds32/diff.ld: New test.
	* ld-nds32/diff.s: New test.
	* ld-nds32/gp.d: New test.
	* ld-nds32/gp.ld: New test.
	* ld-nds32/gp.s: New test.
	* ld-nds32/imm.d: New test.
	* ld-nds32/imm.ld: New test.
	* ld-nds32/imm.s: New test.
	* ld-nds32/imm_symbol.s: New test.
	* ld-nds32/relax_jmp.d: New test.
	* ld-nds32/relax_jmp.ld: New test.
	* ld-nds32/relax_jmp.s: New test.
	* ld-nds32/relax_load_store.d: New test.
	* ld-nds32/relax_load_store.ld: New test.
	* ld-nds32/relax_load_store.s: New test.
	* ld-nds32/nds32.exp: New file.

OPCODES:
	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nds32-asm.c
	and nds32-dis.c.
	* Makefile.in: Regenerate.
	* configure.in: Add case for bfd_nds32_arch.
	* configure: Regenerate.
	* disassemble.c (ARCH_nds32): Define.
	* nds32-asm.c: New file for nds32.
	* nds32-asm.h: New file for nds32.
	* nds32-dis.c: New file for nds32.
	* nds32-opc.h: New file for nds32.

INCLUDE:
	* dis-asm.h (print_insn_nds32): Add nds32 target.
	* elf/nds32.h: New file for nds32.
	* opcode/nds32.h: New file for nds32.

bfd/ChangeLog

@@ -1,3 +1,32 @@
+2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
+	    Wei-Cheng Wang  <cole945@gmail.com>
+
+	* Makefile.am (BFD32_BACKENDS, BFD32_BACKENDS_CFILES): Add nds32
+	files.
+	* Makefile.in: Regenerate.
+	* archures.c (bfd_nds32_arch): Add nds32 target.
+	* bfd-in2.h: Regenerate.
+	* config.bfd (nds32*le-*-linux): Add bfd_elf32_nds32lelin_vec
+	and bfd_elf32_nds32belin_vec.
+	(nds32*be-*-linux*): Likewise.
+	(nds32*le-*-*): Add bfd_elf32_nds32le_vec and bfd_elf32_nds32be_vec.
+	(nds32*be-*-*): Likewise.
+	* configure.in (bfd_elf32_nds32be_vec): Add elf32-nds32.lo.
+	(bfd_elf32_nds32le_vec): Likewise.
+	(bfd_elf32_nds32belin_vec): Likewise.
+	(bfd_elf32_nds32lelin_vec): Likewise.
+	* configure: Regenerate.
+	* cpu-nds32.c: New file for nds32.
+	* elf-bfd.h: Add NDS32_ELF_DATA.
+	* elf32-nds32.c: New file for nds32.
+	* elf32-nds32.h: New file for nds32.
+	* libbfd.h: Regenerate.
+	* reloc.c: Add relocations for nds32.
+	* targets.c (bfd_elf32_nds32be_vec): New declaration for nds32.
+	(bfd_elf32_nds32le_vec): Likewise.
+	(bfd_elf32_nds32belin_vec): Likewise.
+	(bfd_elf32_nds32lelin_vec): Likewise.
+
 2013-12-12  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR binutils/16318

bfd/Makefile.am

@@ -136,6 +136,7 @@ ALL_MACHINES = \
 	cpu-moxie.lo \
 	cpu-msp430.lo \
 	cpu-mt.lo \
+	cpu-nds32.lo \
 	cpu-nios2.lo \
 	cpu-ns32k.lo \
 	cpu-openrisc.lo \
@@ -220,6 +221,7 @@ ALL_MACHINES_CFILES = \
 	cpu-moxie.c \
 	cpu-msp430.c \
 	cpu-mt.c \
+	cpu-nds32.c \
 	cpu-ns32k.c \
 	cpu-nios2.c \
 	cpu-openrisc.c \
@@ -349,6 +351,7 @@ BFD32_BACKENDS = \
 	elf32-moxie.lo \
 	elf32-msp430.lo \
 	elf32-mt.lo \
+	elf32-nds32.lo \
 	elf32-nios2.lo \
 	elf32-openrisc.lo \
 	elf32-or32.lo \
@@ -537,6 +540,7 @@ BFD32_BACKENDS_CFILES = \
 	elf32-moxie.c \
 	elf32-msp430.c \
 	elf32-mt.c \
+	elf32-nds32.c \
 	elf32-nios2.c \
 	elf32-openrisc.c \
 	elf32-or32.c \

bfd/Makefile.in

@@ -437,6 +437,7 @@ ALL_MACHINES = \
 	cpu-moxie.lo \
 	cpu-msp430.lo \
 	cpu-mt.lo \
+	cpu-nds32.lo \
 	cpu-nios2.lo \
 	cpu-ns32k.lo \
 	cpu-openrisc.lo \
@@ -521,6 +522,7 @@ ALL_MACHINES_CFILES = \
 	cpu-moxie.c \
 	cpu-msp430.c \
 	cpu-mt.c \
+	cpu-nds32.c \
 	cpu-ns32k.c \
 	cpu-nios2.c \
 	cpu-openrisc.c \
@@ -651,6 +653,7 @@ BFD32_BACKENDS = \
 	elf32-moxie.lo \
 	elf32-msp430.lo \
 	elf32-mt.lo \
+	elf32-nds32.lo \
 	elf32-nios2.lo \
 	elf32-openrisc.lo \
 	elf32-or32.lo \
@@ -839,6 +842,7 @@ BFD32_BACKENDS_CFILES = \
 	elf32-moxie.c \
 	elf32-msp430.c \
 	elf32-mt.c \
+	elf32-nds32.c \
 	elf32-nios2.c \
 	elf32-openrisc.c \
 	elf32-or32.c \
@@ -1352,6 +1356,7 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-moxie.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-msp430.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-mt.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-nds32.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-nios2.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-ns32k.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-openrisc.Plo@am__quote@
@@ -1442,6 +1447,7 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-moxie.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-msp430.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-mt.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-nds32.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-nios2.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-openrisc.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-or32.Plo@am__quote@

bfd/archures.c

@@ -316,6 +316,12 @@ DESCRIPTION
 .#define bfd_mach_arm_ep9312	11
 .#define bfd_mach_arm_iWMMXt	12
 .#define bfd_mach_arm_iWMMXt2	13
+.  bfd_arch_nds32,     {* Andes NDS32 *}
+.#define bfd_mach_n1            1
+.#define bfd_mach_n1h           2
+.#define bfd_mach_n1h_v2        3
+.#define bfd_mach_n1h_v3        4
+.#define bfd_mach_n1h_v3m       5
 .  bfd_arch_ns32k,     {* National Semiconductors ns32000 *}
 .  bfd_arch_w65,       {* WDC 65816 *}
 .  bfd_arch_tic30,     {* Texas Instruments TMS320C30 *}
@@ -574,6 +580,7 @@ extern const bfd_arch_info_type bfd_mn10300_arch;
 extern const bfd_arch_info_type bfd_moxie_arch;
 extern const bfd_arch_info_type bfd_msp430_arch;
 extern const bfd_arch_info_type bfd_mt_arch;
+extern const bfd_arch_info_type bfd_nds32_arch;
 extern const bfd_arch_info_type bfd_nios2_arch;
 extern const bfd_arch_info_type bfd_ns32k_arch;
 extern const bfd_arch_info_type bfd_openrisc_arch;
@@ -663,6 +670,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
     &bfd_moxie_arch,
     &bfd_msp430_arch,
     &bfd_mt_arch,
+    &bfd_nds32_arch,
     &bfd_nios2_arch,
     &bfd_ns32k_arch,
     &bfd_openrisc_arch,

bfd/bfd-in2.h

@@ -2073,6 +2073,12 @@ enum bfd_architecture
 #define bfd_mach_arm_ep9312    11
 #define bfd_mach_arm_iWMMXt    12
 #define bfd_mach_arm_iWMMXt2   13
+  bfd_arch_nds32,     /* Andes NDS32 */
+#define bfd_mach_n1            1
+#define bfd_mach_n1h           2
+#define bfd_mach_n1h_v2        3
+#define bfd_mach_n1h_v3        4
+#define bfd_mach_n1h_v3m       5
   bfd_arch_ns32k,     /* National Semiconductors ns32000 */
   bfd_arch_w65,       /* WDC 65816 */
   bfd_arch_tic30,     /* Texas Instruments TMS320C30 */
@@ -3796,6 +3802,178 @@ add3, load, and store instructions.  */
   BFD_RELOC_M32R_GOTPC_HI_SLO,
   BFD_RELOC_M32R_GOTPC_LO,
 
+/* NDS32 relocs.
+This is a 20 bit absolute address.  */
+  BFD_RELOC_NDS32_20,
+
+/* This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.  */
+  BFD_RELOC_NDS32_9_PCREL,
+
+/* This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.  */
+  BFD_RELOC_NDS32_WORD_9_PCREL,
+
+/* This is an 15-bit reloc with the right 1 bit assumed to be 0.  */
+  BFD_RELOC_NDS32_15_PCREL,
+
+/* This is an 17-bit reloc with the right 1 bit assumed to be 0.  */
+  BFD_RELOC_NDS32_17_PCREL,
+
+/* This is a 25-bit reloc with the right 1 bit assumed to be 0.  */
+  BFD_RELOC_NDS32_25_PCREL,
+
+/* This is a 20-bit reloc containing the high 20 bits of an address
+used with the lower 12 bits  */
+  BFD_RELOC_NDS32_HI20,
+
+/* This is a 12-bit reloc containing the lower 12 bits of an address
+then shift right by 3. This is used with ldi,sdi...  */
+  BFD_RELOC_NDS32_LO12S3,
+
+/* This is a 12-bit reloc containing the lower 12 bits of an address
+then shift left by 2. This is used with lwi,swi...  */
+  BFD_RELOC_NDS32_LO12S2,
+
+/* This is a 12-bit reloc containing the lower 12 bits of an address
+then shift left by 1. This is used with lhi,shi...  */
+  BFD_RELOC_NDS32_LO12S1,
+
+/* This is a 12-bit reloc containing the lower 12 bits of an address
+then shift left by 0. This is used with lbisbi...  */
+  BFD_RELOC_NDS32_LO12S0,
+
+/* This is a 12-bit reloc containing the lower 12 bits of an address
+then shift left by 0. This is only used with branch relaxations  */
+  BFD_RELOC_NDS32_LO12S0_ORI,
+
+/* This is a 15-bit reloc containing the small data area 18-bit signed offset
+and shift left by 3 for use in ldi, sdi...  */
+  BFD_RELOC_NDS32_SDA15S3,
+
+/* This is a 15-bit reloc containing the small data area 17-bit signed offset
+and shift left by 2 for use in lwi, swi...  */
+  BFD_RELOC_NDS32_SDA15S2,
+
+/* This is a 15-bit reloc containing the small data area 16-bit signed offset
+and shift left by 1 for use in lhi, shi...  */
+  BFD_RELOC_NDS32_SDA15S1,
+
+/* This is a 15-bit reloc containing the small data area 15-bit signed offset
+and shift left by 0 for use in lbi, sbi...  */
+  BFD_RELOC_NDS32_SDA15S0,
+
+/* This is a 16-bit reloc containing the small data area 16-bit signed offset
+and shift left by 3  */
+  BFD_RELOC_NDS32_SDA16S3,
+
+/* This is a 17-bit reloc containing the small data area 17-bit signed offset
+and shift left by 2 for use in lwi.gp, swi.gp...  */
+  BFD_RELOC_NDS32_SDA17S2,
+
+/* This is a 18-bit reloc containing the small data area 18-bit signed offset
+and shift left by 1 for use in lhi.gp, shi.gp...  */
+  BFD_RELOC_NDS32_SDA18S1,
+
+/* This is a 19-bit reloc containing the small data area 19-bit signed offset
+and shift left by 0 for use in lbi.gp, sbi.gp...  */
+  BFD_RELOC_NDS32_SDA19S0,
+
+/* for PIC  */
+  BFD_RELOC_NDS32_GOT20,
+  BFD_RELOC_NDS32_9_PLTREL,
+  BFD_RELOC_NDS32_25_PLTREL,
+  BFD_RELOC_NDS32_COPY,
+  BFD_RELOC_NDS32_GLOB_DAT,
+  BFD_RELOC_NDS32_JMP_SLOT,
+  BFD_RELOC_NDS32_RELATIVE,
+  BFD_RELOC_NDS32_GOTOFF,
+  BFD_RELOC_NDS32_GOTOFF_HI20,
+  BFD_RELOC_NDS32_GOTOFF_LO12,
+  BFD_RELOC_NDS32_GOTPC20,
+  BFD_RELOC_NDS32_GOT_HI20,
+  BFD_RELOC_NDS32_GOT_LO12,
+  BFD_RELOC_NDS32_GOTPC_HI20,
+  BFD_RELOC_NDS32_GOTPC_LO12,
+
+/* for relax  */
+  BFD_RELOC_NDS32_INSN16,
+  BFD_RELOC_NDS32_LABEL,
+  BFD_RELOC_NDS32_LONGCALL1,
+  BFD_RELOC_NDS32_LONGCALL2,
+  BFD_RELOC_NDS32_LONGCALL3,
+  BFD_RELOC_NDS32_LONGJUMP1,
+  BFD_RELOC_NDS32_LONGJUMP2,
+  BFD_RELOC_NDS32_LONGJUMP3,
+  BFD_RELOC_NDS32_LOADSTORE,
+  BFD_RELOC_NDS32_9_FIXED,
+  BFD_RELOC_NDS32_15_FIXED,
+  BFD_RELOC_NDS32_17_FIXED,
+  BFD_RELOC_NDS32_25_FIXED,
+
+/* for PIC  */
+  BFD_RELOC_NDS32_PLTREL_HI20,
+  BFD_RELOC_NDS32_PLTREL_LO12,
+  BFD_RELOC_NDS32_PLT_GOTREL_HI20,
+  BFD_RELOC_NDS32_PLT_GOTREL_LO12,
+
+/* for floating point  */
+  BFD_RELOC_NDS32_SDA12S2_DP,
+  BFD_RELOC_NDS32_SDA12S2_SP,
+  BFD_RELOC_NDS32_LO12S2_DP,
+  BFD_RELOC_NDS32_LO12S2_SP,
+
+/* for dwarf2 debug_line.  */
+  BFD_RELOC_NDS32_DWARF2_OP1,
+  BFD_RELOC_NDS32_DWARF2_OP2,
+  BFD_RELOC_NDS32_DWARF2_LEB,
+
+/* for eliminate 16-bit instructions  */
+  BFD_RELOC_NDS32_UPDATE_TA,
+
+/* for PIC object relaxation  */
+  BFD_RELOC_NDS32_PLT_GOTREL_LO20,
+  BFD_RELOC_NDS32_PLT_GOTREL_LO15,
+  BFD_RELOC_NDS32_PLT_GOTREL_LO19,
+  BFD_RELOC_NDS32_GOT_LO15,
+  BFD_RELOC_NDS32_GOT_LO19,
+  BFD_RELOC_NDS32_GOTOFF_LO15,
+  BFD_RELOC_NDS32_GOTOFF_LO19,
+  BFD_RELOC_NDS32_GOT15S2,
+  BFD_RELOC_NDS32_GOT17S2,
+
+/* NDS32 relocs.
+This is a 5 bit absolute address.  */
+  BFD_RELOC_NDS32_5,
+
+/* This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.  */
+  BFD_RELOC_NDS32_10_UPCREL,
+
+/* If fp were omitted, fp can used as another gp.  */
+  BFD_RELOC_NDS32_SDA_FP7U2_RELA,
+
+/* relaxation relative relocation types  */
+  BFD_RELOC_NDS32_RELAX_ENTRY,
+  BFD_RELOC_NDS32_GOT_SUFF,
+  BFD_RELOC_NDS32_GOTOFF_SUFF,
+  BFD_RELOC_NDS32_PLT_GOT_SUFF,
+  BFD_RELOC_NDS32_MULCALL_SUFF,
+  BFD_RELOC_NDS32_PTR,
+  BFD_RELOC_NDS32_PTR_COUNT,
+  BFD_RELOC_NDS32_PTR_RESOLVED,
+  BFD_RELOC_NDS32_PLTBLOCK,
+  BFD_RELOC_NDS32_RELAX_REGION_BEGIN,
+  BFD_RELOC_NDS32_RELAX_REGION_END,
+  BFD_RELOC_NDS32_MINUEND,
+  BFD_RELOC_NDS32_SUBTRAHEND,
+  BFD_RELOC_NDS32_DIFF8,
+  BFD_RELOC_NDS32_DIFF16,
+  BFD_RELOC_NDS32_DIFF32,
+  BFD_RELOC_NDS32_DIFF_ULEB128,
+  BFD_RELOC_NDS32_25_ABS,
+  BFD_RELOC_NDS32_DATA,
+  BFD_RELOC_NDS32_TRAN,
+  BFD_RELOC_NDS32_17IFC_PCREL,
+  BFD_RELOC_NDS32_10IFCU_PCREL,
+
 /* This is a 9-bit reloc  */
   BFD_RELOC_V850_9_PCREL,
 

bfd/config.bfd

@@ -109,6 +109,7 @@ m68*)		 targ_archs=bfd_m68k_arch ;;
 m88*)		 targ_archs=bfd_m88k_arch ;;
 microblaze*)	 targ_archs=bfd_microblaze_arch ;;
 mips*)		 targ_archs=bfd_mips_arch ;;
+nds32*)		 targ_archs=bfd_nds32_arch ;;
 nios2*)          targ_archs=bfd_nios2_arch ;;
 or32*)		 targ_archs=bfd_or32_arch ;;
 pdp11*)		 targ_archs=bfd_pdp11_arch ;;
@@ -1120,6 +1121,26 @@ case "${targ}" in
     targ_selvecs=bfd_elf32_msp430_ti_vec
     ;;
 
+  nds32*le-*-linux*)
+    targ_defvec=bfd_elf32_nds32lelin_vec
+    targ_selvecs=bfd_elf32_nds32belin_vec
+    ;;
+
+  nds32*be-*-linux*)
+    targ_defvec=bfd_elf32_nds32belin_vec
+    targ_selvecs=bfd_elf32_nds32lelin_vec
+    ;;
+
+  nds32*le-*-*)
+    targ_defvec=bfd_elf32_nds32le_vec
+    targ_selvecs=bfd_elf32_nds32be_vec
+    ;;
+
+  nds32*be-*-*)
+    targ_defvec=bfd_elf32_nds32be_vec
+    targ_selvecs=bfd_elf32_nds32le_vec
+    ;;
+
   ns32k-pc532-mach* | ns32k-pc532-ux*)
     targ_defvec=pc532machaout_vec
     targ_underscore=yes

bfd/configure

@@ -15307,6 +15307,10 @@ do
 				tb="$tb elfn32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
     bfd_elf32_ntradlittlemips_vec | bfd_elf32_ntradlittlemips_freebsd_vec)
 				tb="$tb elfn32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
+    bfd_elf32_nds32be_vec)      tb="$tb elf32-nds32.lo elf32.lo $elf" ;;
+    bfd_elf32_nds32le_vec)      tb="$tb elf32-nds32.lo elf32.lo $elf" ;;
+    bfd_elf32_nds32belin_vec)   tb="$tb elf32-nds32.lo elf32.lo $elf" ;;
+    bfd_elf32_nds32lelin_vec)   tb="$tb elf32-nds32.lo elf32.lo $elf" ;;
     bfd_elf32_openrisc_vec)	tb="$tb elf32-openrisc.lo elf32.lo $elf" ;;
     bfd_elf32_or32_big_vec)	tb="$tb elf32-or32.lo elf32.lo $elf" ;;
     bfd_elf32_pj_vec)           tb="$tb elf32-pj.lo elf32.lo $elf";;

bfd/configure.in

@@ -796,6 +796,10 @@ do
 				tb="$tb elfn32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
     bfd_elf32_ntradlittlemips_vec | bfd_elf32_ntradlittlemips_freebsd_vec)
 				tb="$tb elfn32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
+    bfd_elf32_nds32be_vec)      tb="$tb elf32-nds32.lo elf32.lo $elf" ;;
+    bfd_elf32_nds32le_vec)      tb="$tb elf32-nds32.lo elf32.lo $elf" ;;
+    bfd_elf32_nds32belin_vec)   tb="$tb elf32-nds32.lo elf32.lo $elf" ;;
+    bfd_elf32_nds32lelin_vec)   tb="$tb elf32-nds32.lo elf32.lo $elf" ;;
     bfd_elf32_openrisc_vec)	tb="$tb elf32-openrisc.lo elf32.lo $elf" ;;
     bfd_elf32_or32_big_vec)	tb="$tb elf32-or32.lo elf32.lo $elf" ;;
     bfd_elf32_pj_vec)           tb="$tb elf32-pj.lo elf32.lo $elf";;

bfd/cpu-nds32.c

@@ -0,0 +1,45 @@
+/* BFD support for the NDS32 processor
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libbfd.h"
+#include "elf-bfd.h"
+
+#define N(number, print, default, next)  \
+    {32, 32, 8, bfd_arch_nds32, number, "nds32", print, 4, default, \
+     bfd_default_compatible, bfd_default_scan, bfd_arch_default_fill, next }
+
+#define NEXT		&arch_info_struct[0]
+#define NDS32V2_NEXT	&arch_info_struct[1]
+#define NDS32V3_NEXT	&arch_info_struct[2]
+#define NDS32V3M_NEXT	&arch_info_struct[3]
+
+static const bfd_arch_info_type arch_info_struct[] =
+{
+  N (bfd_mach_n1h, "n1h", FALSE, NDS32V2_NEXT),
+  N (bfd_mach_n1h_v2, "n1h_v2", FALSE, NDS32V3_NEXT),
+  N (bfd_mach_n1h_v3, "n1h_v3", FALSE, NDS32V3M_NEXT),
+  N (bfd_mach_n1h_v3m, "n1h_v3m", FALSE, NULL),
+};
+
+const bfd_arch_info_type bfd_nds32_arch =
+  N (bfd_mach_n1, "n1h", TRUE, NEXT);

bfd/elf-bfd.h

@@ -419,6 +419,7 @@ enum elf_target_id
   MICROBLAZE_ELF_DATA,
   MIPS_ELF_DATA,
   MN10300_ELF_DATA,
+  NDS32_ELF_DATA,
   NIOS2_ELF_DATA,
   PPC32_ELF_DATA,
   PPC64_ELF_DATA,

bfd/elf32-nds32.h

@@ -0,0 +1,147 @@
+/* NDS32-specific support for 32-bit ELF.
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.*/
+
+#ifndef ELF32_NDS32_H
+#define ELF32_NDS32_H
+
+/* Relocation flags encoded in r_addend.  */
+
+/* Relocation flags for R_NDS32_ERLAX_ENTRY.  */
+
+/* Set if relax on this section is done or disabled.  */
+#define R_NDS32_RELAX_ENTRY_DISABLE_RELAX_FLAG			(1 << 31)
+/* Optimize for performance.  */
+#define R_NDS32_RELAX_ENTRY_OPTIMIZE_FLAG			(1 << 30)
+/* Optimize for size.  Branch destination 4-byte adjustment
+   may be disabled.  */
+#define R_NDS32_RELAX_ENTRY_OPTIMIZE_FOR_SPACE_FLAG		(1 << 29)
+/* To distinguish the assembly code generated by compiler
+   or written manually.  */
+#define R_NDS32_RELAX_ENTRY_VERBATIM_FLAG			(1 << 28)
+/* EX9 and link-time IFC must be explicitly enabled, so we
+   won't mess up handcraft assembly code.  */
+/* Enable EX9 optimization for this section.  */
+#define R_NDS32_RELAX_ENTRY_EX9_FLAG				(1 << 2)
+/* Enable IFC optimization for this section.  */
+#define R_NDS32_RELAX_ENTRY_IFC_FLAG				(1 << 3)
+
+
+/* Relocation flags for R_NDS32_INSN16.  */
+
+#define R_NDS32_INSN16_CONVERT_FLAG				(1 << 0)
+/* Convert a gp-relative access (e.g., lwi.gp)
+   to fp-as-gp access (lwi37.fp).
+   This value is used by linker internally only.
+   It's fine to change the vlaue.  */
+#define R_NDS32_INSN16_FP7U2_FLAG				(1 << 1)
+
+/* Relocation flags for R_NDS32_RELAX_REGION_OMIT_FP_START/END.  */
+
+/* OMIT_FP_FLAG marks the region for applying fp-as-gp
+   optimization.  */
+#define R_NDS32_RELAX_REGION_OMIT_FP_FLAG			(1 << 0)
+/* NOT_OMIT_FP_FLAG is set if this region is not worth
+   for fp-as-gp.  */
+#define R_NDS32_RELAX_REGION_NOT_OMIT_FP_FLAG			(1 << 1)
+/* Suppress EX9 optimization in the region.  */
+#define R_NDS32_RELAX_REGION_NO_EX9_FLAG			(1 << 2)
+/* A Innermost loop region.  Some optimizations is suppressed
+   in this region due to performance drop.  */
+#define R_NDS32_RELAX_REGION_INNERMOST_LOOP_FLAG		(1 << 4)
+
+/* Relax tag for nds32_elf_relax_section, we have to specify which
+   optimization do in this round.  */
+enum
+{
+  NDS32_RELAX_NONE_ROUND = 0,
+  NDS32_RELAX_JUMP_IFC_ROUND = 1,
+  NDS32_RELAX_EX9_BUILD_ROUND,
+  NDS32_RELAX_EX9_REPLACE_ROUND
+
+};
+
+/* Optimization status mask.  */
+#define NDS32_RELAX_JUMP_IFC_DONE	(1 << 0)
+#define NDS32_RELAX_EX9_DONE		(1 << 1)
+
+/* Optimization turn on mask.  */
+#define NDS32_RELAX_JUMP_IFC_ON		(1 << 0)
+#define NDS32_RELAX_EX9_ON		(1 << 1)
+
+/* The break 0xea defined for ex9 table to keep for trace32 to use 0xeaea.  */
+#define INSN_BREAK_EA   0x64001d4a
+
+extern void nds32_insertion_sort
+  (void *, size_t, size_t, int (*) (const void *, const void *));
+
+extern int         nds32_elf_ex9_init (void);
+extern void        nds32_elf_ex9_reloc_jmp (struct bfd_link_info *);
+extern void        nds32_elf_ex9_finish (struct bfd_link_info *);
+extern bfd_boolean nds32_elf_ex9_itb_base (struct bfd_link_info *);
+extern void        nds32_elf_ex9_import_table (struct bfd_link_info *);
+extern bfd_boolean nds32_elf_ifc_reloc (void);
+extern bfd_boolean nds32_elf_ifc_finish (struct bfd_link_info *);
+extern int         nds32_convert_32_to_16 (bfd *, uint32_t, uint16_t *, int *);
+extern int         nds32_convert_16_to_32 (bfd *, uint16_t, uint32_t *);
+extern void        bfd_elf32_nds32_set_target_option (struct bfd_link_info *, int, int,
+						      FILE *, int, int, int, int, FILE *, FILE *,
+						      int, int, bfd_boolean, bfd_boolean);
+
+#define nds32_elf_hash_table(info) \
+  (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
+   == NDS32_ELF_DATA ? ((struct elf_nds32_link_hash_table *) ((info)->hash)) : NULL)
+
+/* Hash table structure for target nds32.  There are some members to
+   save target options passed from nds32elf.em to bfd.  */
+
+struct elf_nds32_link_hash_table
+{
+  struct elf_link_hash_table root;
+
+  /* Short-cuts to get to dynamic linker sections.  */
+  asection *sgot;
+  asection *sgotplt;
+  asection *srelgot;
+  asection *splt;
+  asection *srelplt;
+  asection *sdynbss;
+  asection *srelbss;
+
+  /* Small local sym to section mapping cache.  */
+  struct sym_cache sym_cache;
+
+  /* Target dependent options.  */
+  int relax_fp_as_gp;		/* --mrelax-omit-fp  */
+  int eliminate_gc_relocs;	/* --meliminate-gc-relocs  */
+  FILE *sym_ld_script;		/* --mgen-symbol-ld-script=<file>  */
+  /* Disable if linking a dynamically linked executable.  */
+  int load_store_relax;
+  int target_optimize;		/* Switch optimization.  */
+  int relax_status;		/* Finished optimization.  */
+  int relax_round;		/* Going optimization.  */
+  FILE *ex9_export_file;	/* --mexport-ex9=<file>  */
+  FILE *ex9_import_file;	/* --mimport-ex9=<file>  */
+  int update_ex9_table;		/* --mupdate-ex9.  */
+  int ex9_limit;
+  bfd_boolean ex9_loop_aware;	/* Ignore ex9 if inside a loop.  */
+  bfd_boolean ifc_loop_aware;	/* Ignore ifc if inside a loop.  */
+};
+#endif

bfd/libbfd.h

@@ -1746,6 +1746,100 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
   "BFD_RELOC_M32R_GOTPC_HI_ULO",
   "BFD_RELOC_M32R_GOTPC_HI_SLO",
   "BFD_RELOC_M32R_GOTPC_LO",
+  "BFD_RELOC_NDS32_20",
+  "BFD_RELOC_NDS32_9_PCREL",
+  "BFD_RELOC_NDS32_WORD_9_PCREL",
+  "BFD_RELOC_NDS32_15_PCREL",
+  "BFD_RELOC_NDS32_17_PCREL",
+  "BFD_RELOC_NDS32_25_PCREL",
+  "BFD_RELOC_NDS32_HI20",
+  "BFD_RELOC_NDS32_LO12S3",
+  "BFD_RELOC_NDS32_LO12S2",
+  "BFD_RELOC_NDS32_LO12S1",
+  "BFD_RELOC_NDS32_LO12S0",
+  "BFD_RELOC_NDS32_LO12S0_ORI",
+  "BFD_RELOC_NDS32_SDA15S3",
+  "BFD_RELOC_NDS32_SDA15S2",
+  "BFD_RELOC_NDS32_SDA15S1",
+  "BFD_RELOC_NDS32_SDA15S0",
+  "BFD_RELOC_NDS32_SDA16S3",
+  "BFD_RELOC_NDS32_SDA17S2",
+  "BFD_RELOC_NDS32_SDA18S1",
+  "BFD_RELOC_NDS32_SDA19S0",
+  "BFD_RELOC_NDS32_GOT20",
+  "BFD_RELOC_NDS32_9_PLTREL",
+  "BFD_RELOC_NDS32_25_PLTREL",
+  "BFD_RELOC_NDS32_COPY",
+  "BFD_RELOC_NDS32_GLOB_DAT",
+  "BFD_RELOC_NDS32_JMP_SLOT",
+  "BFD_RELOC_NDS32_RELATIVE",
+  "BFD_RELOC_NDS32_GOTOFF",
+  "BFD_RELOC_NDS32_GOTOFF_HI20",
+  "BFD_RELOC_NDS32_GOTOFF_LO12",
+  "BFD_RELOC_NDS32_GOTPC20",
+  "BFD_RELOC_NDS32_GOT_HI20",
+  "BFD_RELOC_NDS32_GOT_LO12",
+  "BFD_RELOC_NDS32_GOTPC_HI20",
+  "BFD_RELOC_NDS32_GOTPC_LO12",
+  "BFD_RELOC_NDS32_INSN16",
+  "BFD_RELOC_NDS32_LABEL",
+  "BFD_RELOC_NDS32_LONGCALL1",
+  "BFD_RELOC_NDS32_LONGCALL2",
+  "BFD_RELOC_NDS32_LONGCALL3",
+  "BFD_RELOC_NDS32_LONGJUMP1",
+  "BFD_RELOC_NDS32_LONGJUMP2",
+  "BFD_RELOC_NDS32_LONGJUMP3",
+  "BFD_RELOC_NDS32_LOADSTORE",
+  "BFD_RELOC_NDS32_9_FIXED",
+  "BFD_RELOC_NDS32_15_FIXED",
+  "BFD_RELOC_NDS32_17_FIXED",
+  "BFD_RELOC_NDS32_25_FIXED",
+  "BFD_RELOC_NDS32_PLTREL_HI20",
+  "BFD_RELOC_NDS32_PLTREL_LO12",
+  "BFD_RELOC_NDS32_PLT_GOTREL_HI20",
+  "BFD_RELOC_NDS32_PLT_GOTREL_LO12",
+  "BFD_RELOC_NDS32_SDA12S2_DP",
+  "BFD_RELOC_NDS32_SDA12S2_SP",
+  "BFD_RELOC_NDS32_LO12S2_DP",
+  "BFD_RELOC_NDS32_LO12S2_SP",
+  "BFD_RELOC_NDS32_DWARF2_OP1",
+  "BFD_RELOC_NDS32_DWARF2_OP2",
+  "BFD_RELOC_NDS32_DWARF2_LEB",
+  "BFD_RELOC_NDS32_UPDATE_TA",
+  "BFD_RELOC_NDS32_PLT_GOTREL_LO20",
+  "BFD_RELOC_NDS32_PLT_GOTREL_LO15",
+  "BFD_RELOC_NDS32_PLT_GOTREL_LO19",
+  "BFD_RELOC_NDS32_GOT_LO15",
+  "BFD_RELOC_NDS32_GOT_LO19",
+  "BFD_RELOC_NDS32_GOTOFF_LO15",
+  "BFD_RELOC_NDS32_GOTOFF_LO19",
+  "BFD_RELOC_NDS32_GOT15S2",
+  "BFD_RELOC_NDS32_GOT17S2",
+  "BFD_RELOC_NDS32_5",
+  "BFD_RELOC_NDS32_10_UPCREL",
+  "BFD_RELOC_NDS32_SDA_FP7U2_RELA",
+  "BFD_RELOC_NDS32_RELAX_ENTRY",
+  "BFD_RELOC_NDS32_GOT_SUFF",
+  "BFD_RELOC_NDS32_GOTOFF_SUFF",
+  "BFD_RELOC_NDS32_PLT_GOT_SUFF",
+  "BFD_RELOC_NDS32_MULCALL_SUFF",
+  "BFD_RELOC_NDS32_PTR",
+  "BFD_RELOC_NDS32_PTR_COUNT",
+  "BFD_RELOC_NDS32_PTR_RESOLVED",
+  "BFD_RELOC_NDS32_PLTBLOCK",
+  "BFD_RELOC_NDS32_RELAX_REGION_BEGIN",
+  "BFD_RELOC_NDS32_RELAX_REGION_END",
+  "BFD_RELOC_NDS32_MINUEND",
+  "BFD_RELOC_NDS32_SUBTRAHEND",
+  "BFD_RELOC_NDS32_DIFF8",
+  "BFD_RELOC_NDS32_DIFF16",
+  "BFD_RELOC_NDS32_DIFF32",
+  "BFD_RELOC_NDS32_DIFF_ULEB128",
+  "BFD_RELOC_NDS32_25_ABS",
+  "BFD_RELOC_NDS32_DATA",
+  "BFD_RELOC_NDS32_TRAN",
+  "BFD_RELOC_NDS32_17IFC_PCREL",
+  "BFD_RELOC_NDS32_10IFCU_PCREL",
   "BFD_RELOC_V850_9_PCREL",
   "BFD_RELOC_V850_22_PCREL",
   "BFD_RELOC_V850_SDA_16_16_OFFSET",

bfd/reloc.c

@@ -3838,6 +3838,274 @@ ENUMDOC
   For PIC.
 
 
+ENUM
+  BFD_RELOC_NDS32_20
+ENUMDOC
+  NDS32 relocs.
+  This is a 20 bit absolute address.
+ENUM
+  BFD_RELOC_NDS32_9_PCREL
+ENUMDOC
+  This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
+ENUM
+  BFD_RELOC_NDS32_WORD_9_PCREL
+ENUMDOC
+  This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
+ENUM
+  BFD_RELOC_NDS32_15_PCREL
+ENUMDOC
+  This is an 15-bit reloc with the right 1 bit assumed to be 0.
+ENUM
+  BFD_RELOC_NDS32_17_PCREL
+ENUMDOC
+  This is an 17-bit reloc with the right 1 bit assumed to be 0.
+ENUM
+  BFD_RELOC_NDS32_25_PCREL
+ENUMDOC
+  This is a 25-bit reloc with the right 1 bit assumed to be 0.
+ENUM
+  BFD_RELOC_NDS32_HI20
+ENUMDOC
+  This is a 20-bit reloc containing the high 20 bits of an address
+  used with the lower 12 bits
+ENUM
+  BFD_RELOC_NDS32_LO12S3
+ENUMDOC
+  This is a 12-bit reloc containing the lower 12 bits of an address
+  then shift right by 3. This is used with ldi,sdi...
+ENUM
+  BFD_RELOC_NDS32_LO12S2
+ENUMDOC
+  This is a 12-bit reloc containing the lower 12 bits of an address
+  then shift left by 2. This is used with lwi,swi...
+ENUM
+  BFD_RELOC_NDS32_LO12S1
+ENUMDOC
+  This is a 12-bit reloc containing the lower 12 bits of an address
+  then shift left by 1. This is used with lhi,shi...
+ENUM
+  BFD_RELOC_NDS32_LO12S0
+ENUMDOC
+  This is a 12-bit reloc containing the lower 12 bits of an address
+  then shift left by 0. This is used with lbisbi...
+ENUM
+  BFD_RELOC_NDS32_LO12S0_ORI
+ENUMDOC
+  This is a 12-bit reloc containing the lower 12 bits of an address
+  then shift left by 0. This is only used with branch relaxations
+ENUM
+  BFD_RELOC_NDS32_SDA15S3
+ENUMDOC
+  This is a 15-bit reloc containing the small data area 18-bit signed offset
+  and shift left by 3 for use in ldi, sdi...
+ENUM
+  BFD_RELOC_NDS32_SDA15S2
+ENUMDOC
+  This is a 15-bit reloc containing the small data area 17-bit signed offset
+  and shift left by 2 for use in lwi, swi...
+ENUM
+  BFD_RELOC_NDS32_SDA15S1
+ENUMDOC
+  This is a 15-bit reloc containing the small data area 16-bit signed offset
+  and shift left by 1 for use in lhi, shi...
+ENUM
+  BFD_RELOC_NDS32_SDA15S0
+ENUMDOC
+  This is a 15-bit reloc containing the small data area 15-bit signed offset
+  and shift left by 0 for use in lbi, sbi...
+ENUM
+  BFD_RELOC_NDS32_SDA16S3
+ENUMDOC
+  This is a 16-bit reloc containing the small data area 16-bit signed offset
+  and shift left by 3
+ENUM
+  BFD_RELOC_NDS32_SDA17S2
+ENUMDOC
+  This is a 17-bit reloc containing the small data area 17-bit signed offset
+  and shift left by 2 for use in lwi.gp, swi.gp...
+ENUM
+  BFD_RELOC_NDS32_SDA18S1
+ENUMDOC
+  This is a 18-bit reloc containing the small data area 18-bit signed offset
+  and shift left by 1 for use in lhi.gp, shi.gp...
+ENUM
+  BFD_RELOC_NDS32_SDA19S0
+ENUMDOC
+  This is a 19-bit reloc containing the small data area 19-bit signed offset
+  and shift left by 0 for use in lbi.gp, sbi.gp...
+ENUM
+  BFD_RELOC_NDS32_GOT20
+ENUMX
+  BFD_RELOC_NDS32_9_PLTREL
+ENUMX
+  BFD_RELOC_NDS32_25_PLTREL
+ENUMX
+  BFD_RELOC_NDS32_COPY
+ENUMX
+  BFD_RELOC_NDS32_GLOB_DAT
+ENUMX
+  BFD_RELOC_NDS32_JMP_SLOT
+ENUMX
+  BFD_RELOC_NDS32_RELATIVE
+ENUMX
+  BFD_RELOC_NDS32_GOTOFF
+ENUMX
+  BFD_RELOC_NDS32_GOTOFF_HI20
+ENUMX
+  BFD_RELOC_NDS32_GOTOFF_LO12
+ENUMX
+  BFD_RELOC_NDS32_GOTPC20
+ENUMX
+  BFD_RELOC_NDS32_GOT_HI20
+ENUMX
+  BFD_RELOC_NDS32_GOT_LO12
+ENUMX
+  BFD_RELOC_NDS32_GOTPC_HI20
+ENUMX
+  BFD_RELOC_NDS32_GOTPC_LO12
+ENUMDOC
+  for PIC
+ENUM
+  BFD_RELOC_NDS32_INSN16
+ENUMX
+  BFD_RELOC_NDS32_LABEL
+ENUMX
+  BFD_RELOC_NDS32_LONGCALL1
+ENUMX
+  BFD_RELOC_NDS32_LONGCALL2
+ENUMX
+  BFD_RELOC_NDS32_LONGCALL3
+ENUMX
+  BFD_RELOC_NDS32_LONGJUMP1
+ENUMX
+  BFD_RELOC_NDS32_LONGJUMP2
+ENUMX
+  BFD_RELOC_NDS32_LONGJUMP3
+ENUMX
+  BFD_RELOC_NDS32_LOADSTORE
+ENUMX
+  BFD_RELOC_NDS32_9_FIXED
+ENUMX
+  BFD_RELOC_NDS32_15_FIXED
+ENUMX
+  BFD_RELOC_NDS32_17_FIXED
+ENUMX
+  BFD_RELOC_NDS32_25_FIXED
+ENUMDOC
+  for relax
+ENUM
+  BFD_RELOC_NDS32_PLTREL_HI20
+ENUMX
+  BFD_RELOC_NDS32_PLTREL_LO12
+ENUMX
+  BFD_RELOC_NDS32_PLT_GOTREL_HI20
+ENUMX
+  BFD_RELOC_NDS32_PLT_GOTREL_LO12
+ENUMDOC
+  for PIC
+ENUM
+  BFD_RELOC_NDS32_SDA12S2_DP
+ENUMX
+  BFD_RELOC_NDS32_SDA12S2_SP
+ENUMX
+  BFD_RELOC_NDS32_LO12S2_DP
+ENUMX
+  BFD_RELOC_NDS32_LO12S2_SP
+ENUMDOC
+  for floating point
+ENUM
+  BFD_RELOC_NDS32_DWARF2_OP1
+ENUMX
+  BFD_RELOC_NDS32_DWARF2_OP2
+ENUMX
+  BFD_RELOC_NDS32_DWARF2_LEB
+ENUMDOC
+  for dwarf2 debug_line.
+ENUM
+  BFD_RELOC_NDS32_UPDATE_TA
+ENUMDOC
+  for eliminate 16-bit instructions
+ENUM
+  BFD_RELOC_NDS32_PLT_GOTREL_LO20
+ENUMX
+  BFD_RELOC_NDS32_PLT_GOTREL_LO15
+ENUMX
+  BFD_RELOC_NDS32_PLT_GOTREL_LO19
+ENUMX
+  BFD_RELOC_NDS32_GOT_LO15
+ENUMX
+  BFD_RELOC_NDS32_GOT_LO19
+ENUMX
+  BFD_RELOC_NDS32_GOTOFF_LO15
+ENUMX
+  BFD_RELOC_NDS32_GOTOFF_LO19
+ENUMX
+  BFD_RELOC_NDS32_GOT15S2
+ENUMX
+  BFD_RELOC_NDS32_GOT17S2
+ENUMDOC
+  for PIC object relaxation
+ENUM
+  BFD_RELOC_NDS32_5
+ENUMDOC
+  NDS32 relocs.
+  This is a 5 bit absolute address.
+ENUM
+  BFD_RELOC_NDS32_10_UPCREL
+ENUMDOC
+  This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
+ENUM
+  BFD_RELOC_NDS32_SDA_FP7U2_RELA
+ENUMDOC
+  If fp were omitted, fp can used as another gp.
+ENUM
+  BFD_RELOC_NDS32_RELAX_ENTRY
+ENUMX
+  BFD_RELOC_NDS32_GOT_SUFF
+ENUMX
+  BFD_RELOC_NDS32_GOTOFF_SUFF
+ENUMX
+  BFD_RELOC_NDS32_PLT_GOT_SUFF
+ENUMX
+  BFD_RELOC_NDS32_MULCALL_SUFF
+ENUMX
+  BFD_RELOC_NDS32_PTR
+ENUMX
+  BFD_RELOC_NDS32_PTR_COUNT
+ENUMX
+  BFD_RELOC_NDS32_PTR_RESOLVED
+ENUMX
+  BFD_RELOC_NDS32_PLTBLOCK
+ENUMX
+  BFD_RELOC_NDS32_RELAX_REGION_BEGIN
+ENUMX
+  BFD_RELOC_NDS32_RELAX_REGION_END
+ENUMX
+  BFD_RELOC_NDS32_MINUEND
+ENUMX
+  BFD_RELOC_NDS32_SUBTRAHEND
+ENUMX
+  BFD_RELOC_NDS32_DIFF8
+ENUMX
+  BFD_RELOC_NDS32_DIFF16
+ENUMX
+  BFD_RELOC_NDS32_DIFF32
+ENUMX
+  BFD_RELOC_NDS32_DIFF_ULEB128
+ENUMX
+  BFD_RELOC_NDS32_25_ABS
+ENUMX
+  BFD_RELOC_NDS32_DATA
+ENUMX
+  BFD_RELOC_NDS32_TRAN
+ENUMX
+  BFD_RELOC_NDS32_17IFC_PCREL
+ENUMX
+  BFD_RELOC_NDS32_10IFCU_PCREL
+ENUMDOC
+  relaxation relative relocation types
+
+
 ENUM
   BFD_RELOC_V850_9_PCREL
 ENUMDOC

bfd/targets.c

@@ -673,6 +673,10 @@ extern const bfd_target bfd_elf32_ntradbigmips_vec;
 extern const bfd_target bfd_elf32_ntradlittlemips_vec;
 extern const bfd_target bfd_elf32_ntradbigmips_freebsd_vec;
 extern const bfd_target bfd_elf32_ntradlittlemips_freebsd_vec;
+extern const bfd_target bfd_elf32_nds32be_vec;
+extern const bfd_target bfd_elf32_nds32le_vec;
+extern const bfd_target bfd_elf32_nds32belin_vec;
+extern const bfd_target bfd_elf32_nds32lelin_vec;
 extern const bfd_target bfd_elf32_openrisc_vec;
 extern const bfd_target bfd_elf32_or32_big_vec;
 extern const bfd_target bfd_elf32_pj_vec;
@@ -1061,6 +1065,10 @@ static const bfd_target * const _bfd_target_vector[] =
 	&bfd_elf32_ntradbigmips_freebsd_vec,
 	&bfd_elf32_ntradlittlemips_freebsd_vec,
 #endif
+	&bfd_elf32_nds32be_vec,
+	&bfd_elf32_nds32le_vec,
+	&bfd_elf32_nds32belin_vec,
+	&bfd_elf32_nds32lelin_vec,
 	&bfd_elf32_openrisc_vec,
 	&bfd_elf32_or32_big_vec,
 	&bfd_elf32_pj_vec,

binutils/ChangeLog

@@ -1,3 +1,18 @@
+2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
+	    Wei-Cheng Wang  <cole945@gmail.com>
+
+	* readelf.c: Include elf/nds32.h
+	(guess_is_rela): Add case for EM_NDS32.
+	(dump_relocations): Add case for EM_NDS32.
+	(decode_NDS32_machine_flags): New.
+	(get_machine_flags): Add case for EM_NDS32.
+	(is_32bit_abs_reloc): Likewise.
+	(is_16bit_abs_reloc): Likewise.
+	(process_nds32_specific): New.
+	(process_arch_specific): Add case for EM_NDS32.
+	* NEWS: Announce Andes nds32 support.
+	* MAINTAINERS: Add nds32 maintainers.
+
 2013-12-10  Roland McGrath  <mcgrathr@google.com>
 
 	* Makefile.am (install-exec-local): Prefix libtool invocation with

binutils/MAINTAINERS

@@ -109,6 +109,8 @@ responsibility among the other maintainers.
   MN10300	   Alexandre Oliva <aoliva@redhat.com>
   Moxie		   Anthony Green <green@moxielogic.com>
   MSP430	   Dmitry Diky <diwil@spec.ru>
+  NDS32		   Kuan-Lin Chen <kuanlinchentw@gmail.com>
+  NDS32		   Wei-Cheng Wang <cole945@gmail.com>
   NetBSD support   Matt Thomas <matt@netbsd.org>
   Nios II	   Sandra Loosemore <sandra@codesourcery.com>
   Nios II	   Andrew Jenner <andrew@codesourcery.com>

binutils/NEWS

@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Add support for the Andes NDS32.
+
 Changes in 2.24:
 
 * Objcopy now supports wildcard characters in command line options that take

binutils/readelf.c

@@ -131,6 +131,7 @@
 #include "elf/moxie.h"
 #include "elf/mt.h"
 #include "elf/msp430.h"
+#include "elf/nds32.h"
 #include "elf/nios2.h"
 #include "elf/or32.h"
 #include "elf/pj.h"
@@ -626,6 +627,7 @@ guess_is_rela (unsigned int e_machine)
     case EM_MSP430:
     case EM_MSP430_OLD:
     case EM_MT:
+    case EM_NDS32:
     case EM_NIOS32:
     case EM_PPC64:
     case EM_PPC:
@@ -1144,6 +1146,10 @@ dump_relocations (FILE * file,
 	  rtype = elf_msp430_reloc_type (type);
 	  break;
 
+	case EM_NDS32:
+	  rtype = elf_nds32_reloc_type (type);
+	  break;
+
 	case EM_PPC:
 	  rtype = elf_ppc_reloc_type (type);
 	  break;
@@ -2307,6 +2313,207 @@ decode_ARM_machine_flags (unsigned e_flags, char buf[])
     strcat (buf,_(", <unknown>"));
 }
 
+static void
+decode_NDS32_machine_flags (unsigned e_flags, char buf[], size_t size)
+{
+  unsigned abi;
+  unsigned arch;
+  unsigned config;
+  unsigned version;
+  int has_fpu = 0;
+  int r = 0;
+
+  static const char *ABI_STRINGS[] =
+  {
+    "ABI v0", /* use r5 as return register; only used in N1213HC */
+    "ABI v1", /* use r0 as return register */
+    "ABI v2", /* use r0 as return register and don't reserve 24 bytes for arguments */
+    "ABI v2fp", /* for FPU */
+    "AABI"
+  };
+  static const char *VER_STRINGS[] =
+  {
+    "Andes ELF V1.3 or older",
+    "Andes ELF V1.3.1",
+    "Andes ELF V1.4"
+  };
+  static const char *ARCH_STRINGS[] =
+  {
+    "",
+    "Andes Star v1.0",
+    "Andes Star v2.0",
+    "Andes Star v3.0",
+    "Andes Star v3.0m"
+  };
+
+  abi = EF_NDS_ABI & e_flags;
+  arch = EF_NDS_ARCH & e_flags;
+  config = EF_NDS_INST & e_flags;
+  version = EF_NDS32_ELF_VERSION & e_flags;
+
+  memset (buf, 0, size);
+
+  switch (abi)
+    {
+    case E_NDS_ABI_V0:
+    case E_NDS_ABI_V1:
+    case E_NDS_ABI_V2:
+    case E_NDS_ABI_V2FP:
+    case E_NDS_ABI_AABI:
+      /* In case there are holes in the array.  */
+      r += snprintf (buf + r, size - r, ", %s", ABI_STRINGS[abi >> EF_NDS_ABI_SHIFT]);
+      break;
+
+    default:
+      r += snprintf (buf + r, size - r, ", <unrecognized ABI>");
+      break;
+    }
+
+  switch (version)
+    {
+    case E_NDS32_ELF_VER_1_2:
+    case E_NDS32_ELF_VER_1_3:
+    case E_NDS32_ELF_VER_1_4:
+      r += snprintf (buf + r, size - r, ", %s", VER_STRINGS[version >> EF_NDS32_ELF_VERSION_SHIFT]);
+      break;
+
+    default:
+      r += snprintf (buf + r, size - r, ", <unrecognized ELF version number>");
+      break;
+    }
+
+  if (E_NDS_ABI_V0 == abi)
+    {
+      /* OLD ABI; only used in N1213HC, has performance extension 1.  */
+      r += snprintf (buf + r, size - r, ", Andes Star v1.0, N1213HC, MAC, PERF1");
+      if (arch == E_NDS_ARCH_STAR_V1_0)
+	r += snprintf (buf + r, size -r, ", 16b"); /* has 16-bit instructions */
+      return;
+    }
+
+  switch (arch)
+    {
+    case E_NDS_ARCH_STAR_V1_0:
+    case E_NDS_ARCH_STAR_V2_0:
+    case E_NDS_ARCH_STAR_V3_0:
+    case E_NDS_ARCH_STAR_V3_M:
+      r += snprintf (buf + r, size - r, ", %s", ARCH_STRINGS[arch >> EF_NDS_ARCH_SHIFT]);
+      break;
+
+    default:
+      r += snprintf (buf + r, size - r, ", <unrecognized architecture>");
+      /* ARCH version determines how the e_flags are interpreted.
+	 If it is unknown, we cannot proceed.  */
+      return;
+    }
+
+  /* Newer ABI; Now handle architecture specific flags.  */
+  if (arch == E_NDS_ARCH_STAR_V1_0)
+    {
+      if (config & E_NDS32_HAS_MFUSR_PC_INST)
+	r += snprintf (buf + r, size -r, ", MFUSR_PC");
+
+      if (!(config & E_NDS32_HAS_NO_MAC_INST))
+	r += snprintf (buf + r, size -r, ", MAC");
+
+      if (config & E_NDS32_HAS_DIV_INST)
+	r += snprintf (buf + r, size -r, ", DIV");
+
+      if (config & E_NDS32_HAS_16BIT_INST)
+	r += snprintf (buf + r, size -r, ", 16b");
+    }
+  else
+    {
+      if (config & E_NDS32_HAS_MFUSR_PC_INST)
+	{
+	  if (version <= E_NDS32_ELF_VER_1_3)
+	    r += snprintf (buf + r, size -r, ", [B8]");
+	  else
+	    r += snprintf (buf + r, size -r, ", EX9");
+	}
+
+      if (config & E_NDS32_HAS_MAC_DX_INST)
+	r += snprintf (buf + r, size -r, ", MAC_DX");
+
+      if (config & E_NDS32_HAS_DIV_DX_INST)
+	r += snprintf (buf + r, size -r, ", DIV_DX");
+
+      if (config & E_NDS32_HAS_16BIT_INST)
+	{
+	  if (version <= E_NDS32_ELF_VER_1_3)
+	    r += snprintf (buf + r, size -r, ", 16b");
+	  else
+	    r += snprintf (buf + r, size -r, ", IFC");
+	}
+    }
+
+  if (config & E_NDS32_HAS_EXT_INST)
+    r += snprintf (buf + r, size -r, ", PERF1");
+
+  if (config & E_NDS32_HAS_EXT2_INST)
+    r += snprintf (buf + r, size -r, ", PERF2");
+
+  if (config & E_NDS32_HAS_FPU_INST)
+    {
+      has_fpu = 1;
+      r += snprintf (buf + r, size -r, ", FPU_SP");
+    }
+
+  if (config & E_NDS32_HAS_FPU_DP_INST)
+    {
+      has_fpu = 1;
+      r += snprintf (buf + r, size -r, ", FPU_DP");
+    }
+
+  if (config & E_NDS32_HAS_FPU_MAC_INST)
+    {
+      has_fpu = 1;
+      r += snprintf (buf + r, size -r, ", FPU_MAC");
+    }
+
+  if (has_fpu)
+    {
+      switch ((config & E_NDS32_FPU_REG_CONF) >> E_NDS32_FPU_REG_CONF_SHIFT)
+	{
+	case E_NDS32_FPU_REG_8SP_4DP:
+	  r += snprintf (buf + r, size -r, ", FPU_REG:8/4");
+	  break;
+	case E_NDS32_FPU_REG_16SP_8DP:
+	  r += snprintf (buf + r, size -r, ", FPU_REG:16/8");
+	  break;
+	case E_NDS32_FPU_REG_32SP_16DP:
+	  r += snprintf (buf + r, size -r, ", FPU_REG:32/16");
+	  break;
+	case E_NDS32_FPU_REG_32SP_32DP:
+	  r += snprintf (buf + r, size -r, ", FPU_REG:32/32");
+	  break;
+	}
+    }
+
+  if (config & E_NDS32_HAS_AUDIO_INST)
+    r += snprintf (buf + r, size -r, ", AUDIO");
+
+  if (config & E_NDS32_HAS_STRING_INST)
+    r += snprintf (buf + r, size -r, ", STR");
+
+  if (config & E_NDS32_HAS_REDUCED_REGS)
+    r += snprintf (buf + r, size -r, ", 16REG");
+
+  if (config & E_NDS32_HAS_VIDEO_INST)
+    {
+      if (version <= E_NDS32_ELF_VER_1_3)
+	r += snprintf (buf + r, size -r, ", VIDEO");
+      else
+	r += snprintf (buf + r, size -r, ", SATURATION");
+    }
+
+  if (config & E_NDS32_HAS_ENCRIPT_INST)
+    r += snprintf (buf + r, size -r, ", ENCRP");
+
+  if (config & E_NDS32_HAS_L2C_INST)
+    r += snprintf (buf + r, size -r, ", L2C");
+}
+
 static char *
 get_machine_flags (unsigned e_flags, unsigned e_machine)
 {
@@ -2649,6 +2856,10 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
 	    }
 	  break;
 
+	case EM_NDS32:
+	  decode_NDS32_machine_flags (e_flags, buf, sizeof buf);
+	  break;
+
 	case EM_SH:
 	  switch ((e_flags & EF_SH_MACH_MASK))
 	    {
@@ -10261,6 +10472,8 @@ is_32bit_abs_reloc (unsigned int reloc_type)
       return reloc_type == 1; /* R_MSP430_32 or R_MSP320_ABS32.  */
     case EM_MT:
       return reloc_type == 2; /* R_MT_32.  */
+    case EM_NDS32:
+      return reloc_type == 20; /* R_NDS32_RELA.  */
     case EM_ALTERA_NIOS2:
       return reloc_type == 12; /* R_NIOS2_BFD_RELOC_32.  */
     case EM_NIOS32:
@@ -10514,6 +10727,8 @@ is_16bit_abs_reloc (unsigned int reloc_type)
 	return reloc_type == 2; /* R_MSP430_ABS16.  */
     case EM_MSP430_OLD:
       return reloc_type == 5; /* R_MSP430_16_BYTE.  */
+    case EM_NDS32:
+      return reloc_type == 19; /* R_NDS32_RELA.  */
     case EM_ALTERA_NIOS2:
       return reloc_type == 13; /* R_NIOS2_BFD_RELOC_16.  */
     case EM_NIOS32:
@@ -10577,6 +10792,12 @@ is_none_reloc (unsigned int reloc_type)
       return reloc_type == 0;
     case EM_AARCH64:
       return reloc_type == 0 || reloc_type == 256;
+    case EM_NDS32:
+      return (reloc_type == 0       /* R_XTENSA_NONE.  */
+	      || reloc_type == 204  /* R_NDS32_DIFF8.  */
+	      || reloc_type == 205  /* R_NDS32_DIFF16.  */
+	      || reloc_type == 206  /* R_NDS32_DIFF32.  */
+	      || reloc_type == 207  /* R_NDS32_ULEB128.  */);
     case EM_XTENSA_OLD:
     case EM_XTENSA:
       return (reloc_type == 0      /* R_XTENSA_NONE.  */
@@ -12981,6 +13202,40 @@ process_mips_specific (FILE * file)
   return 1;
 }
 
+static int
+process_nds32_specific (FILE * file)
+{
+  Elf_Internal_Shdr *sect = NULL;
+
+  sect = find_section (".nds32_e_flags");
+  if (sect != NULL)
+    {
+      unsigned int *flag;
+
+      printf ("\nNDS32 elf flags section:\n");
+      flag = get_data (NULL, file, sect->sh_offset, 1,
+		       sect->sh_size, _("NDS32 elf flags section"));
+
+      switch ((*flag) & 0x3)
+	{
+	case 0:
+	  printf ("(VEC_SIZE):\tNo entry.\n");
+	  break;
+	case 1:
+	  printf ("(VEC_SIZE):\t4 bytes\n");
+	  break;
+	case 2:
+	  printf ("(VEC_SIZE):\t16 bytes\n");
+	  break;
+	case 3:
+	  printf ("(VEC_SIZE):\treserved\n");
+	  break;
+	}
+    }
+
+  return TRUE;
+}
+
 static int
 process_gnu_liblist (FILE * file)
 {
@@ -13807,6 +14062,9 @@ process_arch_specific (FILE * file)
     case EM_MIPS_RS3_LE:
       return process_mips_specific (file);
       break;
+    case EM_NDS32:
+      return process_nds32_specific (file);
+      break;
     case EM_PPC:
       return process_power_specific (file);
       break;

binutils/testsuite/ChangeLog

@@ -1,3 +1,9 @@
+2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
+	    Wei-Cheng Wang  <cole945@gmail.com>
+
+	* binutils-all/objdump.exp: Add NDS32 cpu.
+	* binutils-all/readelf.r: Skip extra reloc created by NDS32.
+
 2013-12-12  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR binutils/16318

binutils/testsuite/binutils-all/objdump.exp

@@ -39,8 +39,8 @@ set cpus_expected [list]
 lappend cpus_expected aarch64 alpha arc arm cris
 lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 i860 i960 ip2022
 lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k m88k MCore MicroBlaze
-lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 ns32k pj powerpc pyramid
+lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nds32 n1h_v3 ns32k 
-lappend cpus_expected romp rs6000 s390 sh sparc
+lappend cpus_expected pj powerpc pyramid romp rs6000 s390 sh sparc
 lappend cpus_expected tahoe tic54x tic80 tilegx tms320c30 tms320c4x tms320c54x
 lappend cpus_expected v850 vax we32k x86-64 xscale xtensa z8k z8001 z8002
 

binutils/testsuite/binutils-all/readelf.r

@@ -1,4 +1,6 @@
 
-Relocation section '.rel.*text' at offset 0x.* contains 1 entries:
+Relocation section '.rel.*text' at offset 0x.* contains . entries:
  Offset     Info    Type            Sym.Value  Sym. Name.*
+# NDS32 targets puts R_NDS32_RELAX_ENT here
+#...
 00000004  [0-9A-Fa-f]+ *R_.*00000000   external_symbol.*

binutils/testsuite/binutils-all/readelf.s

@@ -6,7 +6,7 @@ Section Headers:
 # On the normal MIPS systems, sections must be aligned to 16 byte
 # boundaries. On IA64, text sections are aligned to 16 byte boundaries.
  +\[ 1\] .text +PROGBITS +00000000 0000(34|40) 0000(08|10) 00 +AX +0 +0 +(.|..)
- +\[ 2\] .rel.+text +REL. +0+ 0+.* 00000. 0. +. +1 +4
+ +\[ 2\] .rel.+text +REL. +0+ 0+.* 0000.. 0. +. +1 +4
 # MIPS targets put .rela.text here.
 #...
  +\[ .\] .data +PROGBITS +00000000 0000(3c|48|50) 0000(04|10) 00 +WA +0 +0 +(.|..)

gas/ChangeLog

@@ -1,3 +1,23 @@
+2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
+	    Wei-Cheng Wang  <cole945@gmail.com>
+	    Hsiang-Kai Wang  <hsiangkai@gmail.com>
+	    Hui-Wen Ni  <sabrinanitw@gmail.com>
+
+	* Makefile.am (TARGET_CPU_CFILES): Add config/tc-nds32.c.
+	(TARGET_CPU_HFILES): Add config/tc-nds32.h.
+	* Makefile.in: Regenerate.
+	* configure.in (nds32): Add nds32 target extension config support.
+	* configure.tgt : Add case for nds32-*-elf* and nds32-*-linux*.
+	* configure: Regenerate.
+	* config/tc-nds32.c: New file for nds32.
+	* config/tc-nds32.h: New file for nds32.
+	* doc/Makefile.am (CPU_DOCS): Add c-nds32.texi.
+	* doc/Makefile.in: Regenerate.
+	* doc/as.texinfo: Add nds32 options.
+	* doc/all.texi: Set NDS32.
+	* doc/c-nds32.texi: New file dor nds32 document.
+	* NEWS: Announce Andes nds32 support.
+
 2013-12-10  Roland McGrath  <mcgrathr@google.com>
 
 	* Makefile.am (install-exec-bindir): Prefix libtool invocation

gas/Makefile.am

@@ -164,6 +164,7 @@ TARGET_CPU_CFILES = \
 	config/tc-moxie.c \
 	config/tc-msp430.c \
 	config/tc-mt.c \
+	config/tc-nds32.c \
 	config/tc-nios2.c \
 	config/tc-ns32k.c \
 	config/tc-openrisc.c \
@@ -235,6 +236,7 @@ TARGET_CPU_HFILES = \
 	config/tc-mn10300.h \
 	config/tc-msp430.h \
 	config/tc-mt.h \
+	config/tc-nds32.h \
 	config/tc-nios2.h \
 	config/tc-ns32k.h \
 	config/tc-openrisc.h \

gas/Makefile.in

@@ -433,6 +433,7 @@ TARGET_CPU_CFILES = \
 	config/tc-moxie.c \
 	config/tc-msp430.c \
 	config/tc-mt.c \
+	config/tc-nds32.c \
 	config/tc-nios2.c \
 	config/tc-ns32k.c \
 	config/tc-openrisc.c \
@@ -504,6 +505,7 @@ TARGET_CPU_HFILES = \
 	config/tc-mn10300.h \
 	config/tc-msp430.h \
 	config/tc-mt.h \
+	config/tc-nds32.h \
 	config/tc-nios2.h \
 	config/tc-ns32k.h \
 	config/tc-openrisc.h \
@@ -854,6 +856,7 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-moxie.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-msp430.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-mt.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-nds32.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-nios2.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ns32k.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-openrisc.Po@am__quote@
@@ -1468,6 +1471,20 @@ tc-mt.obj: config/tc-mt.c
 @AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
 @am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-mt.obj `if test -f 'config/tc-mt.c'; then $(CYGPATH_W) 'config/tc-mt.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-mt.c'; fi`
 
+tc-nds32.o: config/tc-nds32.c
+@am__fastdepCC_TRUE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-nds32.o -MD -MP -MF $(DEPDIR)/tc-nds32.Tpo -c -o tc-nds32.o `test -f 'config/tc-nds32.c' || echo '$(srcdir)/'`config/tc-nds32.c
+@am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/tc-nds32.Tpo $(DEPDIR)/tc-nds32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='config/tc-nds32.c' object='tc-nds32.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-nds32.o `test -f 'config/tc-nds32.c' || echo '$(srcdir)/'`config/tc-nds32.c
+
+tc-nds32.obj: config/tc-nds32.c
+@am__fastdepCC_TRUE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-nds32.obj -MD -MP -MF $(DEPDIR)/tc-nds32.Tpo -c -o tc-nds32.obj `if test -f 'config/tc-nds32.c'; then $(CYGPATH_W) 'config/tc-nds32.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-nds32.c'; fi`
+@am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/tc-nds32.Tpo $(DEPDIR)/tc-nds32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='config/tc-nds32.c' object='tc-nds32.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-nds32.obj `if test -f 'config/tc-nds32.c'; then $(CYGPATH_W) 'config/tc-nds32.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-nds32.c'; fi`
+
 tc-nios2.o: config/tc-nios2.c
 @am__fastdepCC_TRUE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-nios2.o -MD -MP -MF $(DEPDIR)/tc-nios2.Tpo -c -o tc-nios2.o `test -f 'config/tc-nios2.c' || echo '$(srcdir)/'`config/tc-nios2.c
 @am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/tc-nios2.Tpo $(DEPDIR)/tc-nios2.Po

gas/NEWS

@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Add support for the Andes NDS32.
+
 Changes in 2.24:
 
 * Add support for the Texas Instruments MSP430X processor.

gas/config/tc-nds32.h

@@ -0,0 +1,264 @@
+/* tc-nds32.h -- Header file for tc-nds32.c.
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GAS.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#ifndef TC_NDS32
+#define TC_NDS32
+
+#include "bfd_stdint.h"
+
+#define LISTING_HEADER \
+  (target_big_endian ? "NDS32 GAS" : "NDS32 GAS Little Endian")
+
+/* The target BFD architecture.  */
+#define TARGET_ARCH		bfd_arch_nds32
+
+/* mapping to mach_table[5] */
+#define ISA_V1      bfd_mach_n1h
+#define ISA_V2      bfd_mach_n1h_v2
+#define ISA_V3      bfd_mach_n1h_v3
+#define ISA_V3M     bfd_mach_n1h_v3m
+
+/* Default to big endian. Please note that for Andes architecture,
+   instructions are always in big-endian format.  */
+#ifndef TARGET_BYTES_BIG_ENDIAN
+#define TARGET_BYTES_BIG_ENDIAN	1
+#endif
+
+/* This is used to construct expressions out of @GOTOFF, @PLT and @GOT
+   symbols.  The relocation type is stored in X_md.  */
+#define O_PIC_reloc O_md1
+
+/* as.c.  */
+/* Extend GAS command line option handling capability.  */
+extern int nds32_parse_option (int, char *);
+extern void nds32_after_parse_args (void);
+/* The endianness of the target format may change based on command
+   line arguments.  */
+extern const char * nds32_target_format (void);
+
+#define md_parse_option(optc, optarg)	nds32_parse_option (optc, optarg)
+#define md_after_parse_args()		nds32_after_parse_args ()
+#define TARGET_FORMAT nds32_target_format()
+
+/* expr.c */
+extern int nds32_parse_name (char const *, expressionS *, enum expr_mode, char *);
+extern bfd_boolean nds32_allow_local_subtract (expressionS *, expressionS *, segT);
+#define md_parse_name(name, exprP, mode, nextcharP) \
+	nds32_parse_name (name, exprP, mode, nextcharP)
+#define md_allow_local_subtract(lhs,rhs,sect)	nds32_allow_local_subtract (lhs, rhs, sect)
+
+/* dwarf2dbg.c.  */
+#define DWARF2_USE_FIXED_ADVANCE_PC		1
+
+/* write.c.  */
+extern long nds32_pcrel_from_section (struct fix *, segT);
+extern bfd_boolean nds32_fix_adjustable (struct fix *);
+extern void nds32_frob_file (void);
+extern void nds32_post_relax_hook (void);
+extern void nds32_frob_file_before_fix (void);
+extern void elf_nds32_final_processing (void);
+extern int nds32_validate_fix_sub (struct fix *, segT);
+extern int nds32_force_relocation (struct fix *);
+extern void nds32_set_section_relocs (asection *, arelent ** , unsigned int);
+
+/* Fill in rs_align_code fragments.  TODO: Review this.  */
+extern void nds32_handle_align (fragS *);
+extern int nds32_relax_frag (segT, fragS *, long);
+extern int tc_nds32_regname_to_dw2regnum (char *);
+extern void tc_nds32_frame_initial_instructions (void);
+
+#define MD_PCREL_FROM_SECTION(fix, sect)	nds32_pcrel_from_section (fix, sect)
+#define TC_FINALIZE_SYMS_BEFORE_SIZE_SEG	0
+#define tc_fix_adjustable(FIX)			nds32_fix_adjustable (FIX)
+#define md_apply_fix(fixP, addn, seg)		nds32_apply_fix (fixP, addn, seg)
+#define md_post_relax_hook			nds32_post_relax_hook ()
+#define tc_frob_file_before_fix()		nds32_frob_file_before_fix ()
+#define elf_tc_final_processing()		elf_nds32_final_processing ()
+/* For DIFF relocations.  The default behavior is inconsistent with the
+   asm internal document.  */
+#define TC_FORCE_RELOCATION_SUB_SAME(FIX, SEC)		\
+  (! SEG_NORMAL (SEC) || TC_FORCE_RELOCATION (FIX))
+#define TC_FORCE_RELOCATION(fix)		nds32_force_relocation (fix)
+#define TC_VALIDATE_FIX_SUB(FIX,SEG)		nds32_validate_fix_sub (FIX,SEG)
+#define SET_SECTION_RELOCS(sec, relocs, n)	nds32_set_section_relocs (sec, relocs, n)
+/* Values passed to md_apply_fix don't include the symbol value.  */
+#define MD_APPLY_SYM_VALUE(FIX)			0
+#define HANDLE_ALIGN(f)				nds32_handle_align (f)
+#undef DIFF_EXPR_OK				/* They should be fixed in linker.  */
+#define md_relax_frag(segment, fragP, stretch)	nds32_relax_frag (segment, fragP, stretch)
+#define WORKING_DOT_WORD			/* We don't need to handle .word strangely.  */
+/* Using to chain fixup with previous fixup.  */
+#define TC_FIX_TYPE struct fix *
+#define TC_INIT_FIX_DATA(fixP)		\
+  do					\
+    {					\
+      fixP->tc_fix_data = NULL;		\
+    }					\
+  while (0)
+
+/* read.c.  */
+/* Extend GAS macro handling capability.  */
+extern void nds32_macro_start (void);
+extern void nds32_macro_end (void);
+extern void nds32_macro_info (void *);
+extern void nds32_start_line_hook (void);
+extern void nds32_elf_section_change_hook (void);
+extern void md_begin (void);
+extern void md_end (void);
+extern int nds32_start_label (int, int);
+extern void nds32_cleanup (void);
+extern void nds32_flush_pending_output (void);
+extern void nds32_cons_align (int);
+extern void nds32_check_label (symbolS *);
+extern void nds32_frob_label (symbolS *);
+extern void nds32_pre_do_align (int, char *, int, int);
+extern void nds32_do_align (int);
+
+#define md_macro_start()			nds32_macro_start ()
+#define md_macro_end()				nds32_macro_end ()
+#define md_macro_info(args)			nds32_macro_info (args)
+#define TC_START_LABEL(C, S, STR)		(C == ':' && nds32_start_label (0, 0))
+#define tc_check_label(label)			nds32_check_label (label)
+#define tc_frob_label(label)			nds32_frob_label (label)
+#define md_end					md_end
+#define md_start_line_hook()			nds32_start_line_hook ()
+#define md_cons_align(n)			nds32_cons_align (n)
+/* COLE: TODO: Review md_do_align.  */
+#define md_do_align(N, FILL, LEN, MAX, LABEL)	\
+  nds32_pre_do_align (N, FILL, LEN, MAX);	\
+  if ((N) > 1 && (subseg_text_p (now_seg)	\
+      || strncmp (now_seg->name, ".gcc_except_table", sizeof(".gcc_except_table") - 1) == 0)) \
+    nds32_do_align (N);				\
+  goto LABEL;
+#define md_elf_section_change_hook()		nds32_elf_section_change_hook ()
+#define md_flush_pending_output()		nds32_flush_pending_output ()
+#define md_cleanup()				nds32_cleanup ()
+#define LOCAL_LABELS_FB				1 /* Permit temporary numeric labels.  */
+
+/* frags.c.  */
+struct nds32_frag_type
+{
+  relax_substateT flag;
+  struct nds32_opcode *opcode;
+  uint32_t insn;
+  /* To Save previos label fixup if existence.  */
+  struct fix *fixup;
+};
+
+extern void nds32_frag_init (fragS *);
+
+#define TC_FRAG_TYPE				struct nds32_frag_type
+#define TC_FRAG_INIT(fragP)			nds32_frag_init (fragP)
+
+/* CFI directive.  */
+extern void nds32_elf_frame_initial_instructions (void);
+extern int tc_nds32_regname_to_dw2regnum (char *);
+
+#define TARGET_USE_CFIPOP			1
+#define DWARF2_DEFAULT_RETURN_COLUMN		30
+#define DWARF2_CIE_DATA_ALIGNMENT		-4
+#define DWARF2_LINE_MIN_INSN_LENGTH		2
+
+#define tc_regname_to_dw2regnum			tc_nds32_regname_to_dw2regnum
+#define tc_cfi_frame_initial_instructions	tc_nds32_frame_initial_instructions
+
+/* COLE: TODO: Review These. They seem to be obsoleted.  */
+#if 1
+#define TC_RELOC_RTSYM_LOC_FIXUP(FIX)				\
+   ((FIX)->fx_addsy == NULL					\
+    || (! S_IS_EXTERNAL ((FIX)->fx_addsy)			\
+	&& ! S_IS_WEAK ((FIX)->fx_addsy)			\
+	&& S_IS_DEFINED ((FIX)->fx_addsy)			\
+	&& ! S_IS_COMMON ((FIX)->fx_addsy)))
+#define TC_HANDLES_FX_DONE
+/* This arranges for gas/write.c to not apply a relocation if
+   obj_fix_adjustable() says it is not adjustable.  */
+#define TC_FIX_ADJUSTABLE(fixP) obj_fix_adjustable (fixP)
+#endif
+
+/* Because linker may relax the code, assemble-time expression
+   optimization is not allowed.  */
+#define md_allow_eh_opt 0
+
+/* For nds32 relax.  */
+enum nds32_br_range
+{
+  BR_RANGE_S256 = 0,
+  BR_RANGE_S16K,
+  BR_RANGE_S64K,
+  BR_RANGE_S16M,
+  BR_RANGE_U4G,
+  BR_RANGE_NUM
+};
+
+enum nds32_ramp
+{
+  NDS32_CREATE_LABLE = 1,
+  NDS32_RELAX = 2,
+  NDS32_ORIGIN = 4,
+  NDS32_CONVERT = 8
+};
+
+typedef struct nds32_relax_fixup_info
+{
+  int offset;
+  int size;
+  /* Reverse branch has to jump to the end of instruction pattern.  */
+  int ramp;
+  enum bfd_reloc_code_real r_type;
+} nds32_relax_fixup_info_t;
+
+typedef struct nds32_cond_field
+{
+  int offset;
+  int bitpos; /* Register position.  */
+  int bitmask; /* Number of register bits.  */
+} nds32_cond_field_t;
+
+/* The max relaxation pattern is 20-bytes including the nop.  */
+#define NDS32_MAXCHAR 20
+/* In current, the max entend number of instruction for one pseudo instruction
+   is 4, but its number of relocation may be 5.  */
+#define MAX_RELAX_NUM 8
+
+typedef struct nds32_relax_info
+{
+  /* Opcode for the instruction.  */
+  const char *opcode;
+  enum nds32_br_range br_range;
+  nds32_cond_field_t cond_field[MAX_RELAX_NUM]; /* TODO: Reuse nds32_field?  */
+  /* Code sequences for different branch range.  */
+  uint32_t relax_code_seq[BR_RANGE_NUM][MAX_RELAX_NUM];
+  nds32_cond_field_t relax_code_condition[BR_RANGE_NUM][MAX_RELAX_NUM];
+  int relax_code_size[BR_RANGE_NUM];
+  int relax_branch_isize[BR_RANGE_NUM];
+  nds32_relax_fixup_info_t relax_fixup[BR_RANGE_NUM][MAX_RELAX_NUM];
+} relax_info_t;
+
+/* Relocation table.  */
+struct nds32_relocation_map
+{
+  unsigned int main_type;
+  /* Number of instructions, {relocations type, instruction type}.  */
+  unsigned int reloc_insn[6][6][3];
+};
+
+#endif /* TC_NDS32 */

gas/configure

@@ -12192,6 +12192,100 @@ _ACEOF
         using_cgen=yes
 	;;
 
+      nds32)
+        # Decide BASELINE, REDUCED_REGS, FPU_DP_EXT, FPU_SP_EXT features
+	# based on arch_name.
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for default configuration of --with-arch" >&5
+$as_echo_n "checking for default configuration of --with-arch... " >&6; }
+	if test "x${with_arch}" != x; then
+	  case ${with_arch} in
+            v2j | v2s | v2f | v2 | v3m | v3j | v3s | v3f | v3 )
+
+cat >>confdefs.h <<_ACEOF
+#define NDS32_DEFAULT_ARCH_NAME "$with_arch"
+_ACEOF
+
+              ;;
+	    *)
+	      as_fn_error "This kind of arch name does *NOT* exist!" "$LINENO" 5
+	      ;;
+          esac
+	fi
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $with_arch" >&5
+$as_echo "$with_arch" >&6; }
+
+        # Decide features one by one.
+        { $as_echo "$as_me:${as_lineno-$LINENO}: checking for default configuration of --enable-dx-regs" >&5
+$as_echo_n "checking for default configuration of --enable-dx-regs... " >&6; }
+	if test "x${enable_dx_regs}" == xyes; then
+
+$as_echo "#define NDS32_DEFAULT_DX_REGS 1" >>confdefs.h
+
+	else
+
+$as_echo "#define NDS32_DEFAULT_DX_REGS 0" >>confdefs.h
+
+	fi
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $enable_dx_regs" >&5
+$as_echo "$enable_dx_regs" >&6; }
+
+        { $as_echo "$as_me:${as_lineno-$LINENO}: checking for default configuration of --enable-perf-ext" >&5
+$as_echo_n "checking for default configuration of --enable-perf-ext... " >&6; }
+	if test "x${enable_perf_ext}" == xno; then
+
+$as_echo "#define NDS32_DEFAULT_PERF_EXT 0" >>confdefs.h
+
+	else
+
+$as_echo "#define NDS32_DEFAULT_PERF_EXT 1" >>confdefs.h
+
+	fi
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $enable_perf_ext" >&5
+$as_echo "$enable_perf_ext" >&6; }
+
+        { $as_echo "$as_me:${as_lineno-$LINENO}: checking for default configuration of --enable-perf-ext2" >&5
+$as_echo_n "checking for default configuration of --enable-perf-ext2... " >&6; }
+	if test "x${enable_perf_ext2}" == xno; then
+
+$as_echo "#define NDS32_DEFAULT_PERF_EXT2 0" >>confdefs.h
+
+	else
+
+$as_echo "#define NDS32_DEFAULT_PERF_EXT2 1" >>confdefs.h
+
+	fi
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $enable_perf_ext2" >&5
+$as_echo "$enable_perf_ext2" >&6; }
+
+        { $as_echo "$as_me:${as_lineno-$LINENO}: checking for default configuration of --enable-string-ext" >&5
+$as_echo_n "checking for default configuration of --enable-string-ext... " >&6; }
+	if test "x${enable_string_ext}" == xno; then
+
+$as_echo "#define NDS32_DEFAULT_STRING_EXT 0" >>confdefs.h
+
+	else
+
+$as_echo "#define NDS32_DEFAULT_STRING_EXT 1" >>confdefs.h
+
+	fi
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $enable_string_ext" >&5
+$as_echo "$enable_string_ext" >&6; }
+
+        { $as_echo "$as_me:${as_lineno-$LINENO}: checking for default configuration of --enable-audio-ext" >&5
+$as_echo_n "checking for default configuration of --enable-audio-ext... " >&6; }
+	if test "x${enable_audio_ext}" == xno; then
+
+$as_echo "#define NDS32_DEFAULT_AUDIO_EXT 0" >>confdefs.h
+
+	else
+
+$as_echo "#define NDS32_DEFAULT_AUDIO_EXT 1" >>confdefs.h
+
+	fi
+	{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $enable_audio_ext" >&5
+$as_echo "$enable_audio_ext" >&6; }
+	;;
+
       i386 | s390 | sparc)
 	if test $this_target = $target ; then
 

gas/configure.in

@@ -363,6 +363,75 @@ changequote([,])dnl
         using_cgen=yes
 	;;
 
+      nds32)
+        # Decide BASELINE, REDUCED_REGS, FPU_DP_EXT, FPU_SP_EXT features
+	# based on arch_name.
+	AC_MSG_CHECKING(for default configuration of --with-arch)
+	if test "x${with_arch}" != x; then
+	  case ${with_arch} in
+            v2j | v2s | v2f | v2 | v3m | v3j | v3s | v3f | v3 )
+	      AC_DEFINE_UNQUOTED(NDS32_DEFAULT_ARCH_NAME, "$with_arch",
+				 [Define value for nds32_arch_name])
+              ;;
+	    *)
+	      AC_MSG_ERROR(This kind of arch name does *NOT* exist!)
+	      ;;
+          esac
+	fi
+	AC_MSG_RESULT($with_arch)
+
+        # Decide features one by one.
+        AC_MSG_CHECKING(for default configuration of --enable-dx-regs)
+	if test "x${enable_dx_regs}" == xyes; then
+	  AC_DEFINE(NDS32_DEFAULT_DX_REGS, 1,
+		    [Define value for nds32_dx_regs])
+	else
+	  AC_DEFINE(NDS32_DEFAULT_DX_REGS, 0,
+		    [Define default value for nds32_dx_regs])
+	fi
+	AC_MSG_RESULT($enable_dx_regs)
+
+        AC_MSG_CHECKING(for default configuration of --enable-perf-ext)
+	if test "x${enable_perf_ext}" == xno; then
+	  AC_DEFINE(NDS32_DEFAULT_PERF_EXT, 0,
+		    [Define value for nds32_perf_ext])
+	else
+	  AC_DEFINE(NDS32_DEFAULT_PERF_EXT, 1,
+		    [Define default value for nds32_perf_ext])
+	fi
+	AC_MSG_RESULT($enable_perf_ext)
+
+        AC_MSG_CHECKING(for default configuration of --enable-perf-ext2)
+	if test "x${enable_perf_ext2}" == xno; then
+	  AC_DEFINE(NDS32_DEFAULT_PERF_EXT2, 0,
+		    [Define value for nds32_perf_ext2])
+	else
+	  AC_DEFINE(NDS32_DEFAULT_PERF_EXT2, 1,
+		    [Define default value for nds32_perf_ext2])
+	fi
+	AC_MSG_RESULT($enable_perf_ext2)
+
+        AC_MSG_CHECKING(for default configuration of --enable-string-ext)
+	if test "x${enable_string_ext}" == xno; then
+	  AC_DEFINE(NDS32_DEFAULT_STRING_EXT, 0,
+		    [Define value for nds32_string_ext])
+	else
+	  AC_DEFINE(NDS32_DEFAULT_STRING_EXT, 1,
+		    [Define default value for nds32_string_ext])
+	fi
+	AC_MSG_RESULT($enable_string_ext)
+
+        AC_MSG_CHECKING(for default configuration of --enable-audio-ext)
+	if test "x${enable_audio_ext}" == xno; then
+	  AC_DEFINE(NDS32_DEFAULT_AUDIO_EXT, 0,
+		    [Define value for nds32_audio_ext])
+	else
+	  AC_DEFINE(NDS32_DEFAULT_AUDIO_EXT, 1,
+		    [Define default value for nds32_audio_ext])
+	fi
+	AC_MSG_RESULT($enable_audio_ext)
+	;;
+
       i386 | s390 | sparc)
 	if test $this_target = $target ; then
 	  AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.])

gas/configure.tgt

@@ -79,6 +79,8 @@ case ${cpu} in
   mips*el)		cpu_type=mips endian=little ;;
   mips*)		cpu_type=mips endian=big ;;
   mt)			cpu_type=mt endian=big ;;
+  nds32be)		cpu_type=nds32 endian=big ;;
+  nds32le)		cpu_type=nds32 endian=little ;;
   or32*)		cpu_type=or32 endian=big ;;
   pjl*)			cpu_type=pj endian=little ;;
   pj*)			cpu_type=pj endian=big ;;
@@ -344,6 +346,9 @@ case ${generic_target} in
 
   msp430-*-*)				fmt=elf ;;
 
+  nds32-*-elf*)				fmt=elf ;;
+  nds32-*-linux*)			fmt=elf em=linux ;;
+
   nios2-*-rtems*)			fmt=elf ;;
   nios2*-linux*)			fmt=elf em=linux ;;
 

gas/doc/Makefile.am

@@ -75,6 +75,7 @@ CPU_DOCS = \
 	c-mt.texi \
 	c-msp430.texi \
 	c-nios2.texi \
+	c-nds32.texi \
 	c-ns32k.texi \
 	c-pdp11.texi \
 	c-pj.texi \

gas/doc/Makefile.in

@@ -317,6 +317,7 @@ CPU_DOCS = \
 	c-mt.texi \
 	c-msp430.texi \
 	c-nios2.texi \
+	c-nds32.texi \
 	c-ns32k.texi \
 	c-pdp11.texi \
 	c-pj.texi \

gas/doc/all.texi

@@ -1,6 +1,4 @@
-@c Copyright 1992, 1993, 1994, 1996, 1997, 1999, 2000, 2001, 2002,
+@c Copyright 1992-2013 Free Software Foundation, Inc.
-@c 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011
-@c Free Software Foundation, Inc.
 @c This file is part of the documentation for the GAS manual
 
 @c Configuration settings for all-inclusive version of manual
@@ -59,6 +57,7 @@
 @set MS1
 @set MSP430
 @set NIOSII
+@set NDS32
 @set NS32K
 @set PDP11
 @set PJ

gas/doc/as.texinfo

@@ -437,6 +437,18 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-relax-all}] [@b{-relax-section}] [@b{-no-relax}]
    [@b{-EB}] [@b{-EL}]
 @end ifset
+@ifset NDS32
+
+@emph{Target NDS32 options:}
+    [@b{-EL}] [@b{-EB}] [@b{-O}] [@b{-Os}] [@b{-mcpu=@var{cpu}}]
+    [@b{-misa=@var{isa}}] [@b{-mabi=@var{abi}}] [@b{-mall-ext}]
+    [@b{-m[no-]16-bit}]  [@b{-m[no-]perf-ext}] [@b{-m[no-]perf2-ext}]
+    [@b{-m[no-]string-ext}] [@b{-m[no-]dsp-ext}] [@b{-m[no-]mac}] [@b{-m[no-]div}]
+    [@b{-m[no-]audio-isa-ext}] [@b{-m[no-]fpu-sp-ext}] [@b{-m[no-]fpu-dp-ext}]
+    [@b{-m[no-]fpu-fma}] [@b{-mfpu-freg=@var{FREG}}] [@b{-mreduced-regs}]
+    [@b{-mfull-regs}] [@b{-m[no-]dx-regs}] [@b{-mpic}] [@b{-mno-relax}]
+    [@b{-mb2bb}]
+@end ifset
 @ifset PDP11
 
 @emph{Target PDP11 options:}
@@ -1471,6 +1483,25 @@ Meta processor.
 See the info pages for documentation of the MMIX-specific options.
 @end ifset
 
+@ifset NDS32
+
+@ifclear man
+@xref{NDS32 Options}, for the options available when @value{AS} is configured
+for a NDS32 processor.
+@end ifclear
+@c ended inside the included file
+@end ifset
+
+@ifset man
+@c man begin OPTIONS
+The following options are available when @value{AS} is configured for a
+NDS32 processor.
+@c man end
+@c man begin INCLUDE
+@include c-nds32.texi
+@c ended inside the included file
+@end ifset
+
 @c man end
 @ifset PPC
 
@@ -7127,6 +7158,9 @@ subject, see the hardware manufacturer's manual.
 @ifset MSP430
 * MSP430-Dependent::		MSP430 Dependent Features
 @end ifset
+@ifset NDS32
+* NDS32-Dependent::             Andes NDS32 Dependent Features
+@end ifset
 @ifset NIOSII
 * NiosII-Dependent::            Altera Nios II Dependent Features
 @end ifset
@@ -7341,6 +7375,10 @@ family.
 @include c-msp430.texi
 @end ifset
 
+@ifset NDS32
+@include c-nds32.texi
+@end ifset
+
 @ifset NIOSII
 @include c-nios2.texi
 @end ifset

gas/doc/c-nds32.texi

@@ -0,0 +1,299 @@
+@c Copyright 2013 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@c man end
+
+@ifset GENERIC
+@page
+@node NDS32-Dependent
+@chapter NDS32 Dependent Features
+@end ifset
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter NDS32 Dependent Features
+@end ifclear
+
+@cindex NDS32 processor
+The NDS32 processors family includes high-performance and low-power 32-bit
+processors for high-end to low-end.  @sc{gnu} @code{@value{AS}} for NDS32
+architectures supports NDS32 ISA version 3.  For detail about NDS32
+instruction set, please see the AndeStar ISA User Manual which is availible
+at http://www.andestech.com/en/index/index.htm
+
+@menu
+* NDS32 Options::         Assembler options
+* NDS32 Syntax::          High-level assembly macros
+@end menu
+
+@node NDS32 Options
+@section NDS32 Options
+
+@cindex NDS32 options
+@cindex options for NDS32
+The NDS32 configurations of @sc{gnu} @code{@value{AS}} support these
+special options:
+
+@c man begin OPTIONS
+@table @code
+
+@item -O1
+Optimize for performance.
+
+@item -Os
+Optimize for space.
+
+@item -EL
+Produce little endian data output.
+
+@item -EB
+Produce little endian data output.
+
+@item -mpic
+Generate PIC.
+
+@item -mno-fp-as-gp-relax
+Suppress fp-as-gp relaxation for this file.
+
+@item -mb2bb-relax
+Back-to-back branch optimization.
+
+@item -mno-all-relax
+Suppress all relaxation for this file.
+
+@item -march=<arch name>
+Assemble for architecture <arch name> which could be v3, v3j, v3m, v3f,
+v3s, v2, v2j, v2f, v2s.
+
+@item -mbaseline=<baseline>
+Assemble for baseline <baseline> which could be v2, v3, v3m.
+
+@item -mfpu-freg=@var{FREG}
+Specify a FPU configuration.
+@table @code
+@item 0      8 SP /  4 DP registers
+@item 1     16 SP /  8 DP registers
+@item 2     32 SP / 16 DP registers
+@item 3     32 SP / 32 DP registers
+@end table
+
+@item -mabi=@var{abi}
+Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
+
+@item -m[no-]mac
+Enable/Disable Multiply instructions support.
+
+@item -m[no-]div
+Enable/Disable Divide instructions support.
+
+@item -m[no-]16bit-ext
+Enable/Disable 16-bit extension
+
+@item -m[no-]dx-regs
+Enable/Disable d0/d1 registers
+
+@item -m[no-]perf-ext
+Enable/Disable Performance extension
+
+@item -m[no-]perf2-ext
+Enable/Disable Performance extension 2
+
+@item -m[no-]string-ext
+Enable/Disable String extension
+
+@item -m[no-]reduced-regs
+Enable/Disable Reduced Register configuration (GPR16) option
+
+@item -m[no-]audio-isa-ext
+Enable/Disable AUDIO ISA extension
+
+@item -m[no-]fpu-sp-ext
+Enable/Disable FPU SP extension
+
+@item -m[no-]fpu-dp-ext
+Enable/Disable FPU DP extension
+
+@item -m[no-]fpu-fma
+Enable/Disable FPU fused-multiply-add instructions
+
+@item -mall-ext
+Turn on all extensions and instructions support
+@end table
+@c man end
+
+@node NDS32 Syntax
+@section Syntax
+
+@menu
+* NDS32-Chars::                Special Characters
+* NDS32-Regs::                 Register Names
+* NDS32-Ops::                  Pseudo Instructions
+@end menu
+
+@node NDS32-Chars
+@subsection Special Characters
+
+Use @samp{#} at column 1 and @samp{!} anywhere in the line except inside
+quotes.
+
+Multiple instructions in a line are allowed though not recommended and
+should be separated by @samp{;}.
+
+Assembler is not case-sensitive in general except user defined label.
+For example, @samp{jral F1} is different from @samp{jral f1} while it is
+the same as @samp{JRAL F1}.
+
+@node NDS32-Regs
+@subsection Register Names
+@table @code
+@item General purpose registers (GPR)
+There are 32 32-bit general purpose registers $r0 to $r31.
+
+@item Accumulators d0 and d1
+64-bit accumulators: $d0.hi, $d0.lo, $d1.hi, and $d1.lo.
+
+@item Assembler reserved register $ta
+Register $ta ($r15) is reserved for assembler using.
+
+@item Operating system reserved registers $p0 and $p1
+Registers $p0 ($r26) and $p1 ($r27) are used by operating system as scratch
+registers.
+
+@item Frame pointer $fp
+Register $r28 is regarded as the frame pointer.
+
+@item Global pointer
+Register $r29 is regarded as the global pointer.
+
+@item Link pointer
+Register $r30 is regarded as the link pointer.
+
+@item Stack pointer
+Register $r31 is regarded as the stack pointer.
+@end table
+
+@node NDS32-Ops
+@subsection Pseudo Instructions
+@table @code
+@item li rt5,imm32
+load 32-bit integer into register rt5.  @samp{sethi rt5,hi20(imm32)} and then
+@samp{ori rt5,reg,lo12(imm32)}.
+
+@item la rt5,var
+Load 32-bit address of var into register rt5.  @samp{sethi rt5,hi20(var)} and
+then @samp{ori reg,rt5,lo12(var)}
+
+@item l.[bhw] rt5,var
+Load value of var into register rt5.  @samp{sethi $ta,hi20(var)} and then
+@samp{l[bhw]i rt5,[$ta+lo12(var)]}
+
+@item l.[bh]s rt5,var
+Load value of var into register rt5.  @samp{sethi $ta,hi20(var)} and then
+@samp{l[bh]si rt5,[$ta+lo12(var)]}
+
+@item  l.[bhw]p rt5,var,inc
+Load value of var into register rt5 and increment $ta by amount inc.
+@samp{la $ta,var} and then @samp{l[bhw]i.bi rt5,[$ta],inc}
+
+@item l.[bhw]pc rt5,inc
+Continue loading value of var into register rt5 and increment $ta by amount inc.
+@samp{l[bhw]i.bi rt5,[$ta],inc.}
+
+@item l.[bh]sp rt5,var,inc
+Load value of var into register rt5 and increment $ta by amount inc.
+@samp{la $ta,var} and then @samp{l[bh]si.bi rt5,[$ta],inc}
+
+@item l.[bh]spc rt5,inc
+Continue loading value of var into register rt5 and increment $ta by amount inc.
+@samp{l[bh]si.bi rt5,[$ta],inc.}
+
+@item s.[bhw] rt5,var
+Store register rt5 to var.
+@samp{sethi $ta,hi20(var)} and then @samp{s[bhw]i rt5,[$ta+lo12(var)]}
+
+@item s.[bhw]p rt5,var,inc
+Store register rt5 to var and increment $ta by amount inc.
+@samp{la $ta,var} and then @samp{s[bhw]i.bi rt5,[$ta],inc}
+
+@item s.[bhw]pc rt5,inc
+Continue storing register rt5 to var and increment $ta by amount inc.
+@samp{s[bhw]i.bi rt5,[$ta],inc.}
+
+@item not rt5,ra5
+Alias of @samp{nor rt5,ra5,ra5}.
+
+@item neg rt5,ra5
+Alias of @samp{subri rt5,ra5,0}.
+
+@item br rb5
+Depending on how it is assembled, it is translated into @samp{r5 rb5}
+or @samp{jr rb5}.
+
+@item b label
+Branch to label depending on how it is assembled, it is translated into
+@samp{j8 label}, @samp{j label}, or "@samp{la $ta,label} @samp{br $ta}".
+
+@item bral rb5
+Alias of jral br5 depending on how it is assembled, it is translated
+into @samp{jral5 rb5} or @samp{jral rb5}.
+
+@item bal fname
+Alias of jal fname depending on how it is assembled, it is translated into
+@samp{jal fname} or "@samp{la $ta,fname} @samp{bral $ta}".
+
+@item call fname
+Call function fname same as @samp{jal fname}.
+
+@item move rt5,ra5
+For 16-bit, this is @samp{mov55 rt5,ra5}.
+For no 16-bit, this is @samp{ori rt5,ra5,0}.
+
+@item move rt5,var
+This is the same as @samp{l.w rt5,var}.
+
+@item move rt5,imm32
+This is the same as @samp{li rt5,imm32}.
+
+@item pushm ra5,rb5
+Push contents of registers from ra5 to rb5 into stack.
+
+@item push ra5
+Push content of register ra5 into stack. (same @samp{pushm ra5,ra5}).
+
+@item push.d var
+Push value of double-word variable var into stack.
+
+@item push.w var
+Push value of word variable var into stack.
+
+@item push.h var
+Push value of half-word variable var into stack.
+
+@item push.b var
+Push value of byte variable var into stack.
+
+@item pusha var
+Push 32-bit address of variable var into stack.
+
+@item pushi imm32
+Push 32-bit immediate value into stack.
+
+@item popm ra5,rb5
+Pop top of stack values into registers ra5 to rb5.
+
+@item pop rt5
+Pop top of stack value into register. (same as @samp{popm rt5,rt5}.)
+
+@item pop.d var,ra5
+Pop value of double-word variable var from stack using register ra5
+as 2nd scratch register. (1st is $ta)
+
+@item pop.w var,ra5
+Pop value of word variable var from stack using register ra5.
+
+@item pop.h var,ra5
+Pop value of half-word variable var from stack using register ra5.
+
+@item pop.b var,ra5
+Pop value of byte variable var from stack using register ra5.
+
+@end table

gas/testsuite/ChangeLog

@@ -1,3 +1,35 @@
+2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
+
+	* gas/all/gas.exp: Add expected failures for NDS32.
+	* gas/elf/elf.exp: Likewise.
+	* gas/lns/lns.exp: Use alternate test.
+	* gas/macros/irp.d: Skip for NDS32.
+	* gas/macros/macros.exp: Skip some tests for the NDS32.
+	* gas/macros/rept.d: Skip for NDS32.
+	* gas/macros/test3.d: Skip for NDS32.
+	* gas/nds32: New directory.
+	* gas/nds32/alu-1.s: New test.
+	* gas/nds32/alu-1.d: Likewise.
+	* gas/nds32/alu-2.s: Likewise.
+	* gas/nds32/alu-2.d: Likewise.
+	* gas/nds32/br-1.d: Likewise.
+	* gas/nds32/br-1.s: Likewise.
+	* gas/nds32/br-2.d: Likewise.
+	* gas/nds32/br-2.s: Likewise.
+	* gas/nds32/ji-jr.d: Likewise.
+	* gas/nds32/ji-jr.s: Likewise.
+	* gas/nds32/ls.d: Likewise.
+	* gas/nds32/ls.s: Likewise.
+	* gas/nds32/lsi.d: Likewise.
+	* gas/nds32/lsi.s: Likewise.
+	* gas/nds32/to-16bit-v1.d: Likewise.
+	* gas/nds32/to-16bit-v1.s: Likewise.
+	* gas/nds32/to-16bit-v2.d: Likewise.
+	* gas/nds32/to-16bit-v2.s: Likewise.
+	* gas/nds32/to-16bit-v3.d: Likewise.
+	* gas/nds32/to-16bit-v3.s: Likewise.
+	* gas/nds32/nds32.exp: New test driver.
+
 2013-12-07  Mike Frysinger  <vapier@gentoo.org>
 
 	* gas/bfin/bit2.s: Remove +x file mode.

gas/testsuite/gas/all/gas.exp

@@ -101,7 +101,7 @@ case $target_triplet in {
 	# Some targets don't manage to resolve BFD_RELOC_8 for constants.
 	setup_xfail "alpha*-*-*" "*c30*-*-*" "*c4x*-*-*" \
 	    "d\[13\]0v*-*-*" "i860-*-*" "mips*-*-*" \
-	    "pdp11-*-*" "xtensa*-*-*"
+	    "nds32*-*-*" "pdp11-*-*" "xtensa*-*-*"
 	run_dump_test forward
     }
 }
@@ -118,6 +118,7 @@ if { ![is_aout_format] } {
 	{ hppa*-*-hpux* } { }
 	{ mep-*-* } { }
 	{ mmix-*-* } { }
+	{ nds32*-*-* } { }
 	{ tic30*-*-* } { }
 	{ tic4x*-*-* } { }
 	{ tic54x*-*-* } { }
@@ -140,6 +141,7 @@ case $target_triplet in {
     { mn10200-*-* } { }
     { mn10300-*-* } { }
     { msp430*-*-* } { }
+    { nds32*-*-* } { }
     { pdp11-*-* } { }
     { tic30*-*-* } { }
     { tic4x*-*-* } { }
@@ -366,12 +368,13 @@ if {  ([istarget "i*86-*-*pe*"] && ![istarget "i*86-*-openbsd*"]) \
   gas_test "fastcall.s" ""   "" "fastcall labels"
 }
 
-if { ![istarget "bfin-*-*"] } then {
+if { ![istarget "bfin-*-*"] && ![istarget "nds32*-*-*"] } then {
     run_dump_test assign
 }
 run_dump_test sleb128
 run_dump_test sleb128-2
 run_dump_test sleb128-3
+setup_xfail "nds32*-*-*"
 run_dump_test sleb128-4
 run_dump_test sleb128-5
 # .byte is not 8 bits on either tic4x or tic54x
@@ -414,6 +417,7 @@ case $target_triplet in {
     { *c54x*-*-* } { }
     { z80-*-* } { }
     default {
+	setup_xfail "nds32*-*-*"
 	run_dump_test weakref1
 	run_dump_test weakref1g
 	run_dump_test weakref1l

gas/testsuite/gas/elf/elf.exp

@@ -94,6 +94,7 @@ if { [is_elf_format] } then {
     if {![istarget "mn10300-*-*"]
 	&& ![istarget "xtensa*-*-*"]
 	&& ![istarget "msp430*-*-*"]
+	&& ![istarget "nds32*-*-*"]
 	&& ![istarget "am3*-*-*"]} then {
       run_dump_test "ehopt0"
     }
@@ -111,6 +112,7 @@ if { [is_elf_format] } then {
 	    run_dump_test "file"
 	}
     }
+    setup_xfail "nds32*-*-*"
     run_dump_test "group0a"
     run_dump_test "group0b"
     run_dump_test "group0c"

gas/testsuite/gas/lns/lns.exp

@@ -39,6 +39,7 @@ if {
 	 || [istarget cr16-*-*]
 	 || [istarget crx-*-*]
 	 || [istarget msp430-*-*]
+	 || [istarget nds32*-*-*]
 	 || [istarget mn10*-*-*] } {
       run_dump_test "lns-common-1-alt"
       run_dump_test "lns-big-delta"

gas/testsuite/gas/macros/irp.d

@@ -1,7 +1,7 @@
 #objdump: -r
 #name: macro irp
 #darwin (mach-o) reverses relocs.
-#not-target: *-*-darwin*
+#not-target: *-*-darwin* nds32*-*-*
 
 .*: +file format .*
 

gas/testsuite/gas/macros/macros.exp

@@ -21,13 +21,13 @@ if { ![istarget hppa*-*-*] || [istarget *-*-linux*] } {
     run_dump_test test1
 }
 
-if { ![istarget *c54x*-*-*] && ![istarget *c4x*-*-*] } {
+if { ![istarget *c54x*-*-*] && ![istarget *c4x*-*-*] && ![istarget "nds32*-*-*"] } {
     run_dump_test test2
 }
 
 run_dump_test test3
 
-if { ![istarget *c54x*-*-*] && ![istarget *c4x*-*-*] } {
+if { ![istarget *c54x*-*-*] && ![istarget *c4x*-*-*] && ![istarget "nds32*-*-*"] } {
     run_dump_test irp
     run_dump_test rept
     run_dump_test repeat

gas/testsuite/gas/macros/rept.d

@@ -1,7 +1,7 @@
 #objdump: -r
 #name: macro rept
 #darwin (mach-o) reverses relocs.
-#not-target: *-*-darwin*
+#not-target: *-*-darwin* nds32*-*-*
 
 .*: +file format .*
 

gas/testsuite/gas/macros/test3.d

@@ -1,5 +1,6 @@
 #objdump: -r
 #name: macro test 3
+#not-target: nds32*-*-*
 
 .*: +file format .*
 

gas/testsuite/gas/nds32/alu-1.d

@@ -0,0 +1,47 @@
+#objdump: -d --prefix-addresses
+#name: nds32 alu_1 instructions
+#as:
+
+# Test alu_1 instructions
+
+.*:     file format .*
+
+Disassembly of section .text:
+0+0000 <[^>]*> add	\$r0, \$r1, \$r2
+0+0004 <[^>]*> and	\$r0, \$r1, \$r2
+0+0008 <[^>]*> cmovn	\$r0, \$r1, \$r2
+0+000c <[^>]*> cmovz	\$r0, \$r1, \$r2
+0+0010 <[^>]*> nop
+0+0014 <[^>]*> nor	\$r0, \$r1, \$r2
+0+0018 <[^>]*> or	\$r0, \$r1, \$r2
+0+001c <[^>]*> rotr	\$r0, \$r1, \$r2
+0+0020 <[^>]*> rotri	\$r0, \$r1, #1
+0+0024 <[^>]*> seb	\$r0, \$r1
+0+0028 <[^>]*> seh	\$r0, \$r1
+0+002c <[^>]*> sll	\$r0, \$r1, \$r2
+0+0030 <[^>]*> slli	\$r0, \$r1, #1
+0+0034 <[^>]*> slt	\$r0, \$r1, \$r2
+0+0038 <[^>]*> slts	\$r0, \$r1, \$r2
+0+003c <[^>]*> sra	\$r0, \$r1, \$r2
+0+0040 <[^>]*> srai	\$r0, \$r1, #1
+0+0044 <[^>]*> srl	\$r0, \$r1, \$r2
+0+0048 <[^>]*> srli	\$r0, \$r1, #1
+0+004c <[^>]*> sub	\$r0, \$r1, \$r2
+0+0050 <[^>]*> sva	\$r0, \$r1, \$r2
+0+0054 <[^>]*> svs	\$r0, \$r1, \$r2
+0+0058 <[^>]*> wsbh	\$r0, \$r1
+0+005c <[^>]*> xor	\$r0, \$r1, \$r2
+0+0060 <[^>]*> zeh	\$r0, \$r1
+0+0064 <[^>]*> divr	\$r0, \$r1, \$r2, \$r3
+0+0068 <[^>]*> divsr	\$r0, \$r1, \$r2, \$r3
+0+006c <[^>]*> add_slli	\$r0, \$r1, \$r2, #1
+0+0070 <[^>]*> add_srli	\$r0, \$r1, \$r2, #1
+0+0074 <[^>]*> and_slli	\$r0, \$r1, \$r2, #1
+0+0078 <[^>]*> and_srli	\$r0, \$r1, \$r2, #1
+0+007c <[^>]*> bitc	\$r0, \$r1, \$r2
+0+0080 <[^>]*> or_slli	\$r0, \$r1, \$r2, #1
+0+0084 <[^>]*> or_srli	\$r0, \$r1, \$r2, #1
+0+0088 <[^>]*> sub_slli	\$r0, \$r1, \$r2, #1
+0+008c <[^>]*> sub_srli	\$r0, \$r1, \$r2, #1
+0+0090 <[^>]*> xor_slli	\$r0, \$r1, \$r2, #1
+0+0094 <[^>]*> xor_srli	\$r0, \$r1, \$r2, #1

gas/testsuite/gas/nds32/alu-1.s

@@ -0,0 +1,39 @@
+foo:
+	add $r0, $r1, $r2
+	and $r0, $r1, $r2
+	cmovn $r0, $r1, $r2
+	cmovz $r0, $r1, $r2
+	nop
+	nor $r0, $r1, $r2
+	or $r0, $r1, $r2
+	rotr $r0, $r1, $r2
+	rotri $r0, $r1, 1
+	seb $r0, $r1
+	seh $r0, $r1
+	sll $r0, $r1, $r2
+	slli $r0, $r1, 1
+	slt $r0, $r1, $r2
+	slts $r0, $r1, $r2
+	sra $r0, $r1, $r2
+	srai $r0, $r1, 1
+	srl $r0, $r1, $r2
+	srli $r0, $r1, 1
+	sub $r0, $r1, $r2
+	sva $r0, $r1, $r2
+	svs $r0, $r1, $r2
+	wsbh $r0, $r1
+	xor $r0, $r1, $r2
+	zeh $r0, $r1
+	divr $r0, $r1, $r2, $r3
+	divsr $r0, $r1, $r2, $r3
+	add_slli $r0, $r1, $r2, 1
+	add_srli $r0, $r1, $r2, 1
+	and_slli $r0, $r1, $r2, 1
+	and_srli $r0, $r1, $r2, 1
+	bitc $r0, $r1, $r2
+	or_slli $r0, $r1, $r2, 1
+	or_srli $r0, $r1, $r2, 1
+	sub_slli $r0, $r1, $r2, 1
+	sub_srli $r0, $r1, $r2, 1
+	xor_slli $r0, $r1, $r2, 1
+	xor_srli $r0, $r1, $r2, 1

gas/testsuite/gas/nds32/alu-2.d

@@ -0,0 +1,42 @@
+#objdump: -d --prefix-addresses
+#name: nds32 alu_2 instructions
+#as:
+
+# Test alu_2 instructions
+
+.*:     file format .*
+
+Disassembly of section .text:
+0+0000 <[^>]*> madd64	\$d0, \$r0, \$r1
+0+0004 <[^>]*> madds64	\$d0, \$r0, \$r1
+0+0008 <[^>]*> mfusr	\$r0, \$pc
+0+000c <[^>]*> msub64	\$d0, \$r0, \$r1
+0+0010 <[^>]*> msubs64	\$d0, \$r0, \$r1
+0+0014 <[^>]*> mtusr	\$r0, \$pc
+0+0018 <[^>]*> mul	\$r0, \$r1, \$r2
+0+001c <[^>]*> mult32	\$d0, \$r1, \$r2
+0+0020 <[^>]*> mult64	\$d0, \$r1, \$r2
+0+0024 <[^>]*> mults64	\$d0, \$r1, \$r2
+0+0028 <[^>]*> abs	\$r0, \$r1
+0+002c <[^>]*> ave	\$r0, \$r1, \$r2
+0+0030 <[^>]*> bclr	\$r0, \$r1, #1
+0+0034 <[^>]*> bset	\$r0, \$r1, #1
+0+0038 <[^>]*> btgl	\$r0, \$r1, #1
+0+003c <[^>]*> btst	\$r0, \$r1, #1
+0+0040 <[^>]*> clip	\$r0, \$r1, #1
+0+0044 <[^>]*> clips	\$r0, \$r1, #1
+0+0048 <[^>]*> clo	\$r0, \$r1
+0+004c <[^>]*> clz	\$r0, \$r1
+0+0050 <[^>]*> max	\$r0, \$r1, \$r2
+0+0054 <[^>]*> min	\$r0, \$r1, \$r2
+0+0058 <[^>]*> bse	\$r0, \$r1, \$r2
+0+005c <[^>]*> bsp	\$r0, \$r1, \$r2
+0+0060 <[^>]*> ffb	\$r0, \$r1, \$r2
+0+0064 <[^>]*> ffbi	\$r0, \$r1, #0x8
+0+0068 <[^>]*> ffmism	\$r0, \$r1, \$r2
+0+006c <[^>]*> flmism	\$r0, \$r1, \$r2
+0+0070 <[^>]*> maddr32	\$r0, \$r0, \$r1
+0+0074 <[^>]*> msubr32	\$r0, \$r1, \$r2
+0+0078 <[^>]*> mulr64	\$r0, \$r1, \$r2
+0+007c <[^>]*> mulsr64	\$r0, \$r1, \$r2
+

gas/testsuite/gas/nds32/alu-2.s

@@ -0,0 +1,33 @@
+foo:
+	madd64 $d0, $r0, $r1
+	madds64 $d0, $r0, $r1
+	mfusr $r0, $pc
+	msub64 $d0, $r0, $r1
+	msubs64 $d0, $r0, $r1
+	mtusr $r0, $pc
+	mul $r0, $r1, $r2
+	mult32 $d0, $r1, $r2
+	mult64 $d0, $r1, $r2
+	mults64 $d0, $r1, $r2
+	abs $r0, $r1
+	ave $r0, $r1, $r2
+	bclr $r0, $r1, 1
+	bset $r0, $r1, 1
+	btgl $r0, $r1, 1
+	btst $r0, $r1, 1
+	clip $r0, $r1, 1
+	clips $r0, $r1, 1
+	clo $r0, $r1
+	clz $r0, $r1
+	max $r0, $r1, $r2
+	min $r0, $r1, $r2
+	bse $r0, $r1, $r2
+	bsp $r0, $r1, $r2
+	ffb $r0, $r1, $r2
+	ffbi $r0, $r1, 1
+	ffmism $r0, $r1, $r2
+	flmism $r0, $r1, $r2
+	maddr32 $r0, $r0, $r1
+	msubr32 $r0, $r1, $r2
+	mulr64 $r0, $r1, $r2
+	mulsr64 $r0, $r1, $r2

gas/testsuite/gas/nds32/br-1.d

@@ -0,0 +1,15 @@
+#objdump: -dr --prefix-addresses
+#name: nds32 branch 1 instructions
+#as:
+
+# Test br-1 instructions
+
+.*:     file format .*
+
+Disassembly of section .text:
+0+0000 <[^>]*> beq	\$r0, \$r1, 00000000 <foo>
+			0: R_NDS32_15_PCREL_RELA	.text
+			0: R_NDS32_RELAX_ENTRY	.text
+0+0004 <[^>]*> bne	\$r0, \$r1, 00000004 <foo\+0x4>
+			4: R_NDS32_15_PCREL_RELA	.text
+

gas/testsuite/gas/nds32/br-1.s

@@ -0,0 +1,3 @@
+foo:
+	beq $r0, $r1, foo
+	bne $r0, $r1, foo

gas/testsuite/gas/nds32/br-2.d

@@ -0,0 +1,25 @@
+#objdump: -dr --prefix-addresses
+#name: nds32 branch 2 instructions
+#as:
+
+# Test br-2 instructions
+
+.*:     file format .*
+
+Disassembly of section .text:
+0+0000 <[^>]*> beqz	\$r0, 00000000 <foo>
+			0: R_NDS32_17_PCREL_RELA	.text
+			0: R_NDS32_RELAX_ENTRY	.text
+0+0004 <[^>]*> bgez	\$r0, 00000004 <foo\+0x4>
+			4: R_NDS32_17_PCREL_RELA	.text
+0+0008 <[^>]*> bgezal	\$r0, 00000008 <foo\+0x8>
+			8: R_NDS32_17_PCREL_RELA	.text
+0+000c <[^>]*> bgtz	\$r0, 0000000c <foo\+0xc>
+			c: R_NDS32_17_PCREL_RELA	.text
+0+0010 <[^>]*> blez	\$r0, 00000010 <foo\+0x10>
+			10: R_NDS32_17_PCREL_RELA	.text
+0+0014 <[^>]*> bltz	\$r0, 00000014 <foo\+0x14>
+			14: R_NDS32_17_PCREL_RELA	.text
+0+0018 <[^>]*> bltzal	\$r0, 00000018 <foo\+0x18>
+			18: R_NDS32_17_PCREL_RELA	.text
+

gas/testsuite/gas/nds32/br-2.s

@@ -0,0 +1,8 @@
+foo:
+	beqz $r0, foo
+	bgez $r0, foo
+	bgezal $r0, foo
+	bgtz $r0, foo
+	blez $r0, foo
+	bltz $r0, foo
+	bltzal $r0, foo

gas/testsuite/gas/nds32/ji-jr.d

@@ -0,0 +1,18 @@
+#objdump: -dr --prefix-addresses
+#name: nds32 load-store instructions
+#as:
+
+# Test ls instructions
+
+.*:     file format .*
+
+Disassembly of section .text:
+0+0000 <[^>]*> j8	00000000 <foo>
+			0: R_NDS32_9_PCREL_RELA	.text
+			0: R_NDS32_RELAX_ENTRY	.text
+0+0002 <[^>]*> jal	00000002 <foo\+0x2>
+			2: R_NDS32_25_PCREL_RELA	.text
+0+0006 <[^>]*> jr	\$r0
+0+000a <[^>]*> jral	\$lp, \$r0
+0+000e <[^>]*> ret	\$lp
+

gas/testsuite/gas/nds32/ji-jr.s

@@ -0,0 +1,6 @@
+foo:
+	j foo
+	jal foo
+	jr $r0
+	jral $r0
+	ret

gas/testsuite/gas/nds32/ls.d

@@ -0,0 +1,25 @@
+#objdump: -d --prefix-addresses
+#name: nds32 load-store instructions
+#as:
+
+# Test ls instructions
+
+.*:     file format .*
+
+Disassembly of section .text:
+0+0000 <[^>]*> lw	\$r0, \[\$r1 \+ \(\$r2 << 1\)\]
+0+0004 <[^>]*> lh	\$r0, \[\$r1 \+ \(\$r2 << 1\)\]
+0+0008 <[^>]*> lhs	\$r0, \[\$r1 \+ \(\$r2 << 1\)\]
+0+000c <[^>]*> lb	\$r0, \[\$r1 \+ \(\$r2 << 1\)\]
+0+0010 <[^>]*> lbs	\$r0, \[\$r1 \+ \(\$r2 << 1\)\]
+0+0014 <[^>]*> sw	\$r0, \[\$r1 \+ \(\$r2 << 1\)\]
+0+0018 <[^>]*> sh	\$r0, \[\$r1 \+ \(\$r2 << 1\)\]
+0+001c <[^>]*> sb	\$r0, \[\$r1 \+ \(\$r2 << 1\)\]
+0+0020 <[^>]*> lw.bi	\$r0, \[\$r1\], \(\$r2 << 1\)
+0+0024 <[^>]*> lh.bi	\$r0, \[\$r1\], \(\$r2 << 1\)
+0+0028 <[^>]*> lhs.bi	\$r0, \[\$r1\], \(\$r2 << 1\)
+0+002c <[^>]*> lb.bi	\$r0, \[\$r1\], \(\$r2 << 1\)
+0+0030 <[^>]*> lbs.bi	\$r0, \[\$r1\], \(\$r2 << 1\)
+0+0034 <[^>]*> sw.bi	\$r0, \[\$r1\], \(\$r2 << 1\)
+0+0038 <[^>]*> sh.bi	\$r0, \[\$r1\], \(\$r2 << 1\)
+0+003c <[^>]*> sb.bi	\$r0, \[\$r1\], \(\$r2 << 1\)

gas/testsuite/gas/nds32/ls.s

@@ -0,0 +1,17 @@
+foo:
+	lw $r0, [$r1 + ($r2 << 1)]
+	lh $r0, [$r1 + ($r2 << 1)]
+	lhs $r0, [$r1 + ($r2 << 1)]
+	lb $r0, [$r1 + ($r2 << 1)]
+	lbs $r0, [$r1 + ($r2 << 1)]
+	sw $r0, [$r1 + ($r2 << 1)]
+	sh $r0, [$r1 + ($r2 << 1)]
+	sb $r0, [$r1 + ($r2 << 1)]
+	lw.bi $r0, [$r1], $r2 << 1
+	lh.bi $r0, [$r1], $r2 << 1
+	lhs.bi $r0, [$r1], $r2 << 1
+	lb.bi $r0, [$r1], $r2 << 1
+	lbs.bi $r0, [$r1], $r2 << 1
+	sw.bi $r0, [$r1], $r2 << 1
+	sh.bi $r0, [$r1], $r2 << 1
+	sb.bi $r0, [$r1], $r2 << 1

gas/testsuite/gas/nds32/lsi.d

@@ -0,0 +1,26 @@
+#objdump: -d --prefix-addresses
+#name: nds32 load-store immediate instructions
+#as:
+
+# Test lsi instructions
+
+.*:     file format .*
+
+Disassembly of section .text:
+0+0000 <[^>]*> lwi	\$r0, \[\$r1 \+ #4\]
+0+0004 <[^>]*> lhi	\$r0, \[\$r1 \+ #2\]
+0+0008 <[^>]*> lhsi	\$r0, \[\$r1 \+ #-2\]
+0+000c <[^>]*> lbi	\$r0, \[\$r1 \+ #1\]
+0+0010 <[^>]*> lbsi	\$r0, \[\$r1 \+ #-1\]
+0+0014 <[^>]*> swi	\$r0, \[\$r1 \+ #4\]
+0+0018 <[^>]*> shi	\$r0, \[\$r1 \+ #2\]
+0+001c <[^>]*> sbi	\$r0, \[\$r1 \+ #1\]
+0+0020 <[^>]*> lwi.bi	\$r0, \[\$r1\], #4
+0+0024 <[^>]*> lhi.bi	\$r0, \[\$r1\], #2
+0+0028 <[^>]*> lhsi.bi	\$r0, \[\$r1\], #-2
+0+002c <[^>]*> lbi.bi	\$r0, \[\$r1\], #1
+0+0030 <[^>]*> lbsi.bi	\$r0, \[\$r1\], #-1
+0+0034 <[^>]*> swi.bi	\$r0, \[\$r1\], #4
+0+0038 <[^>]*> shi.bi	\$r0, \[\$r1\], #2
+0+003c <[^>]*> sbi.bi	\$r0, \[\$r1\], #1
+

gas/testsuite/gas/nds32/lsi.s

@@ -0,0 +1,17 @@
+foo:
+	lwi $r0, [$r1 + (1 << 2)]
+	lhi $r0, [$r1 + (1 << 1)]
+	lhsi $r0, [$r1 + (-1 << 1)]
+	lbi $r0, [$r1 + 1]
+	lbsi $r0, [$r1 + (-1)]
+	swi $r0, [$r1 + (1 << 2)]
+	shi $r0, [$r1 + (1 << 1)]
+	sbi $r0, [$r1 + 1]
+	lwi.bi $r0, [$r1], (1 << 2)
+	lhi.bi $r0, [$r1], (1 << 1)
+	lhsi.bi $r0, [$r1], (-1 << 1)
+	lbi.bi $r0, [$r1], 1
+	lbsi.bi $r0, [$r1], -1
+	swi.bi $r0, [$r1], (1 << 2)
+	shi.bi $r0, [$r1], (1 << 1)
+	sbi.bi $r0, [$r1], 1

gas/testsuite/gas/nds32/nds32.exp

@@ -0,0 +1,30 @@
+# Copyright (C) 2012-2013 Free Software Foundation, Inc.
+# Contributed by Andes Technology Corporation.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+if { [istarget nds32*] } {
+    run_dump_test "alu-1"
+    run_dump_test "alu-2"
+    run_dump_test "lsi"
+    run_dump_test "ls"
+    run_dump_test "br-1"
+    run_dump_test "br-2"
+    run_dump_test "ji-jr"
+    run_dump_test "to-16bit-v1"
+    run_dump_test "to-16bit-v2"
+    run_dump_test "to-16bit-v3"
+}

gas/testsuite/gas/nds32/to-16bit-v1.d

@@ -0,0 +1,79 @@
+#objdump: -d --prefix-addresses
+#name: nds32 convert 32 to 16 (v1 instructions)
+#as: -Os -mno-reduced-regs
+
+# Test the convert 32bits to 16bits
+
+.*:     file format .*
+
+
+Disassembly of section .text:
+0+0000 .*
+0+0002 .*
+0+0004 .*
+0+0006 .*
+0+0008 .*
+0+000a .*
+0+000c .*
+0+000e .*
+0+0010 .*
+0+0012 .*
+0+0014 .*
+0+0016 .*
+0+0018 .*
+0+001a .*
+0+001c .*
+0+001e .*
+0+0020 .*
+0+0022 .*
+0+0024 .*
+0+0026 .*
+0+0028 .*
+0+002a .*
+0+002c .*
+0+002e .*
+0+0030 .*
+0+0032 .*
+0+0034 .*
+0+0036 .*
+0+0038 .*
+0+003a .*
+0+003c .*
+0+003e .*
+0+0040 .*
+0+0042 .*
+0+0044 .*
+0+0046 .*
+0+0048 .*
+0+004a .*
+0+004c .*
+0+004e .*
+0+0050 .*
+0+0052 .*
+0+0054 .*
+0+0056 .*
+0+0058 .*
+0+005a .*
+0+005c .*
+0+005e .*
+0+0060 .*
+0+0062 .*
+0+0064 .*
+0+0066 .*
+0+0068 .*
+0+006a .*
+0+006c .*
+0+006e .*
+0+0070 .*
+0+0072 .*
+0+0074 .*
+0+0076 .*
+0+0078 .*
+0+007a .*
+0+007c .*
+0+007e .*
+0+0080 .*
+0+0082 .*
+0+0084 .*
+0+0086 .*
+0+0088 .*

gas/testsuite/gas/nds32/to-16bit-v1.s

@@ -0,0 +1,70 @@
+foo:
+	move $r0, $r0
+	move $sp, $sp
+	movi $r0, -16
+	movi $sp, 15
+	add $r0, $r0, $r0
+	add $r19, $sp, $r19
+	sub $r0, $r0, $r0
+	sub $r19, $r19, $sp
+	addi $r0, $r0, 0
+	addi $r19, $r19, 31
+	srai $r0, $r0, 0
+	srai $r19, $r19, 31
+	srli $r0, $r0, 0
+	srli $r19, $r19, 31
+	slli $r0, $r0, 0
+	slli $r7, $r7, 7
+	zeb $r0, $r0
+	zeb $r7, $r7
+	zeh $r0, $r0
+	zeh $r7, $r7
+	seb $r0, $r0
+	seb $r7, $r7
+	seh $r0, $r0
+	seh $r7, $r7
+	andi $r0, $r0, 1
+	andi $r7, $r7, 0x7ff
+	add $r0, $r0, $r0
+	add $r7, $r7, $r7
+	sub $r0, $r0, $r0
+	sub $r7, $r7, $r7
+	addi $r0, $r0, 0
+	addi $r7, $r7, 7
+	lwi $r0, [$r0 + 0]
+	lwi $r7, [$r7 + 28]
+	lwi.bi $r0, [$r0], 0
+	lwi.bi $r7, [$r7], 28
+	lhi $r0, [$r0 + 0]
+	lhi $r7, [$r7 + 14]
+	lbi $r0, [$r0 + 0]
+	lbi $r7, [$r7 + 7]
+	swi $r0, [$r0 + 0]
+	swi $r7, [$r7 + 28]
+	swi.bi $r0, [$r0], 0
+	swi.bi $r7, [$r7], 28
+	shi $r0, [$r0 + 0]
+	shi $r7, [$r7 + 14]
+	sbi $r0, [$r0 + 0]
+	sbi $r7, [$r7 + 7]
+	lwi $r0, [$r0 + 0]
+	lwi $r19, [$sp + 0]
+	swi $r0, [$r0 + 0]
+	swi $r19, [$sp + 0]
+	lwi $r0, [$fp + 0]
+	lwi $r7, [$fp + 508]
+	swi $r0, [$fp + 0]
+	swi $r7, [$fp + 508]
+	jr $r0
+	jr $sp
+	ret $r0
+	ret $sp
+	jral $r0
+	jral $sp
+	slts $r15, $r0, $r0
+	slts $r15, $r19, $sp
+	slt $r15, $r0, $r0
+	slt $r15, $r19, $sp
+	sltsi $r15, $r0, 0
+	sltsi $r15, $r19, 31
+	slti $r15, $r0, 0

gas/testsuite/gas/nds32/to-16bit-v2.d

@@ -0,0 +1,15 @@
+#objdump: -d --prefix-addresses
+#name: nds32 convert 32 to 16 (v2 instructions)
+#as: -Os -mno-reduced-regs
+
+# Test the convert 32bits to 16bits
+
+.*:     file format .*
+
+
+Disassembly of section .text:
+0+0000 .*
+0+0002 .*
+0+0004 .*
+0+0006 .*
+0+0008 .*

gas/testsuite/gas/nds32/to-16bit-v2.s

@@ -0,0 +1,6 @@
+foo:
+addi $sp, $sp, -512
+addi $sp, $sp, 511
+lwi $r0, [$sp + 0]
+lwi $r7, [$sp + 508]
+swi $r0, [$sp + 0]

gas/testsuite/gas/nds32/to-16bit-v3.d

@@ -0,0 +1,25 @@
+#objdump: -d --prefix-addresses
+#name: nds32 convert 32 to 16 (v3 instructions)
+#as: -Os -mno-reduced-regs
+
+# Test the convert 32bits to 16bits
+
+.*:     file format .*
+
+
+Disassembly of section .text:
+0+0000 .*
+0+0002 .*
+0+0004 .*
+0+0006 .*
+0+0008 .*
+0+000a .*
+0+000c .*
+0+000e .*
+0+0010 .*
+0+0012 .*
+0+0014 .*
+0+0016 .*
+0+0018 .*
+0+001a .*
+0+001c .*

gas/testsuite/gas/nds32/to-16bit-v3.s

@@ -0,0 +1,16 @@
+foo:
+andi $r0, $r0, 1
+andi $r7, $r7, 255
+movi $r0, 16
+movi $r19, 47
+subri $r0, $r0, 0
+subri $r7, $r7, 0
+nor $r0, $r0, $r0
+nor $r7, $r7, $r7
+mul $r0, $r0, $r0
+mul $r7, $r7, $r7
+xor $r0, $r0, $r0
+xor $r7, $r7, $r7
+and $r0, $r0, $r0
+and $r7, $r7, $r7
+or $r0, $r0, $r0

include/ChangeLog

@@ -1,3 +1,8 @@
+2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
+	    Wei-Cheng Wang  <cole945@gmail.com>
+
+	* dis-asm.h (print_insn_nds32): Add nds32 target.
+
 2013-12-04  Richard Sandiford  <rdsandiford@googlemail.com>
 
 	* longlong.h: New file.

include/dis-asm.h

@@ -1,7 +1,6 @@
 /* Interface between the opcode library and its callers.
 
-   Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2009, 2010,
+   Copyright 1999-2013 Free Software Foundation, Inc.
-   2011, 2012 Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
@@ -277,6 +276,7 @@ extern int print_insn_mn10300		(bfd_vma, disassemble_info *);
 extern int print_insn_moxie		(bfd_vma, disassemble_info *);
 extern int print_insn_msp430		(bfd_vma, disassemble_info *);
 extern int print_insn_mt                (bfd_vma, disassemble_info *);
+extern int print_insn_nds32		(bfd_vma, disassemble_info *);
 extern int print_insn_ns32k		(bfd_vma, disassemble_info *);
 extern int print_insn_openrisc		(bfd_vma, disassemble_info *);
 extern int print_insn_pdp11		(bfd_vma, disassemble_info *);

include/elf/ChangeLog

@@ -1,3 +1,8 @@
+2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
+	    Wei-Cheng Wang  <cole945@gmail.com>
+
+	* nds32.h: New file for Andes NDS32.
+
 2013-12-07  Mike Frysinger  <vapier@gentoo.org>
 
 	* epiphany.h: Remove +x file mode.

include/elf/nds32.h

@@ -0,0 +1,282 @@
+/* NDS32 ELF support for BFD.
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#ifndef _ELF_NDS32_H
+#define _ELF_NDS32_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_nds32_reloc_type)
+  RELOC_NUMBER (R_NDS32_NONE, 0)
+  /* REL relocations.  */
+  RELOC_NUMBER (R_NDS32_16, 1)
+  RELOC_NUMBER (R_NDS32_32, 2)
+  RELOC_NUMBER (R_NDS32_20, 3)
+  RELOC_NUMBER (R_NDS32_9_PCREL, 4)
+  RELOC_NUMBER (R_NDS32_15_PCREL, 5)
+  RELOC_NUMBER (R_NDS32_17_PCREL, 6)
+  RELOC_NUMBER (R_NDS32_25_PCREL, 7)
+  RELOC_NUMBER (R_NDS32_HI20, 8)
+  RELOC_NUMBER (R_NDS32_LO12S3, 9)
+  RELOC_NUMBER (R_NDS32_LO12S2, 10)
+  RELOC_NUMBER (R_NDS32_LO12S1, 11)
+  RELOC_NUMBER (R_NDS32_LO12S0, 12)
+  RELOC_NUMBER (R_NDS32_SDA15S3, 13)
+  RELOC_NUMBER (R_NDS32_SDA15S2, 14)
+  RELOC_NUMBER (R_NDS32_SDA15S1, 15)
+  RELOC_NUMBER (R_NDS32_SDA15S0, 16)
+  RELOC_NUMBER (R_NDS32_GNU_VTINHERIT, 17)
+  RELOC_NUMBER (R_NDS32_GNU_VTENTRY, 18)
+
+  /* RELA relocations.  */
+  RELOC_NUMBER (R_NDS32_16_RELA, 19)
+  RELOC_NUMBER (R_NDS32_32_RELA, 20)
+  RELOC_NUMBER (R_NDS32_20_RELA, 21)
+  RELOC_NUMBER (R_NDS32_9_PCREL_RELA, 22)
+  RELOC_NUMBER (R_NDS32_15_PCREL_RELA, 23)
+  RELOC_NUMBER (R_NDS32_17_PCREL_RELA, 24)
+  RELOC_NUMBER (R_NDS32_25_PCREL_RELA, 25)
+  RELOC_NUMBER (R_NDS32_HI20_RELA, 26)
+  RELOC_NUMBER (R_NDS32_LO12S3_RELA, 27)
+  RELOC_NUMBER (R_NDS32_LO12S2_RELA, 28)
+  RELOC_NUMBER (R_NDS32_LO12S1_RELA, 29)
+  RELOC_NUMBER (R_NDS32_LO12S0_RELA, 30)
+  RELOC_NUMBER (R_NDS32_SDA15S3_RELA, 31)
+  RELOC_NUMBER (R_NDS32_SDA15S2_RELA, 32)
+  RELOC_NUMBER (R_NDS32_SDA15S1_RELA, 33)
+  RELOC_NUMBER (R_NDS32_SDA15S0_RELA, 34)
+  RELOC_NUMBER (R_NDS32_RELA_GNU_VTINHERIT, 35)
+  RELOC_NUMBER (R_NDS32_RELA_GNU_VTENTRY, 36)
+
+  RELOC_NUMBER (R_NDS32_GOT20, 37)
+  RELOC_NUMBER (R_NDS32_25_PLTREL, 38)
+  RELOC_NUMBER (R_NDS32_COPY, 39)
+  RELOC_NUMBER (R_NDS32_GLOB_DAT, 40)
+  RELOC_NUMBER (R_NDS32_JMP_SLOT, 41)
+  RELOC_NUMBER (R_NDS32_RELATIVE, 42)
+  RELOC_NUMBER (R_NDS32_GOTOFF, 43)
+  RELOC_NUMBER (R_NDS32_GOTPC20, 44)
+  RELOC_NUMBER (R_NDS32_GOT_HI20, 45)
+
+  RELOC_NUMBER (R_NDS32_GOT_LO12, 46)
+  RELOC_NUMBER (R_NDS32_GOTPC_HI20, 47)
+  RELOC_NUMBER (R_NDS32_GOTPC_LO12, 48)
+  RELOC_NUMBER (R_NDS32_GOTOFF_HI20, 49)
+  RELOC_NUMBER (R_NDS32_GOTOFF_LO12, 50)
+  RELOC_NUMBER (R_NDS32_INSN16, 51)
+  RELOC_NUMBER (R_NDS32_LABEL, 52)
+  RELOC_NUMBER (R_NDS32_LONGCALL1, 53)
+  RELOC_NUMBER (R_NDS32_LONGCALL2, 54)
+  RELOC_NUMBER (R_NDS32_LONGCALL3, 55)
+  RELOC_NUMBER (R_NDS32_LONGJUMP1, 56)
+  RELOC_NUMBER (R_NDS32_LONGJUMP2, 57)
+  RELOC_NUMBER (R_NDS32_LONGJUMP3, 58)
+  RELOC_NUMBER (R_NDS32_LOADSTORE, 59)
+  RELOC_NUMBER (R_NDS32_9_FIXED_RELA, 60)
+  RELOC_NUMBER (R_NDS32_15_FIXED_RELA, 61)
+  RELOC_NUMBER (R_NDS32_17_FIXED_RELA, 62)
+  RELOC_NUMBER (R_NDS32_25_FIXED_RELA, 63)
+  RELOC_NUMBER (R_NDS32_PLTREL_HI20, 64)
+  RELOC_NUMBER (R_NDS32_PLTREL_LO12, 65)
+  RELOC_NUMBER (R_NDS32_PLT_GOTREL_HI20, 66)
+  RELOC_NUMBER (R_NDS32_PLT_GOTREL_LO12, 67)
+  RELOC_NUMBER (R_NDS32_SDA12S2_DP_RELA, 68)
+  RELOC_NUMBER (R_NDS32_SDA12S2_SP_RELA, 69)
+  RELOC_NUMBER (R_NDS32_LO12S2_DP_RELA, 70)
+  RELOC_NUMBER (R_NDS32_LO12S2_SP_RELA, 71)
+  RELOC_NUMBER (R_NDS32_LO12S0_ORI_RELA, 72)
+  RELOC_NUMBER (R_NDS32_SDA16S3_RELA, 73)
+  RELOC_NUMBER (R_NDS32_SDA17S2_RELA, 74)
+  RELOC_NUMBER (R_NDS32_SDA18S1_RELA, 75)
+  RELOC_NUMBER (R_NDS32_SDA19S0_RELA, 76)
+  RELOC_NUMBER (R_NDS32_DWARF2_OP1_RELA, 77)
+  RELOC_NUMBER (R_NDS32_DWARF2_OP2_RELA, 78)
+  RELOC_NUMBER (R_NDS32_DWARF2_LEB_RELA, 79)
+  RELOC_NUMBER (R_NDS32_UPDATE_TA_RELA, 80)	/* This is obsoleted.  */
+  RELOC_NUMBER (R_NDS32_9_PLTREL, 81)
+  RELOC_NUMBER (R_NDS32_PLT_GOTREL_LO20, 82)
+  RELOC_NUMBER (R_NDS32_PLT_GOTREL_LO15, 83)
+  RELOC_NUMBER (R_NDS32_PLT_GOTREL_LO19, 84)
+  RELOC_NUMBER (R_NDS32_GOT_LO15, 85)
+  RELOC_NUMBER (R_NDS32_GOT_LO19, 86)
+  RELOC_NUMBER (R_NDS32_GOTOFF_LO15, 87)
+  RELOC_NUMBER (R_NDS32_GOTOFF_LO19, 88)
+  RELOC_NUMBER (R_NDS32_GOT15S2_RELA, 89)
+  RELOC_NUMBER (R_NDS32_GOT17S2_RELA, 90)
+  RELOC_NUMBER (R_NDS32_5_RELA, 91)
+  RELOC_NUMBER (R_NDS32_10_UPCREL_RELA, 92)
+  RELOC_NUMBER (R_NDS32_SDA_FP7U2_RELA, 93)
+  RELOC_NUMBER (R_NDS32_WORD_9_PCREL_RELA, 94)
+  RELOC_NUMBER (R_NDS32_25_ABS_RELA, 95)
+  RELOC_NUMBER (R_NDS32_17IFC_PCREL_RELA, 96)
+  RELOC_NUMBER (R_NDS32_10IFCU_PCREL_RELA, 97)
+
+  RELOC_NUMBER (R_NDS32_RELAX_ENTRY, 192)
+  RELOC_NUMBER (R_NDS32_GOT_SUFF, 193)
+  RELOC_NUMBER (R_NDS32_GOTOFF_SUFF, 194)
+  RELOC_NUMBER (R_NDS32_PLT_GOT_SUFF, 195)
+  RELOC_NUMBER (R_NDS32_MULCALL_SUFF, 196)
+  RELOC_NUMBER (R_NDS32_PTR, 197)
+  RELOC_NUMBER (R_NDS32_PTR_COUNT, 198)
+  RELOC_NUMBER (R_NDS32_PTR_RESOLVED, 199)
+  RELOC_NUMBER (R_NDS32_PLTBLOCK, 200)
+  RELOC_NUMBER (R_NDS32_RELAX_REGION_BEGIN, 201)
+  RELOC_NUMBER (R_NDS32_RELAX_REGION_END, 202)
+  RELOC_NUMBER (R_NDS32_MINUEND, 203)
+  RELOC_NUMBER (R_NDS32_SUBTRAHEND, 204)
+  RELOC_NUMBER (R_NDS32_DIFF8, 205)
+  RELOC_NUMBER (R_NDS32_DIFF16, 206)
+  RELOC_NUMBER (R_NDS32_DIFF32, 207)
+  RELOC_NUMBER (R_NDS32_DIFF_ULEB128, 208)
+  RELOC_NUMBER (R_NDS32_DATA, 209)
+  RELOC_NUMBER (R_NDS32_TRAN, 210)
+  RELOC_NUMBER (R_NDS32_FPBASE, 211)
+
+END_RELOC_NUMBERS (R_NDS32_max)
+
+/* Processor specific section indices.  These sections do not actually
+   exist.  Symbols with a st_shndx field corresponding to one of these
+   values have a special meaning.  */
+
+/* Processor specific flags for the ELF header e_flags field.
+
+   31   28 27		      8 7   4 3       0
+   ---------------------------------------------
+   | ARCH | CONFUGURAION FIELD | ABI | ELF_VER |
+   ---------------------------------------------  */
+
+/* Architechure definition.  */
+
+/* 4-bit (b31-b28) nds32 architecture field.
+   We can have up to 15 architectures; 0000 is for unknown.  */
+#define EF_NDS_ARCH				0xF0000000
+#define EF_NDS_ARCH_SHIFT			28
+/* There could be more architectures. For now, only n1 and n1h.  */
+#define E_NDS_ARCH_STAR_RESERVED		0x00000000
+#define E_NDS_ARCH_STAR_V1_0			0x10000000
+#define E_NDS_ARCH_STAR_V2_0			0x20000000
+#define E_NDS_ARCH_STAR_V3_0			0x30000000
+#define E_NDS_ARCH_STAR_V3_M			0x40000000
+#define E_NDS_ARCH_STAR_V0_9			0x90000000	/* Obsoleted.  */
+/* n1 code.  */
+#define E_N1_ARCH			E_NDS_ARCH_STAR_V0_9
+/* n1h code.  */
+#define E_N1H_ARCH			E_NDS_ARCH_STAR_V1_0
+
+
+/* Configuration field definitioans.  */
+#define EF_NDS_INST				0x0FFFFF00
+
+/* E_NDS_ARCH_STAR_V1_0 configuration fields.
+
+   E_NDS_ARCH_STAR_V2_0 configuration fields.
+   These are discarded in v2.
+     * E_NDS32_HAS_MFUSR_PC_INST	0x00000100
+     * E_NDS32_HAS_DIV_INST		0x00002000
+     * E_NDS32_HAS_NO_MAC_INST		0x00100000
+   These are added in v2.
+     * E_NDS32_HAS_DIV_DX_INST		0x00002000
+     * E_NDS32_HAS_MAC_DX_INST		0x00100000  */
+
+/* MFUSR rt, PC and correct ISYNC, MSYNC instructions.
+   Old N1213HC has no such instructions.  */
+#define E_NDS32_HAS_MFUSR_PC_INST		0x00000100 /* Reclaimed.  */
+#define E_NDS32_HAS_EX9_INST			0x00000100 /* v3, ELF 1.4.  */
+/* C/C++ performance extension instructions.  */
+#define E_NDS32_HAS_EXT_INST			0x00000200
+/* Performance extension set II instructions.  */
+#define E_NDS32_HAS_EXT2_INST			0x00000400
+/* Single precision Floating point processor instructions.  */
+#define E_NDS32_HAS_FPU_INST			0x00000800
+/* Audio instructions with 32-bit audio dx.lo register.  */
+#define E_NDS32_HAS_AUDIO_INST			0x00001000
+/* DIV instructions.  */
+#define E_NDS32_HAS_DIV_INST			0x00002000 /* Reclaimed.  */
+/* DIV instructions using d0/d1.  */
+#define E_NDS32_HAS_DIV_DX_INST			0x00002000 /* v2.  */
+/* 16-bit instructions.  */
+#define E_NDS32_HAS_16BIT_INST			0x00004000 /* Reclaimed.  */
+#define E_NDS32_HAS_IFC_INST			0x00004000 /* v3, ELF 1.4.  */
+/* String operation instructions.  */
+#define E_NDS32_HAS_STRING_INST			0x00008000
+/* Reduced register file.  */
+#define E_NDS32_HAS_REDUCED_REGS		0x00010000
+/* Video instructions.  */
+#define E_NDS32_HAS_VIDEO_INST			0x00020000 /* Reclaimed.  */
+#define E_NDS32_HAS_SATURATION_INST		0x00020000 /* v3, ELF 1.4.  */
+/* Encription instructions.  */
+#define E_NDS32_HAS_ENCRIPT_INST		0x00040000
+/* Doulbe Precision Floating point processor instructions.  */
+#define E_NDS32_HAS_FPU_DP_INST			0x00080000
+/* No MAC instruction used.  */
+#define E_NDS32_HAS_NO_MAC_INST			0x00100000 /* Reclaimed when V2/V3.  */
+/* MAC instruction using d0/d1.  */
+#define E_NDS32_HAS_MAC_DX_INST			0x00100000 /* v2.  */
+/* L2 cache instruction.  */
+#define E_NDS32_HAS_L2C_INST			0x00200000
+/* FPU registers configuration when FPU SP/DP presents; 0x00c00000.  */
+#define E_NDS32_FPU_REG_CONF_SHIFT		22
+#define E_NDS32_FPU_REG_CONF			(0x3 << E_NDS32_FPU_REG_CONF_SHIFT)
+#define E_NDS32_FPU_REG_8SP_4DP			0x0
+#define E_NDS32_FPU_REG_16SP_8DP		0x1
+#define E_NDS32_FPU_REG_32SP_16DP		0x2
+#define E_NDS32_FPU_REG_32SP_32DP		0x3
+/* FPU MAC instruction used.  */
+#define E_NDS32_HAS_FPU_MAC_INST		0x01000000
+/* <<<Empty Check>>>.  */
+#define E_NDS32_NULL				0x02000000
+/* PIC enabled.  */
+#define E_NDS32_HAS_PIC				0x04000000
+/* Use custom section.  */
+#define E_NDS32_HAS_CUSTOM_SEC			0x08000000
+
+/* 4-bit for ABI signature, allow up to 16 ABIs
+   0: for OLD ABI V0, phase out
+   1: for V1 , starting with V0 toolchain
+   2: for V2
+   3: for V2FP (fs0, fs1 as function parameter)
+   4: for AABI  */
+/* Only old N1213HC use V0.
+   New ABI is used due to return register is changed to r0 from r5.  */
+#define EF_NDS_ABI				0x000000F0
+#define EF_NDS_ABI_SHIFT			4
+#define E_NDS_ABI_V0				0x00000000
+#define E_NDS_ABI_V1				0x00000010
+#define E_NDS_ABI_V2				0x00000020
+#define E_NDS_ABI_V2FP				0x00000030
+#define E_NDS_ABI_AABI				0x00000040
+#define E_NDS_ABI_V2FP_PLUS			0x00000050
+
+/* This flag signifies the version of Andes ELF.
+   Some more information may exist somewhere which is TBD.  */
+#define EF_NDS32_ELF_VERSION			0x0000000F
+#define EF_NDS32_ELF_VERSION_SHIFT		0
+
+/* Andes ELF Version 1.3 and before.  */
+#define E_NDS32_ELF_VER_1_2			0x0
+/* Andes ELF Version 1.31.  */
+#define E_NDS32_ELF_VER_1_3			0x1
+/* Andes ELF Version 1.4. Change the way we fix .debug_* and .gcc_except_table.
+   Change three bit for EX9, IFC and SAT.  */
+#define E_NDS32_ELF_VER_1_4			0x2
+
+#endif

include/opcode/ChangeLog

@@ -1,3 +1,8 @@
+2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
+	    Wei-Cheng Wang  <cole945@gmail.com>
+
+	* nds32.h: New file for Andes NDS32.
+
 2013-12-07  Mike Frysinger  <vapier@gentoo.org>
 
 	* bfin.h: Remove +x file mode.

include/opcode/nds32.h

@@ -0,0 +1,829 @@
+/* nds32.h -- Header file for nds32 opcode table
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#ifndef OPCODE_NDS32_H
+#define OPCODE_NDS32_H
+
+/* Registers.  */
+#define REG_R5		5
+#define REG_R8		8
+#define REG_R10		10
+#define REG_R12		12
+#define REG_R15		15
+#define REG_R16		16
+#define REG_R20		20
+#define REG_TA		15
+#define REG_FP		28
+#define REG_GP		29
+#define REG_LP		30
+#define REG_SP		31
+
+/* Macros for extracting fields or making an instruction.  */
+static const int nds32_r45map[] =
+{
+  0, 1, 2,  3,  4,  5,  6,  7,
+  8, 9, 10, 11, 16, 17, 18, 19
+};
+
+static const int nds32_r54map[] =
+{
+   0,  1,  2,  3,  4,  5,  6,  7,
+   8,  9, 10, 11, -1, -1, -1, -1,
+  12, 13, 14, 15, -1, -1, -1, -1,
+  -1, -1, -1, -1, -1, -1, -1, -1
+};
+
+#define __BIT(n)		(1 << (n))
+#define __MASK(n)		(__BIT (n) - 1)
+#define __MF(v, off, bs)	(((v) & __MASK (bs)) << (off))
+#define __GF(v, off, bs)	(((v) >> off) & __MASK (bs))
+#define __SEXT(v, bs)		((((v) & ((1 << (bs)) - 1)) ^ (1 << ((bs) - 1))) - (1 << ((bs) - 1)))
+
+/* Make nds32 instructions.  */
+
+#define N32_TYPE4(op6, rt5, ra5, rb5, rd5, sub5)  \
+	(__MF (N32_OP6_##op6, 25, 6) | __MF (rt5, 20, 5) \
+	 | __MF (ra5, 15, 5) | __MF (rb5, 10, 5) \
+	 | __MF (rd5, 5, 5) | __MF (sub5, 0, 5))
+#define N32_TYPE3(op6, rt5, ra5, rb5, sub10) \
+	(N32_TYPE4 (op6, rt5, ra5, rb5, 0, 0) \
+	 | __MF (sub10, 0, 10))
+#define N32_TYPE2(op6, rt5, ra5, imm15)	\
+	(N32_TYPE3 (op6, rt5, ra5, 0, 0) | __MF (imm15, 0, 15))
+#define N32_TYPE1(op6, rt5, imm20) \
+	(N32_TYPE2 (op6, rt5, 0, 0) | __MF (imm20, 0, 20))
+#define N32_TYPE0(op6, imm25) \
+	(N32_TYPE1 (op6, 0, 0) | __MF (imm25, 0, 25))
+#define N32_ALU1(sub, rt, ra, rb) \
+	N32_TYPE4 (ALU1, rt, ra, rb, 0, N32_ALU1_##sub)
+#define N32_ALU1_SH(sub, rt, ra, rb, rd) \
+	N32_TYPE4 (ALU1, rt, ra, rb, rd, N32_ALU1_##sub)
+#define N32_ALU2(sub, rt, ra, rb) \
+	N32_TYPE3 (ALU2, rt, ra, rb, N32_ALU2_##sub)
+#define N32_BR1(sub, rt, ra, imm14s) \
+	N32_TYPE2 (BR1, rt, ra, (N32_BR1_##sub << 14) | (imm14s & __MASK (14)))
+#define N32_BR2(sub, rt, imm16s) \
+	N32_TYPE1 (BR2, rt, (N32_BR2_##sub << 16) | (imm16s & __MASK (16)))
+#define N32_BR3(sub, rt, imm11s, imm8s) \
+	N32_TYPE1 (BR3, rt, (N32_BR3_##sub << 19) \
+			    | ((imm11s & __MASK (11)) << 8) \
+			    | (imm8s & __MASK (8)))
+#define N32_JI(sub, imm24s) \
+	N32_TYPE0 (JI, (N32_JI_##sub << 24) | (imm24s & __MASK (24)))
+#define N32_JREG(sub, rt, rb, dtit, hint) \
+	N32_TYPE4(JREG, rt, 0, rb, (dtit << 3) | (hint & 7), N32_JREG_##sub)
+#define N32_MEM(sub, rt, ra, rb, sv) \
+	N32_TYPE3 (MEM, rt, ra, rb, (sv << 8) | N32_MEM_##sub)
+
+#define N16_TYPE55(op5, rt5, ra5) \
+	(0x8000 | __MF (N16_T55_##op5, 10, 5) | __MF (rt5, 5, 5) \
+	 | __MF (ra5, 0, 5))
+#define N16_TYPE45(op6, rt4, ra5) \
+	(0x8000 | __MF (N16_T45_##op6, 9, 6) | __MF (rt4, 5, 4) \
+	 | __MF (ra5, 0, 5))
+#define N16_TYPE333(op6, rt3, ra3, rb3)	\
+	(0x8000 | __MF (N16_T333_##op6, 9, 6) | __MF (rt3, 6, 3) \
+	 | __MF (ra3, 3, 3) | __MF (rb3, 0, 3))
+#define N16_TYPE36(op6, rt3, imm6) \
+	(0x8000 | __MF (N16_T36_##op6, 9, 6) | __MF (rt3, 6, 3) \
+	 | __MF (imm6, 0, 6))
+#define N16_TYPE38(op4, rt3, imm8) \
+	(0x8000 | __MF (N16_T38_##op4, 11, 4) | __MF (rt3, 8, 3) \
+	 | __MF (imm8, 0, 8))
+#define N16_TYPE37(op4, rt3, ls, imm7) \
+	(0x8000 | __MF (N16_T37_##op4, 11, 4) | __MF (rt3, 8, 3) \
+	 | __MF (imm7, 0, 7) | __MF (ls, 7, 1))
+#define N16_TYPE5(op10, imm5) \
+	(0x8000 | __MF (N16_T5_##op10, 5, 10) | __MF (imm5, 0, 5))
+#define N16_TYPE8(op7, imm8) \
+	(0x8000 | __MF (N16_T8_##op7, 8, 7) | __MF (imm8, 0, 8))
+#define N16_TYPE9(op6, imm9) \
+	(0x8000 | __MF (N16_T9_##op6, 9, 6) | __MF (imm9, 0, 9))
+#define N16_TYPE10(op5, imm10) \
+	(0x8000 | __MF (N16_T10_##op5, 10, 5) | __MF (imm10, 0, 10))
+#define N16_TYPE25(op8, re, imm5) \
+	(0x8000 | __MF (N16_T25_##op8, 7, 8) | __MF (re, 5, 2) \
+	 | __MF (imm5, 0, 5))
+
+#define N16_MISC33(sub, rt, ra) \
+	N16_TYPE333 (MISC33, rt, ra, N16_MISC33_##sub)
+#define N16_BFMI333(sub, rt, ra) \
+	N16_TYPE333 (BFMI333, rt, ra, N16_BFMI333_##sub)
+
+/* Get instruction fields.
+
+   Macros used for handling 32-bit and 16-bit instructions are
+   prefixed with N32_ and N16_ respectively.  */
+
+#define N32_OP6(insn)		(((insn) >> 25) & 0x3f)
+#define N32_RT5(insn)		(((insn) >> 20) & 0x1f)
+#define N32_RT53(insn)		(N32_RT5 (insn) & 0x7)
+#define N32_RT54(insn)		nds32_r54map[N32_RT5 (insn)]
+#define N32_RA5(insn)		(((insn) >> 15) & 0x1f)
+#define N32_RA53(insn)		(N32_RA5 (insn) & 0x7)
+#define N32_RA54(insn)		nds32_r54map[N32_RA5 (insn)]
+#define N32_RB5(insn)		(((insn) >> 10) & 0x1f)
+#define N32_UB5(insn)		(((insn) >> 10) & 0x1f)
+#define N32_RB53(insn)		(N32_RB5 (insn) & 0x7)
+#define N32_RB54(insn)		nds32_r54map[N32_RB5 (insn)]
+#define N32_RD5(insn)		(((insn) >> 5) & 0x1f)
+#define N32_SH5(insn)		(((insn) >> 5) & 0x1f)
+#define N32_SUB5(insn)		(((insn) >> 0) & 0x1f)
+#define N32_SWID(insn)		(((insn) >> 5) & 0x3ff)
+#define N32_IMMU(insn, bs)	((insn) & __MASK (bs))
+#define N32_IMMS(insn, bs)	((signed) __SEXT (((insn) & __MASK (bs)), bs))
+#define N32_IMM5U(insn)		N32_IMMU (insn, 5)
+#define N32_IMM12S(insn)	N32_IMMS (insn, 12)
+#define N32_IMM14S(insn)	N32_IMMS (insn, 14)
+#define N32_IMM15U(insn)	N32_IMMU (insn, 15)
+#define N32_IMM15S(insn)	N32_IMMS (insn, 15)
+#define N32_IMM16S(insn)	N32_IMMS (insn, 16)
+#define N32_IMM17S(insn)	N32_IMMS (insn, 17)
+#define N32_IMM20S(insn)	N32_IMMS (insn, 20)
+#define N32_IMM20U(insn)	N32_IMMU (insn, 20)
+#define N32_IMM24S(insn)	N32_IMMS (insn, 24)
+
+#define N16_RT5(insn)		(((insn) >> 5) & 0x1f)
+#define N16_RT4(insn)		nds32_r45map[(((insn) >> 5) & 0xf)]
+#define N16_RT3(insn)		(((insn) >> 6) & 0x7)
+#define N16_RT38(insn)		(((insn) >> 8) & 0x7)
+#define N16_RT8(insn)		(((insn) >> 8) & 0x7)
+#define N16_RA5(insn)		((insn) & 0x1f)
+#define N16_RA3(insn)		(((insn) >> 3) & 0x7)
+#define N16_RB3(insn)		((insn) & 0x7)
+#define N16_IMM3U(insn)		N32_IMMU (insn, 3)
+#define N16_IMM5U(insn)		N32_IMMU (insn, 5)
+#define N16_IMM5S(insn)		N32_IMMS (insn, 5)
+#define N16_IMM6U(insn)		N32_IMMU (insn, 6)
+#define N16_IMM7U(insn)		N32_IMMU (insn, 7)
+#define N16_IMM8S(insn)		N32_IMMS (insn, 8)
+#define N16_IMM9U(insn)		N32_IMMU (insn, 9)
+#define N16_IMM10S(insn)	N32_IMMS (insn, 10)
+
+#define IS_WITHIN_U(v, n)	(((v) >> n) == 0)
+#define IS_WITHIN_S(v, n)	IS_WITHIN_U ((v) + (1 << ((n) - 1)), n)
+
+/* Get fields for specific instruction.  */
+#define N32_JREG_T(insn)	(((insn) >> 8) & 0x3)
+#define N32_JREG_HINT(insn)	(((insn) >> 5) & 0x7)
+#define N32_BR2_SUB(insn)	(((insn) >> 16) & 0xf)
+#define N32_COP_SUB(insn)	((insn) & 0xf)
+#define N32_COP_CP(insn)	(((insn) >> 4) & 0x3)
+
+/* Check fields.  */
+#define N32_IS_RT3(insn)	(N32_RT5 (insn) < 8)
+#define N32_IS_RA3(insn)	(N32_RA5 (insn) < 8)
+#define N32_IS_RB3(insn)	(N32_RB5 (insn) < 8)
+#define N32_IS_RT4(insn)	(nds32_r54map[N32_RT5 (insn)] != -1)
+#define N32_IS_RA4(insn)	(nds32_r54map[N32_RA5 (insn)] != -1)
+#define N32_IS_RB4(insn)	(nds32_r54map[N32_RB5 (insn)] != -1)
+
+
+/* These are opcodes for Nxx_TYPE macros.
+   They are prefixed by corresponding TYPE to avoid misusing.  */
+
+enum n32_opcodes
+{
+  /* Main opcodes (OP6).  */
+
+  N32_OP6_LBI = 0x0,
+  N32_OP6_LHI,
+  N32_OP6_LWI,
+  N32_OP6_LDI,
+  N32_OP6_LBI_BI,
+  N32_OP6_LHI_BI,
+  N32_OP6_LWI_BI,
+  N32_OP6_LDI_BI,
+
+  N32_OP6_SBI = 0x8,
+  N32_OP6_SHI,
+  N32_OP6_SWI,
+  N32_OP6_SDI,
+  N32_OP6_SBI_BI,
+  N32_OP6_SHI_BI,
+  N32_OP6_SWI_BI,
+  N32_OP6_SDI_BI,
+
+  N32_OP6_LBSI = 0x10,
+  N32_OP6_LHSI,
+  N32_OP6_LWSI,
+  N32_OP6_DPREFI,
+  N32_OP6_LBSI_BI,
+  N32_OP6_LHSI_BI,
+  N32_OP6_LWSI_BI,
+  N32_OP6_LBGP,
+
+  N32_OP6_LWC = 0x18,
+  N32_OP6_SWC,
+  N32_OP6_LDC,
+  N32_OP6_SDC,
+  N32_OP6_MEM,
+  N32_OP6_LSMW,
+  N32_OP6_HWGP,
+  N32_OP6_SBGP,
+
+  N32_OP6_ALU1 = 0x20,
+  N32_OP6_ALU2,
+  N32_OP6_MOVI,
+  N32_OP6_SETHI,
+  N32_OP6_JI,
+  N32_OP6_JREG,
+  N32_OP6_BR1,
+  N32_OP6_BR2,
+
+  N32_OP6_ADDI = 0x28,
+  N32_OP6_SUBRI,
+  N32_OP6_ANDI,
+  N32_OP6_XORI,
+  N32_OP6_ORI,
+  N32_OP6_BR3,
+  N32_OP6_SLTI,
+  N32_OP6_SLTSI,
+
+  N32_OP6_AEXT = 0x30,
+  N32_OP6_CEXT,
+  N32_OP6_MISC,
+  N32_OP6_BITCI,
+  N32_OP6_0x34,
+  N32_OP6_COP,
+  N32_OP6_0x36,
+  N32_OP6_0x37,
+
+  N32_OP6_SIMD = 0x38,
+
+  /* Sub-opcodes of specific opcode.  */
+
+  /* bit-24 */
+  N32_BR1_BEQ = 0,
+  N32_BR1_BNE = 1,
+
+  /* bit[16:19] */
+  N32_BR2_IFCALL = 0,
+  N32_BR2_BEQZ = 2,
+  N32_BR2_BNEZ = 3,
+  N32_BR2_BGEZ = 4,
+  N32_BR2_BLTZ = 5,
+  N32_BR2_BGTZ = 6,
+  N32_BR2_BLEZ = 7,
+  N32_BR2_BGEZAL = 0xc,
+  N32_BR2_BLTZAL = 0xd,
+
+  /* bit-19 */
+  N32_BR3_BEQC = 0,
+  N32_BR3_BNEC = 1,
+
+  /* bit-24 */
+  N32_JI_J = 0,
+  N32_JI_JAL = 1,
+
+  /* bit[0:4] */
+  N32_JREG_JR = 0,
+  N32_JREG_JRAL = 1,
+  N32_JREG_JRNEZ = 2,
+  N32_JREG_JRALNEZ = 3,
+
+  /* bit[0:4] */
+  N32_ALU1_ADD_SLLI = 0x0,
+  N32_ALU1_SUB_SLLI,
+  N32_ALU1_AND_SLLI,
+  N32_ALU1_XOR_SLLI,
+  N32_ALU1_OR_SLLI,
+  N32_ALU1_ADD = 0x0,
+  N32_ALU1_SUB,
+  N32_ALU1_AND,
+  N32_ALU1_XOR,
+  N32_ALU1_OR,
+  N32_ALU1_NOR,
+  N32_ALU1_SLT,
+  N32_ALU1_SLTS,
+  N32_ALU1_SLLI = 0x8,
+  N32_ALU1_SRLI,
+  N32_ALU1_SRAI,
+  N32_ALU1_ROTRI,
+  N32_ALU1_SLL,
+  N32_ALU1_SRL,
+  N32_ALU1_SRA,
+  N32_ALU1_ROTR,
+  N32_ALU1_SEB = 0x10,
+  N32_ALU1_SEH,
+  N32_ALU1_BITC,
+  N32_ALU1_ZEH,
+  N32_ALU1_WSBH,
+  N32_ALU1_OR_SRLI,
+  N32_ALU1_DIVSR,
+  N32_ALU1_DIVR,
+  N32_ALU1_SVA = 0x18,
+  N32_ALU1_SVS,
+  N32_ALU1_CMOVZ,
+  N32_ALU1_CMOVN,
+  N32_ALU1_ADD_SRLI,
+  N32_ALU1_SUB_SRLI,
+  N32_ALU1_AND_SRLI,
+  N32_ALU1_XOR_SRLI,
+
+  /* bit[0:5], where bit[6:9] == 0 */
+  N32_ALU2_MAX = 0,
+  N32_ALU2_MIN,
+  N32_ALU2_AVE,
+  N32_ALU2_ABS,
+  N32_ALU2_CLIPS,
+  N32_ALU2_CLIP,
+  N32_ALU2_CLO,
+  N32_ALU2_CLZ,
+  N32_ALU2_BSET = 0x8,
+  N32_ALU2_BCLR,
+  N32_ALU2_BTGL,
+  N32_ALU2_BTST,
+  N32_ALU2_BSE,
+  N32_ALU2_BSP,
+  N32_ALU2_FFB,
+  N32_ALU2_FFMISM,
+  N32_ALU2_ADD_SC = 0x10,
+  N32_ALU2_SUB_SC,
+  N32_ALU2_ADD_WC,
+  N32_ALU2_SUB_WC,
+  N32_ALU2_0x14,
+  N32_ALU2_0x15,
+  N32_ALU2_0x16,
+  N32_ALU2_FFZMISM,
+  N32_ALU2_QADD = 0x18,
+  N32_ALU2_QSUB,
+  N32_ALU2_MFUSR = 0x20,
+  N32_ALU2_MTUSR,
+  N32_ALU2_0x22,
+  N32_ALU2_0x23,
+  N32_ALU2_MUL,
+  N32_ALU2_0x25,
+  N32_ALU2_0x26,
+  N32_ALU2_MULTS64 = 0x28,
+  N32_ALU2_MULT64,
+  N32_ALU2_MADDS64,
+  N32_ALU2_MADD64,
+  N32_ALU2_MSUBS64,
+  N32_ALU2_MSUB64,
+  N32_ALU2_DIVS,
+  N32_ALU2_DIV,
+  N32_ALU2_0x30 = 0x30,
+  N32_ALU2_MULT32,
+  N32_ALU2_0x32,
+  N32_ALU2_MADD32,
+  N32_ALU2_0x34,
+  N32_ALU2_MSUB32,
+
+  /* bit[0:5], where bit[6:9] != 0  */
+  N32_ALU2_FFBI = 0xe,
+  N32_ALU2_FLMISM = 0xf,
+  N32_ALU2_MULSR64 = 0x28,
+  N32_ALU2_MULR64 = 0x29,
+  N32_ALU2_MADDR32 = 0x33,
+  N32_ALU2_MSUBR32 = 0x35,
+
+  /* bit[0:5] */
+  N32_MEM_LB = 0,
+  N32_MEM_LH,
+  N32_MEM_LW,
+  N32_MEM_LD,
+  N32_MEM_LB_BI,
+  N32_MEM_LH_BI,
+  N32_MEM_LW_BI,
+  N32_MEM_LD_BI,
+  N32_MEM_SB,
+  N32_MEM_SH,
+  N32_MEM_SW,
+  N32_MEM_SD,
+  N32_MEM_SB_BI,
+  N32_MEM_SH_BI,
+  N32_MEM_SW_BI,
+  N32_MEM_SD_BI,
+  N32_MEM_LBS,
+  N32_MEM_LHS,
+  N32_MEM_LWS, /* Not used.  */
+  N32_MEM_DPREF,
+  N32_MEM_LBS_BI,
+  N32_MEM_LHS_BI,
+  N32_MEM_LWS_BI, /* Not used.  */
+  N32_MEM_0x17, /* Not used.  */
+  N32_MEM_LLW,
+  N32_MEM_SCW,
+  N32_MEM_LBUP = 0x20,
+  N32_MEM_LWUP = 0x22,
+  N32_MEM_SBUP = 0x28,
+  N32_MEM_SWUP = 0x2a,
+
+  /* bit[0:1] */
+  N32_LSMW_LSMW = 0,
+  N32_LSMW_LSMWA,
+  N32_LSMW_LSMWZB,
+
+  /* bit[2:4] */
+  N32_LSMW_BI = 0,
+  N32_LSMW_BIM,
+  N32_LSMW_BD,
+  N32_LSMW_BDM,
+  N32_LSMW_AI,
+  N32_LSMW_AIM,
+  N32_LSMW_AD,
+  N32_LSMW_ADM,
+
+  /* bit[0:4] */
+  N32_MISC_STANDBY = 0,
+  N32_MISC_CCTL,
+  N32_MISC_MFSR,
+  N32_MISC_MTSR,
+  N32_MISC_IRET,
+  N32_MISC_TRAP,
+  N32_MISC_TEQZ,
+  N32_MISC_TNEZ,
+  N32_MISC_DSB = 0x8,
+  N32_MISC_ISB,
+  N32_MISC_BREAK,
+  N32_MISC_SYSCALL,
+  N32_MISC_MSYNC,
+  N32_MISC_ISYNC,
+  N32_MISC_TLBOP,
+  N32_MISC_0xf,
+
+  /* bit[0;4] */
+  N32_SIMD_PBSAD = 0,
+  N32_SIMD_PBSADA = 1,
+
+  /* bit[0:3] */
+  N32_COP_CPE1 = 0,
+  N32_COP_MFCP,
+  N32_COP_CPLW,
+  N32_COP_CPLD,
+  N32_COP_CPE2,
+  N32_COP_CPE3 = 8,
+  N32_COP_MTCP,
+  N32_COP_CPSW,
+  N32_COP_CPSD,
+  N32_COP_CPE4,
+
+  /* cop/0 b[3:0] */
+  N32_FPU_FS1 = 0,
+  N32_FPU_MFCP,
+  N32_FPU_FLS,
+  N32_FPU_FLD,
+  N32_FPU_FS2,
+  N32_FPU_FD1 = 8,
+  N32_FPU_MTCP,
+  N32_FPU_FSS,
+  N32_FPU_FSD,
+  N32_FPU_FD2,
+
+  /* FS1 b[9:6] */
+  N32_FPU_FS1_FADDS = 0,
+  N32_FPU_FS1_FSUBS,
+  N32_FPU_FS1_FCPYNSS,
+  N32_FPU_FS1_FCPYSS,
+  N32_FPU_FS1_FMADDS,
+  N32_FPU_FS1_FMSUBS,
+  N32_FPU_FS1_FCMOVNS,
+  N32_FPU_FS1_FCMOVZS,
+  N32_FPU_FS1_FNMADDS,
+  N32_FPU_FS1_FNMSUBS,
+  N32_FPU_FS1_10,
+  N32_FPU_FS1_11,
+  N32_FPU_FS1_FMULS = 12,
+  N32_FPU_FS1_FDIVS,
+  N32_FPU_FS1_14,
+  N32_FPU_FS1_F2OP = 15,
+
+  /* FS1/F2OP b[14:10] */
+  N32_FPU_FS1_F2OP_FS2D = 0x00,
+  N32_FPU_FS1_F2OP_FSQRTS  = 0x01,
+  N32_FPU_FS1_F2OP_FABSS  = 0x05,
+  N32_FPU_FS1_F2OP_FUI2S  = 0x08,
+  N32_FPU_FS1_F2OP_FSI2S  = 0x0c,
+  N32_FPU_FS1_F2OP_FS2UI  = 0x10,
+  N32_FPU_FS1_F2OP_FS2UI_Z = 0x14,
+  N32_FPU_FS1_F2OP_FS2SI  = 0x18,
+  N32_FPU_FS1_F2OP_FS2SI_Z = 0x1c,
+
+  /* FS2 b[9:6] */
+  N32_FPU_FS2_FCMPEQS = 0x0,
+  N32_FPU_FS2_FCMPLTS = 0x2,
+  N32_FPU_FS2_FCMPLES = 0x4,
+  N32_FPU_FS2_FCMPUNS = 0x6,
+  N32_FPU_FS2_FCMPEQS_E = 0x1,
+  N32_FPU_FS2_FCMPLTS_E = 0x3,
+  N32_FPU_FS2_FCMPLES_E = 0x5,
+  N32_FPU_FS2_FCMPUNS_E = 0x7,
+
+  /* FD1 b[9:6] */
+  N32_FPU_FD1_FADDD = 0,
+  N32_FPU_FD1_FSUBD,
+  N32_FPU_FD1_FCPYNSD,
+  N32_FPU_FD1_FCPYSD,
+  N32_FPU_FD1_FMADDD,
+  N32_FPU_FD1_FMSUBD,
+  N32_FPU_FD1_FCMOVND,
+  N32_FPU_FD1_FCMOVZD,
+  N32_FPU_FD1_FNMADDD,
+  N32_FPU_FD1_FNMSUBD,
+  N32_FPU_FD1_10,
+  N32_FPU_FD1_11,
+  N32_FPU_FD1_FMULD = 12,
+  N32_FPU_FD1_FDIVD,
+  N32_FPU_FD1_14,
+  N32_FPU_FD1_F2OP = 15,
+
+  /* FD1/F2OP b[14:10] */
+  N32_FPU_FD1_F2OP_FD2S = 0x00,
+  N32_FPU_FD1_F2OP_FSQRTD = 0x01,
+  N32_FPU_FD1_F2OP_FABSD = 0x05,
+  N32_FPU_FD1_F2OP_FUI2D = 0x08,
+  N32_FPU_FD1_F2OP_FSI2D = 0x0c,
+  N32_FPU_FD1_F2OP_FD2UI = 0x10,
+  N32_FPU_FD1_F2OP_FD2UI_Z = 0x14,
+  N32_FPU_FD1_F2OP_FD2SI = 0x18,
+  N32_FPU_FD1_F2OP_FD2SI_Z = 0x1c,
+
+  /* FD2 b[9:6] */
+  N32_FPU_FD2_FCMPEQD = 0x0,
+  N32_FPU_FD2_FCMPLTD = 0x2,
+  N32_FPU_FD2_FCMPLED = 0x4,
+  N32_FPU_FD2_FCMPUND = 0x6,
+  N32_FPU_FD2_FCMPEQD_E = 0x1,
+  N32_FPU_FD2_FCMPLTD_E = 0x3,
+  N32_FPU_FD2_FCMPLED_E = 0x5,
+  N32_FPU_FD2_FCMPUND_E = 0x7,
+
+  /* MFCP b[9:6] */
+  N32_FPU_MFCP_FMFSR = 0x0,
+  N32_FPU_MFCP_FMFDR = 0x1,
+  N32_FPU_MFCP_XR = 0xc,
+
+  /* MFCP/XR b[14:10] */
+  N32_FPU_MFCP_XR_FMFCFG = 0x0,
+  N32_FPU_MFCP_XR_FMFCSR = 0x1,
+
+  /* MTCP b[9:6] */
+  N32_FPU_MTCP_FMTSR = 0x0,
+  N32_FPU_MTCP_FMTDR = 0x1,
+  N32_FPU_MTCP_XR = 0xc,
+
+  /* MTCP/XR b[14:10] */
+  N32_FPU_MTCP_XR_FMTCSR = 0x1
+};
+
+enum n16_opcodes
+{
+  N16_T55_MOV55 = 0x0,
+  N16_T55_MOVI55 = 0x1,
+
+  N16_T45_0 = 0,
+  N16_T45_ADD45 = 0x4,
+  N16_T45_SUB45 = 0x5,
+  N16_T45_ADDI45 = 0x6,
+  N16_T45_SUBI45 = 0x7,
+  N16_T45_SRAI45 = 0x8,
+  N16_T45_SRLI45 = 0x9,
+  N16_T45_LWI45_FE = 0x19,
+  N16_T45_LWI450 = 0x1a,
+  N16_T45_SWI450 = 0x1b,
+  N16_T45_SLTS45 = 0x30,
+  N16_T45_SLT45 = 0x31,
+  N16_T45_SLTSI45 = 0x32,
+  N16_T45_SLTI45 = 0x33,
+  N16_T45_MOVPI45 = 0x3d,
+
+  N15_T44_MOVD44 = 0x7d,
+
+  N16_T333_0 = 0,
+  N16_T333_SLLI333 = 0xa,
+  N16_T333_BFMI333 = 0xb,
+  N16_T333_ADD333 = 0xc,
+  N16_T333_SUB333 = 0xd,
+  N16_T333_ADDI333 = 0xe,
+  N16_T333_SUBI333 = 0xf,
+  N16_T333_LWI333 = 0x10,
+  N16_T333_LWI333_BI = 0x11,
+  N16_T333_LHI333 = 0x12,
+  N16_T333_LBI333 = 0x13,
+  N16_T333_SWI333 = 0x14,
+  N16_T333_SWI333_BI = 0x15,
+  N16_T333_SHI333 = 0x16,
+  N16_T333_SBI333 = 0x17,
+  N16_T333_MISC33 = 0x3f,
+
+  N16_T36_ADDRI36_SP = 0x18,
+
+  N16_T37_XWI37 = 0x7,
+  N16_T37_XWI37SP = 0xe,
+
+  N16_T38_BEQZ38 = 0x8,
+  N16_T38_BNEZ38 = 0x9,
+  N16_T38_BEQS38 = 0xa,
+  N16_T38_BNES38 = 0xb,
+
+  N16_T5_JR5 = 0x2e8,
+  N16_T5_JRAL5 = 0x2e9,
+  N16_T5_EX9IT = 0x2ea,
+  /* 0x2eb reserved.  */
+  N16_T5_RET5 = 0x2ec,
+  N16_T5_ADD5PC = 0x2ed,
+  /* 0x2e[ef] reserved.  */
+  N16_T5_BREAK16 = 0x350,
+
+  N16_T8_J8 = 0x55,
+  N16_T8_BEQZS8 = 0x68,
+  N16_T8_BNEZS8 = 0x69,
+
+  /* N16_T9_BREAK16 = 0x35
+     Since v3, SWID of BREAK16 above 32 are used for encoding EX9.IT.  */
+  N16_T9_EX9IT = 0x35,
+  N16_T9_IFCALL9 = 0x3c,
+
+  N16_T10_ADDI10S = 0x1b,
+
+  N16_T25_PUSH25 = 0xf8,
+  N16_T25_POP25 = 0xf9,
+
+  /* Sub-opcodes.  */
+  N16_MISC33_0 = 0,
+  N16_MISC33_1 = 1,
+  N16_MISC33_NEG33 = 2,
+  N16_MISC33_NOT33 = 3,
+  N16_MISC33_MUL33 = 4,
+  N16_MISC33_XOR33 = 5,
+  N16_MISC33_AND33 = 6,
+  N16_MISC33_OR33 = 7,
+
+  N16_BFMI333_ZEB33 = 0,
+  N16_BFMI333_ZEH33 = 1,
+  N16_BFMI333_SEB33 = 2,
+  N16_BFMI333_SEH33 = 3,
+  N16_BFMI333_XLSB33 = 4,
+  N16_BFMI333_X11B33 = 5,
+  N16_BFMI333_BMSKI33 = 6,
+  N16_BFMI333_FEXTI33 = 7
+};
+
+/* These macros a deprecated.  DO NOT use them anymore.
+   And please help rewrite code used them.  */
+
+/* 32-bit instructions without operands.  */
+#define INSN_SETHI  0x46000000
+#define INSN_ORI    0x58000000
+#define INSN_JR     0x4a000000
+#define INSN_RET    0x4a000020
+#define INSN_JAL    0x49000000
+#define INSN_J      0x48000000
+#define INSN_JRAL   0x4a000001
+#define INSN_BGEZAL 0x4e0c0000
+#define INSN_BLTZAL 0x4e0d0000
+#define INSN_BEQ    0x4c000000
+#define INSN_BNE    0x4c004000
+#define INSN_BEQZ   0x4e020000
+#define INSN_BNEZ   0x4e030000
+#define INSN_BGEZ   0x4e040000
+#define INSN_BLTZ   0x4e050000
+#define INSN_BGTZ   0x4e060000
+#define INSN_BLEZ   0x4e070000
+#define INSN_MOVI   0x44000000
+#define INSN_ADDI   0x50000000
+#define INSN_ANDI   0x54000000
+#define INSN_LDI    0x06000000
+#define INSN_SDI    0x16000000
+#define INSN_LWI    0x04000000
+#define INSN_LWSI   0x24000000
+#define INSN_LWIP   0x0c000000
+#define INSN_LHI    0x02000000
+#define INSN_LHSI   0x22000000
+#define INSN_LBI    0x00000000
+#define INSN_LBSI   0x20000000
+#define INSN_SWI    0x14000000
+#define INSN_SWIP   0x1c000000
+#define INSN_SHI    0x12000000
+#define INSN_SBI    0x10000000
+#define INSN_SLTI   0x5c000000
+#define INSN_SLTSI  0x5e000000
+#define INSN_ADD    0x40000000
+#define INSN_SUB    0x40000001
+#define INSN_SLT    0x40000006
+#define INSN_SLTS   0x40000007
+#define INSN_SLLI   0x40000008
+#define INSN_SRLI   0x40000009
+#define INSN_SRAI   0x4000000a
+#define INSN_SEB    0x40000010
+#define INSN_SEH    0x40000011
+#define INSN_ZEB    INSN_ANDI + 0xFF
+#define INSN_ZEH    0x40000013
+#define INSN_BREAK  0x6400000a
+#define INSN_NOP    0x40000009
+#define INSN_FLSI   0x30000000
+#define INSN_FSSI   0x32000000
+#define INSN_FLDI   0x34000000
+#define INSN_FSDI   0x36000000
+#define INSN_BEQC   0x5a000000
+#define INSN_BNEC   0x5a080000
+#define INSN_DSB    0x64000008
+#define INSN_IFCALL 0x4e000000
+#define INSN_IFRET  0x4a000060
+#define INSN_BR1    0x4c000000
+#define INSN_BR2    0x4e000000
+
+/* 16-bit instructions without operand.  */
+#define INSN_MOV55	0x8000
+#define INSN_MOVI55	0x8400
+#define INSN_ADD45	0x8800
+#define INSN_SUB45	0x8a00
+#define INSN_ADDI45	0x8c00
+#define INSN_SUBI45	0x8e00
+#define INSN_SRAI45	0x9000
+#define INSN_SRLI45	0x9200
+#define INSN_SLLI333	0x9400
+#define INSN_BFMI333	0x9600
+#define INSN_ADD333	0x9800
+#define INSN_SUB333	0x9a00
+#define INSN_ADDI333	0x9c00
+#define INSN_SUBI333	0x9e00
+#define INSN_LWI333	0xa000
+#define INSN_LWI333P	0xa200
+#define INSN_LHI333	0xa400
+#define INSN_LBI333	0xa600
+#define INSN_SWI333	0xa800
+#define INSN_SWI333P	0xaa00
+#define INSN_SHI333	0xac00
+#define INSN_SBI333	0xae00
+#define INSN_RSV01	0xb000
+#define INSN_RSV02	0xb200
+#define INSN_LWI450	0xb400
+#define INSN_SWI450	0xb600
+#define INSN_LWI37	0xb800
+#define INSN_SWI37	0xb880
+#define INSN_BEQZ38	0xc000
+#define INSN_BNEZ38	0xc800
+#define INSN_BEQS38	0xd000
+#define INSN_J8		0xd500
+#define INSN_BNES38	0xd800
+#define INSN_JR5	0xdd00
+#define INSN_RET5	0xdd80
+#define INSN_JRAL5	0xdd20
+#define INSN_EX9_IT_2	0xdd40
+#define INSN_SLTS45	0xe000
+#define INSN_SLT45	0xe200
+#define INSN_SLTSI45	0xe400
+#define INSN_SLTI45	0xe600
+#define INSN_BEQZS8	0xe800
+#define INSN_BNEZS8	0xe900
+#define INSN_BREAK16	0xea00
+#define INSN_EX9_IT_1	0xea00
+#define INSN_NOP16	0x9200
+/* 16-bit version 2.  */
+#define INSN_ADDI10_SP	0xec00
+#define INSN_LWI37SP	0xf000
+#define INSN_SWI37SP	0xf080
+/* 16-bit version 3.  */
+#define INSN_IFRET16	0x83ff
+#define INSN_ADDRI36_SP	0xb000
+#define INSN_LWI45_FE	0xb200
+#define INSN_IFCALL9	0xf800
+#define INSN_MISC33	0xfe00
+
+/* Instruction with specific operands.  */
+#define INSN_ADDI_GP_TO_FP	0x51cd8000	/* BASELINE_V1.  */
+#define INSN_ADDIGP_TO_FP	0x3fc80000	/* BASELINE_V2.  */
+#define INSN_MOVI_TO_FP		0x45c00000
+#define INSN_MFUSR_PC		0x420F8020
+#define INSN_MFUSR_PC_MASK	0xFE0FFFFF
+
+/* Instructions use $ta register as operand.  */
+#define INSN_SETHI_TA	(INSN_SETHI | (REG_TA << 20))
+#define INSN_ORI_TA	(INSN_ORI | (REG_TA << 20) | (REG_TA << 15))
+#define INSN_ADD_TA	(INSN_ADD | (REG_TA << 20))
+#define INSN_ADD45_TA	(INSN_ADD45 | (REG_TA << 5))
+#define INSN_JR5_TA	(INSN_JR5 | (REG_TA << 0))
+#define INSN_RET5_TA	(INSN_RET5 | (REG_TA << 0))
+#define INSN_JR_TA	(INSN_JR | (REG_TA << 10))
+#define INSN_RET_TA	(INSN_RET | (REG_TA << 10))
+#define INSN_JRAL_TA	(INSN_JRAL | (REG_LP << 20) | (REG_TA << 10))
+#define INSN_JRAL5_TA	(INSN_JRAL5 | (REG_TA << 0))
+#define INSN_BEQZ_TA	(INSN_BEQZ | (REG_TA << 20))
+#define INSN_BNEZ_TA	(INSN_BNEZ | (REG_TA << 20))
+#define INSN_MOVI_TA	(INSN_MOVI | (REG_TA << 20))
+#define INSN_BEQ_TA	(INSN_BEQ | (REG_TA << 15))
+#define INSN_BNE_TA	(INSN_BNE | (REG_TA << 15))
+
+/* Instructions use $r5 register as operand.  */
+#define INSN_BNE_R5	(INSN_BNE | (REG_R5 << 15))
+#define INSN_BEQ_R5	(INSN_BEQ | (REG_R5 << 15))
+
+#endif

ld/ChangeLog

@@ -1,3 +1,23 @@
+2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
+            Wei-Cheng Wang  <cole945@gmail.com>
+	    Hui-Wen Ni  <sabrinanitw@gmail.com>
+
+	* Makefile.am (ALL_EMULATION_SOURCES): Add nds32 target.
+	* Makefile.in: Regenerate.
+	* configure.tgt: Add case for nds32*le-*-elf*, nds32*be-*-elf*,
+	nds32*le-*-linux-gnu*, and nds32*be-*-linux-gnu*.
+	* emulparams/nds32belf.sh: New file for nds32.
+	* emulparams/nds32belf_linux.sh: Likewise.
+	* emulparams/nds32belf16m.sh: Likewise.
+	* emulparams/nds32elf.sh: Likewise.
+	* emulparams/nds32elf_linux.sh: Likewise.
+	* emulparams/nds32elf16m.sh: Likewise.
+	* emultempl/nds32elf.em: Likewise.
+	* scripttempl/nds32elf.sc}: Likewise.
+	* gen-doc.texi: Set NDS32.
+	* ld.texinfo: Set NDS32.
+	* NEWS: Announce Andes nds32 support.
+
 2013-12-11  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* ld.texinfo: Remove shared object from -Ttext-segment.

ld/Makefile.am

@@ -397,6 +397,12 @@ ALL_EMULATION_SOURCES = \
 	emsp430xW425.c \
 	emsp430xW427.c \
 	emsp430X.c \
+	ends32elf.c \
+	ends32elf16m.c \
+	ends32elf_linux.c \
+	ends32belf.c \
+	ends32belf16m.c \
+	ends32belf_linux.c \
 	enews.c \
 	ens32knbsd.c \
 	eor32.c \
@@ -1753,6 +1759,30 @@ emsp430X.c: $(srcdir)/emulparams/msp430all.sh \
   $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \
   ${GEN_DEPENDS}
 	${GENSCRIPTS} msp430X "$(tdir_msp430X)" msp430all
+ends32elf.c: $(srcdir)/emulparams/nds32elf.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \
+  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+	${GENSCRIPTS} nds32elf "$(tdir_nds32)"
+ends32elf16m.c: $(srcdir)/emulparams/nds32elf16m.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \
+  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+	${GENSCRIPTS} nds32elf16m "$(tdir_nds32)"
+ends32belf.c: $(srcdir)/emulparams/nds32belf.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \
+  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+	${GENSCRIPTS} nds32belf "$(tdir_nds32belf)"
+ends32belf16m.c: $(srcdir)/emulparams/nds32belf16m.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \
+  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+	${GENSCRIPTS} nds32belf16m "$(tdir_nds32belf)"
+ends32elf_linux.c: $(srcdir)/emulparams/nds32elf_linux.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \
+  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+	${GENSCRIPTS} nds32elf_linux "$(tdir_nds32elf_linux)"
+ends32belf_linux.c: $(srcdir)/emulparams/nds32belf_linux.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \
+  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+	${GENSCRIPTS} nds32belf_linux "$(tdir_nds32belf_linux)"
 enews.c: $(srcdir)/emulparams/news.sh \
   $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}
 	${GENSCRIPTS} news "$(tdir_news)"

ld/Makefile.in

@@ -705,6 +705,12 @@ ALL_EMULATION_SOURCES = \
 	emsp430xW425.c \
 	emsp430xW427.c \
 	emsp430X.c \
+	ends32elf.c \
+	ends32elf16m.c \
+	ends32elf_linux.c \
+	ends32belf.c \
+	ends32belf16m.c \
+	ends32belf_linux.c \
 	enews.c \
 	ens32knbsd.c \
 	eor32.c \
@@ -1399,6 +1405,12 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xW423.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xW425.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xW427.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ends32belf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ends32belf16m.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ends32belf_linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ends32elf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ends32elf16m.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ends32elf_linux.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/enews.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ens32knbsd.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eor32.Po@am__quote@
@@ -3237,6 +3249,30 @@ emsp430X.c: $(srcdir)/emulparams/msp430all.sh \
   $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \
   ${GEN_DEPENDS}
 	${GENSCRIPTS} msp430X "$(tdir_msp430X)" msp430all
+ends32elf.c: $(srcdir)/emulparams/nds32elf.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \
+  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+	${GENSCRIPTS} nds32elf "$(tdir_nds32)"
+ends32elf16m.c: $(srcdir)/emulparams/nds32elf16m.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \
+  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+	${GENSCRIPTS} nds32elf16m "$(tdir_nds32)"
+ends32belf.c: $(srcdir)/emulparams/nds32belf.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \
+  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+	${GENSCRIPTS} nds32belf "$(tdir_nds32belf)"
+ends32belf16m.c: $(srcdir)/emulparams/nds32belf16m.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \
+  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+	${GENSCRIPTS} nds32belf16m "$(tdir_nds32belf)"
+ends32elf_linux.c: $(srcdir)/emulparams/nds32elf_linux.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \
+  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+	${GENSCRIPTS} nds32elf_linux "$(tdir_nds32elf_linux)"
+ends32belf_linux.c: $(srcdir)/emulparams/nds32belf_linux.sh \
+  $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \
+  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+	${GENSCRIPTS} nds32belf_linux "$(tdir_nds32belf_linux)"
 enews.c: $(srcdir)/emulparams/news.sh \
   $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}
 	${GENSCRIPTS} news "$(tdir_news)"

ld/NEWS

@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Add support for the Andes NDS32.
+
 Changes in 2.24:
 
 * Add LOG2CEIL() builtin function to the linker script language

ld/configure.tgt

@@ -6,12 +6,12 @@
 # it under the terms of the GNU General Public License as published by
 # the Free Software Foundation; either version 3 of the License, or
 # (at your option) any later version.
-# 
+#
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
-# 
+#
 # You should have received a copy of the GNU General Public License
 # along with this program; see the file COPYING3.  If not see
 # <http://www.gnu.org/licenses/>.
@@ -514,6 +514,14 @@ mt-*elf)                targ_emul=elf32mt
 msp430-*-*)             targ_emul=msp430x110
                         targ_extra_emuls="msp430x112 msp430x1101 msp430x1111 msp430x1121 msp430x1122 msp430x1132 msp430x122 msp430x123 msp430x1222 msp430x1232 msp430x133 msp430x135 msp430x1331 msp430x1351 msp430x147 msp430x148 msp430x149 msp430x155 msp430x156 msp430x157 msp430x167 msp430x168 msp430x169 msp430x1610 msp430x1611 msp430x1612 msp430x2101 msp430x2111 msp430x2121 msp430x2131 msp430x311 msp430x312 msp430x313 msp430x314 msp430x315 msp430x323 msp430x325 msp430x336 msp430x337 msp430x412 msp430x413 msp430x415 msp430x417 msp430xE423 msp430xE425 msp430xE427 msp430xW423 msp430xW425 msp430xW427 msp430xG437 msp430xG438 msp430xG439 msp430x435 msp430x436 msp430x437 msp430x447 msp430x448 msp430x449 msp430X"
 			;;
+nds32*le-*-elf*)	targ_emul=nds32elf
+			targ_extra_emuls="nds32elf16m nds32belf nds32belf16m"
+			;;
+nds32*be-*-elf*)	targ_emul=nds32belf
+			targ_extra_emuls="nds32elf nds32elf16m nds32belf16m"
+			;;
+nds32*le-*-linux-gnu*)	targ_emul=nds32elf_linux ;;
+nds32*be-*-linux-gnu*)	targ_emul=nds32belf_linux ;;
 nios2*-*-linux*)	targ_emul=nios2linux ;;
 nios2*-*-*)		targ_emul=nios2elf ;;
 ns32k-pc532-mach* | ns32k-pc532-ux*)  targ_emul=pc532macha ;;
@@ -752,7 +760,7 @@ xstormy16-*-*)		targ_emul=elf32xstormy16
 			;;
 xtensa*-*-*)		targ_emul=elf32xtensa
 			;;
-xgate-*-*)  	targ_emul=xgateelf 
+xgate-*-*)  	targ_emul=xgateelf
 			;;
 z80-*-coff)		targ_emul=z80
 			;;

ld/emulparams/nds32belf.sh

@@ -0,0 +1,2 @@
+. ${srcdir}/emulparams/nds32elf.sh
+OUTPUT_FORMAT="$BIG_OUTPUT_FORMAT"

ld/emulparams/nds32belf16m.sh

@@ -0,0 +1,2 @@
+. ${srcdir}/emulparams/nds32elf16m.sh
+OUTPUT_FORMAT="$BIG_OUTPUT_FORMAT"

ld/emulparams/nds32belf_linux.sh

@@ -0,0 +1,2 @@
+. ${srcdir}/emulparams/nds32elf_linux.sh
+OUTPUT_FORMAT="$BIG_OUTPUT_FORMAT"

ld/emulparams/nds32elf.sh

@@ -0,0 +1,19 @@
+TEXT_START_ADDR=0x500000
+# This sets the stack to the top of simulator memory (48MB).
+OTHER_END_SYMBOLS='PROVIDE (_stack = 0x3000000);'
+
+SCRIPT_NAME=nds32elf
+TEMPLATE_NAME=elf32
+EXTRA_EM_FILE=nds32elf
+BIG_OUTPUT_FORMAT="elf32-nds32be"
+LITTLE_OUTPUT_FORMAT="elf32-nds32le"
+OUTPUT_FORMAT="$LITTLE_OUTPUT_FORMAT"
+ARCH=nds32
+MACHINE=
+MAXPAGESIZE=0x20
+EMBEDDED=yes
+COMMONPAGESIZE=0x20
+
+# Instruct genscripts.sh not to compile scripts in by COMPILE_IN
+# in order to use external linker scripts files.
+EMULATION_LIBPATH=

ld/emulparams/nds32elf16m.sh

@@ -0,0 +1,19 @@
+TEXT_START_ADDR=0x300000
+# This sets the stack to the top of simulator memory (48MB).
+OTHER_END_SYMBOLS='PROVIDE (_stack = 0x780000);'
+
+SCRIPT_NAME=nds32elf
+TEMPLATE_NAME=elf32
+EXTRA_EM_FILE=nds32elf
+BIG_OUTPUT_FORMAT="elf32-nds32be"
+LITTLE_OUTPUT_FORMAT="elf32-nds32le"
+OUTPUT_FORMAT="$LITTLE_OUTPUT_FORMAT"
+ARCH=nds32
+MACHINE=
+MAXPAGESIZE=0x20
+EMBEDDED=yes
+COMMONPAGESIZE=0x20
+
+# Instruct genscripts.sh not to compile scripts in by COMPILE_IN
+# in order to use external linker scripts files.
+EMULATION_LIBPATH=

ld/emulparams/nds32elf_linux.sh

@@ -0,0 +1,36 @@
+DEFAULT_TEXT_START_ADDR=0
+DEFAULT_STACK_START_ADDR=0
+MACHINE=
+SCRIPT_NAME=nds32elf
+TEMPLATE_NAME=elf32
+EXTRA_EM_FILE=nds32elf
+BIG_OUTPUT_FORMAT="elf32-nds32be-linux"
+LITTLE_OUTPUT_FORMAT="elf32-nds32le-linux"
+OUTPUT_FORMAT="$LITTLE_OUTPUT_FORMAT"
+LIB_PATH="=/usr/local/lib:=/lib:=/usr/lib/"
+
+if [ "${DEFAULT_TEXT_START_ADDR}" = "0" ]; then
+    TEXT_START_ADDR=0x8000
+else
+    TEXT_START_ADDR=${DEFAULT_TEXT_START_ADDR}
+fi
+
+ARCH=nds32
+MACHINE=
+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
+COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)"
+
+# Hmmm, there's got to be a better way.  This sets the stack to the
+# top of simulator memory (32MB).
+if [ "${DEFAULT_STACK_START_ADDR}" = "0" ]; then
+    OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = 0x2000000);'
+else
+    OTHER_RELOCATING_SECTIONS="PROVIDE (_stack = ${DEFAULT_STACK_START_ADDR});"
+fi
+
+GENERATE_SHLIB_SCRIPT=yes
+GENERATE_PIE_SCRIPT=yes
+
+# Instruct genscripts.sh not to compile scripts in by COMPILE_IN
+# in order to use external linker scripts files.
+EMULATION_LIBPATH=

ld/emultempl/nds32elf.em

@@ -0,0 +1,475 @@
+# This shell script emits a C file. -*- C -*-
+# Copyright (C) 2012-2013 Free Software Foundation, Inc.
+# Contributed by Andes Technology Corporation.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+fragment <<EOF
+
+#include "libbfd.h"
+#include "elf-bfd.h"
+#include "elf/nds32.h"
+#include "elf32-nds32.h"
+
+static int relax_fp_as_gp = 1;		/* --mrelax-omit-fp  */
+static int eliminate_gc_relocs = 0;	/* --meliminate-gc-relocs  */
+static FILE *sym_ld_script = NULL;	/* --mgen-symbol-ld-script=<file>  */
+/* Disable if linking a dynamically linked executable.  */
+static int load_store_relax = 1;
+static int target_optimize = 0;	/* Switch optimization.  */
+static int relax_status = 0;	/* Finished optimization.  */
+static int relax_round = 0;		/* Going optimization.  */
+static FILE *ex9_export_file = NULL;	/* --mexport-ex9=<file>  */
+static FILE *ex9_import_file = NULL;	/* --mimport-ex9=<file>  */
+static int update_ex9_table = 0;	/* --mupdate-ex9.  */
+static int ex9_limit = 511;
+static bfd_boolean ex9_loop_aware = FALSE;	/* Ignore ex9 if inside a loop.  */
+static bfd_boolean ifc_loop_aware = FALSE;	/* Ignore ifc if inside a loop.  */
+
+/* Save the target options into output bfd to avoid using to many global
+   variables. Do this after the output has been created, but before
+   inputs are read.  */
+static void
+nds32_elf_create_output_section_statements (void)
+{
+  if (strstr (bfd_get_target (link_info.output_bfd), "nds32") == NULL)
+    {
+      /* Check the output target is nds32.  */
+      einfo ("%F%X%P: error: Cannot change output format whilst linking NDS32 binaries.\n");
+      return;
+    }
+
+  bfd_elf32_nds32_set_target_option (&link_info, relax_fp_as_gp,
+				     eliminate_gc_relocs,
+				     sym_ld_script,
+				     load_store_relax,
+				     target_optimize, relax_status, relax_round,
+				     ex9_export_file, ex9_import_file,
+				     update_ex9_table, ex9_limit,
+				     ex9_loop_aware, ifc_loop_aware);
+}
+
+static void
+nds32_elf_after_parse (void)
+{
+  if (link_info.relocatable)
+    DISABLE_RELAXATION;
+
+  if (!RELAXATION_ENABLED)
+    {
+      target_optimize = target_optimize & (!NDS32_RELAX_JUMP_IFC_ON);
+      target_optimize = target_optimize & (!NDS32_RELAX_EX9_ON);
+      relax_fp_as_gp = 0;
+    }
+
+  if (ex9_import_file != NULL)
+    {
+      ex9_export_file = NULL;
+      target_optimize = target_optimize & (!NDS32_RELAX_EX9_ON);
+    }
+  else
+    update_ex9_table = 0;
+
+  if (link_info.shared)
+    {
+      target_optimize = target_optimize & (!NDS32_RELAX_JUMP_IFC_ON);
+      target_optimize = target_optimize & (!NDS32_RELAX_EX9_ON);
+    }
+
+  after_parse_default ();
+}
+
+static void
+nds32_elf_after_open (void)
+{
+  unsigned int arch_ver = (unsigned int)-1;
+  unsigned int abi_ver = (unsigned int)-1;
+  bfd *abfd;
+
+  /* For now, make sure all object files are of the same architecture.
+     We may try to merge object files with different architecture together.  */
+  for (abfd = link_info.input_bfds; abfd != NULL; abfd = abfd->link_next)
+    {
+      if (arch_ver == (unsigned int)-1 && E_N1_ARCH != (elf_elfheader (abfd)->e_flags & EF_NDS_ARCH))
+	arch_ver = elf_elfheader (abfd)->e_flags & EF_NDS_ARCH ;
+
+      if (abi_ver == (unsigned int)-1)
+	{
+	  /* Initialize ABI version, if not ABI0.
+	     (OS uses empty file to create empty ELF with ABI0).  */
+	  if ((elf_elfheader (abfd)->e_flags & EF_NDS_ABI) != 0)
+	    abi_ver = elf_elfheader (abfd)->e_flags & EF_NDS_ABI ;
+	}
+      else if ((elf_elfheader (abfd)->e_flags & EF_NDS_ABI) != 0
+	       && abi_ver != (elf_elfheader (abfd)->e_flags & EF_NDS_ABI))
+	{
+	  /* Incompatible objects.  */
+	  einfo (_("%F%B: ABI version of object files mismatched\n"), abfd);
+	}
+
+      /* Append .ex9.itable section in the last input object file.  */
+      if (!link_info.relocatable && abfd->link_next == NULL)
+	{
+	  asection *itable;
+	  struct bfd_link_hash_entry *h;
+	  itable = bfd_make_section_with_flags (abfd, ".ex9.itable",
+						SEC_CODE | SEC_ALLOC | SEC_LOAD
+						| SEC_HAS_CONTENTS | SEC_READONLY
+						| SEC_IN_MEMORY | SEC_KEEP);
+	  if (itable)
+	    {
+	      itable->gc_mark = 1;
+	      itable->alignment_power = 2;
+	      if ((target_optimize & NDS32_RELAX_EX9_ON))
+		{
+		  itable->size = 0x1000;
+		  itable->contents = bfd_zalloc (abfd, itable->size);
+		}
+	      else
+		{
+		  itable->size = 0x4;
+		  itable->contents = bfd_zalloc (abfd, itable->size);
+		  bfd_putb32 (INSN_BREAK_EA,itable->contents);
+		}
+
+	      /* Add a symbol in the head of ex9.itable to objdump clearly.  */
+	      h = bfd_link_hash_lookup (link_info.hash, "_EX9_BASE_",
+					FALSE, FALSE, FALSE);
+	      _bfd_generic_link_add_one_symbol
+		(&link_info, link_info.output_bfd, "_EX9_BASE_",
+		 BSF_GLOBAL | BSF_WEAK, itable, 0, (const char *) NULL, FALSE,
+		 get_elf_backend_data (link_info.output_bfd)->collect, &h);
+	    }
+	}
+    }
+
+  /* Check object files if the target is dynamic linked executable
+     or shared object.  */
+  if (elf_hash_table (&link_info)->dynamic_sections_created
+      || link_info.shared || link_info.pie)
+    {
+      for (abfd = link_info.input_bfds; abfd != NULL; abfd = abfd->link_next)
+	{
+	  if (!(elf_elfheader (abfd)->e_flags & E_NDS32_HAS_PIC))
+	    {
+	      /* Non-PIC object file is used.  */
+	      if (link_info.shared || link_info.pie)
+		{
+		  /* For PIE or shared object, all input must be PIC.  */
+		  einfo (_("%B: must use -fpic to compile this file for shared object or PIE\n"), abfd);
+		}
+	      else
+		{
+		  /* Dynamic linked executable with SDA and non-PIC.
+		     Turn off load/store relaxtion.  */
+		  load_store_relax = 0 ;
+		  relax_fp_as_gp = 0;
+		}
+	    }
+	}
+      /* Turn off relax when building shared object or PIE
+	 until we can support their relaxation.  */
+    }
+
+  /* Call the standard elf routine.  */
+  gld${EMULATION_NAME}_after_open ();
+}
+
+static void nds32_elf_relax_stub (bfd_boolean relax)
+{
+  /* Re-caculate memory map address.  */
+  lang_do_assignments (lang_assigning_phase_enum);
+  lang_reset_memory_regions ();
+  one_lang_size_sections_pass (&relax, FALSE);
+}
+
+static void
+nds32_elf_after_allocation (void)
+{
+  struct elf_nds32_link_hash_table *table;
+  table = nds32_elf_hash_table (&link_info);
+
+  /* Call default after allocation callback.
+     1. This is where relaxation is done.
+     2. It calls gld${EMULATION_NAME}_map_segments to build ELF segment table.
+     3. Any relaxation requires relax being done must be called after it.  */
+  gld${EMULATION_NAME}_after_allocation ();
+
+  if (!table)
+    return;
+
+  /* Use IFC */
+  if ((target_optimize & NDS32_RELAX_JUMP_IFC_ON)
+      && !(table->relax_status & NDS32_RELAX_JUMP_IFC_DONE))
+    {
+      table->relax_round = NDS32_RELAX_JUMP_IFC_ROUND;
+      /* Traverse all sections to build j and jal list.  */
+      nds32_elf_relax_stub (TRUE);
+
+      /* Replace with ifc.  */
+      if (!nds32_elf_ifc_finish (&link_info))
+	einfo (_("%F: Please report this bug. IFC error.\n"));
+      table->relax_round = NDS32_RELAX_NONE_ROUND;
+
+      /* Adjust address after ifcall.  */
+      nds32_elf_relax_stub (FALSE);
+
+      if (!nds32_elf_ifc_reloc ())
+	einfo (_("%F: Please report this bug. IFC error.\n"));
+    }
+
+  /* EX9 Instruction Table Relaxation.  */
+  if (!link_info.relocatable && !nds32_elf_ex9_itb_base (&link_info))
+    einfo (_("%F: Please report this bug. Ex9 relocation error.\n"));
+
+
+  /* Generate ex9 table.  */
+  if ((target_optimize & NDS32_RELAX_EX9_ON)
+      && !(table->relax_status & NDS32_RELAX_EX9_DONE))
+    {
+      /* Ex9 entry point.  */
+      table->relax_round = NDS32_RELAX_EX9_BUILD_ROUND;
+
+      /* Initialize ex9 hash table.  */
+      if (!nds32_elf_ex9_init ())
+	return;
+
+      /* Build ex9 instruction table.  */
+      nds32_elf_relax_stub (TRUE);
+      nds32_elf_ex9_finish (&link_info);
+      /* Replace with ex9.it.  */
+      nds32_elf_relax_stub (TRUE);
+      table->relax_round = NDS32_RELAX_NONE_ROUND;
+
+      /* Do ifc again.  */
+      if (target_optimize & NDS32_RELAX_JUMP_IFC_ON)
+	if (!nds32_elf_ifc_finish (&link_info))
+	  einfo (_("%F: Please report this bug. IFC error.\n"));
+
+      /* Re-caculate memory map address.  */
+      lang_do_assignments (lang_assigning_phase_enum);
+      /* Relocation for .ex9.itable.  */
+      nds32_elf_ex9_reloc_jmp (&link_info);
+    }
+  else if (ex9_import_file != NULL
+      && !(table->relax_status = NDS32_RELAX_EX9_DONE))
+    {
+      /* Import ex9 table.  */
+
+      if (update_ex9_table == 1)
+	{
+	  /* Build ex9 table.  */
+	  table->relax_round = NDS32_RELAX_EX9_BUILD_ROUND;
+	  /* Initialize ex9 hash table.  */
+	  if (!nds32_elf_ex9_init ())
+	    return;
+	  /* Build ex9 table.  */
+	  nds32_elf_relax_stub (TRUE);
+
+	  /* Relocation for .ex9.itable.  */
+	  lang_do_assignments (lang_assigning_phase_enum);
+	  nds32_elf_ex9_reloc_jmp (&link_info);
+	}
+      nds32_elf_ex9_import_table (&link_info);
+
+      /* Replace with ex9.it.  */
+      table->relax_round = NDS32_RELAX_EX9_REPLACE_ROUND;
+      table->relax_status |= NDS32_RELAX_EX9_DONE;
+      nds32_elf_relax_stub (TRUE);
+    }
+}
+
+EOF
+# Define some shell vars to insert bits of code into the standard elf
+# parse_args and list_options functions.
+#
+PARSE_AND_LIST_PROLOGUE='
+#define OPTION_BASELINE			301
+#define OPTION_ELIM_GC_RELOCS		(OPTION_BASELINE + 1)
+#define OPTION_FP_AS_GP			(OPTION_BASELINE + 2)
+#define OPTION_NO_FP_AS_GP		(OPTION_BASELINE + 3)
+#define OPTION_REDUCE_FP_UPDATE		(OPTION_BASELINE + 4)
+#define OPTION_NO_REDUCE_FP_UPDATE	(OPTION_BASELINE + 5)
+#define OPTION_EXPORT_SYMBOLS		(OPTION_BASELINE + 6)
+
+/* These are only available to ex9.  */
+#if defined NDS32_EX9_EXT
+#define OPTION_EX9_BASELINE		320
+#define OPTION_EX9_TABLE		(OPTION_EX9_BASELINE + 1)
+#define OPTION_NO_EX9_TABLE		(OPTION_EX9_BASELINE + 2)
+#define OPTION_EXPORT_EX9		(OPTION_EX9_BASELINE + 3)
+#define OPTION_IMPORT_EX9		(OPTION_EX9_BASELINE + 4)
+#define OPTION_UPDATE_EX9		(OPTION_EX9_BASELINE + 5)
+#define OPTION_EX9_LIMIT		(OPTION_EX9_BASELINE + 6)
+#define OPTION_EX9_LOOP			(OPTION_EX9_BASELINE + 7)
+#endif
+
+/* These are only available to link-time ifc.  */
+#if defined NDS32_IFC_EXT
+#define OPTION_IFC_BASELINE		340
+#define OPTION_JUMP_IFC			(OPTION_IFC_BASELINE + 1)
+#define OPTION_NO_JUMP_IFC		(OPTION_IFC_BASELINE + 2)
+#define OPTION_IFC_LOOP			(OPTION_IFC_BASELINE + 3)
+#endif
+'
+PARSE_AND_LIST_LONGOPTS='
+  { "mfp-as-gp", no_argument, NULL, OPTION_FP_AS_GP},
+  { "mno-fp-as-gp", no_argument, NULL, OPTION_NO_FP_AS_GP},
+  { "mgen-symbol-ld-script", required_argument, NULL, OPTION_EXPORT_SYMBOLS},
+  /* These are deprecated options.  Remove them in the future.  */
+  { "mrelax-reduce-fp-update", no_argument, NULL, OPTION_REDUCE_FP_UPDATE},
+  { "mrelax-no-reduce-fp-update", no_argument, NULL, OPTION_NO_REDUCE_FP_UPDATE},
+  { "mbaseline", required_argument, NULL, OPTION_BASELINE},
+  { "meliminate-gc-relocs", no_argument, NULL, OPTION_ELIM_GC_RELOCS},
+  { "mrelax-omit-fp", no_argument, NULL, OPTION_FP_AS_GP},
+  { "mrelax-no-omit-fp", no_argument, NULL, OPTION_NO_FP_AS_GP},
+  { "mgen-symbol-ld-script", required_argument, NULL, OPTION_EXPORT_SYMBOLS},
+  /* These are specific optioins for ex9-ext support.  */
+#if defined NDS32_EX9_EXT
+  { "mex9", no_argument, NULL, OPTION_EX9_TABLE},
+  { "mno-ex9", no_argument, NULL, OPTION_NO_EX9_TABLE},
+  { "mexport-ex9", required_argument, NULL, OPTION_EXPORT_EX9},
+  { "mimport-ex9", required_argument, NULL, OPTION_IMPORT_EX9},
+  { "mupdate-ex9", no_argument, NULL, OPTION_UPDATE_EX9},
+  { "mex9-limit", required_argument, NULL, OPTION_EX9_LIMIT},
+  { "mex9-loop-aware", no_argument, NULL, OPTION_EX9_LOOP},
+#endif
+  /* These are specific optioins for ifc-ext support.  */
+#if defined NDS32_IFC_EXT
+  { "mifc", no_argument, NULL, OPTION_JUMP_IFC},
+  { "mno-ifc", no_argument, NULL, OPTION_NO_JUMP_IFC},
+  { "mifc-loop-aware", no_argument, NULL, OPTION_IFC_LOOP},
+#endif
+'
+PARSE_AND_LIST_OPTIONS='
+  fprintf (file, _("\
+  --m[no-]fp-as-gp            Disable/enable fp-as-gp relaxation\n\
+  --mexport-symbols=FILE      Exporting symbols in linker script\n\
+"));
+
+#if defined NDS32_EX9_EXT
+  fprintf (file, _("\
+  --m[no-]ex9                 Disable/enable link-time EX9 relaxation\n\
+  --mexport-ex9=FILE          Export EX9 table after linking\n\
+  --mimport-ex9=FILE          Import Ex9 table for EX9 relaxation\n\
+  --mupdate-ex9               Update existing EX9 table\n\
+  --mex9-limit=NUM            Maximum number of entries in ex9 table\n\
+  --mex9-loop-aware           Avoid generate EX9 instruction inside loop\n\
+"));
+#endif
+
+#if defined NDS32_IFC_EXT
+  fprintf (file, _("\
+  --m[no-]ifc                 Disable/enable link-time IFC optimization\n\
+  --mifc-loop-aware           Avoid generate IFC instruction inside loop\n\
+"));
+#endif
+'
+PARSE_AND_LIST_ARGS_CASES='
+  case OPTION_BASELINE:
+    einfo ("%P: --mbaseline is not used anymore.\n");
+    break;
+  case OPTION_ELIM_GC_RELOCS:
+    eliminate_gc_relocs = 1;
+    break;
+  case OPTION_FP_AS_GP:
+  case OPTION_NO_FP_AS_GP:
+    relax_fp_as_gp = (optc == OPTION_FP_AS_GP);
+    break;
+  case OPTION_REDUCE_FP_UPDATE:
+  case OPTION_NO_REDUCE_FP_UPDATE:
+    einfo ("%P: --relax-[no-]reduce-fp-updat is not used anymore.\n");
+    break;
+  case OPTION_EXPORT_SYMBOLS:
+    if (!optarg)
+      einfo (_("Missing file for --mgen-symbol-ld-script.\n"), optarg);
+
+    if(strcmp (optarg, "-") == 0)
+      sym_ld_script = stdout;
+    else
+      {
+	sym_ld_script = fopen (optarg, FOPEN_WT);
+	if(sym_ld_script == NULL)
+	  einfo (_("%P%F: cannot open map file %s: %E.\n"), optarg);
+      }
+    break;
+#if defined NDS32_EX9_EXT
+  case OPTION_EX9_TABLE:
+    target_optimize = target_optimize | NDS32_RELAX_EX9_ON;
+    break;
+  case OPTION_NO_EX9_TABLE:
+    target_optimize = target_optimize & (!NDS32_RELAX_EX9_ON);
+    break;
+  case OPTION_EXPORT_EX9:
+    if (!optarg)
+      einfo (_("Missing file for --mexport-ex9=<file>.\n"));
+
+    if(strcmp (optarg, "-") == 0)
+      ex9_export_file = stdout;
+    else
+      {
+	ex9_export_file = fopen (optarg, FOPEN_WT);
+	if(ex9_export_file == NULL)
+	  einfo (_("ERROR %P%F: cannot open ex9 export file %s.\n"), optarg);
+      }
+    break;
+  case OPTION_IMPORT_EX9:
+    if (!optarg)
+      einfo (_("Missing file for --mimport-ex9=<file>.\n"));
+
+    ex9_import_file = fopen (optarg, "r+");
+    if(ex9_import_file == NULL)
+      einfo (_("ERROR %P%F: cannot open ex9 import file %s.\n"), optarg);
+    break;
+  case OPTION_UPDATE_EX9:
+    update_ex9_table = 1;
+    break;
+  case OPTION_EX9_LIMIT:
+    if (optarg)
+      {
+	ex9_limit = atoi (optarg);
+	if (ex9_limit > 511 || ex9_limit < 1)
+	  {
+	    einfo (_("ERROR: the range of ex9_limit must between 1 and 511\n"));
+	    exit (1);
+	  }
+      }
+    break;
+  case OPTION_EX9_LOOP:
+    target_optimize = target_optimize | NDS32_RELAX_EX9_ON;
+    ex9_loop_aware = 1;
+    break;
+#endif
+#if defined NDS32_IFC_EXT
+  case OPTION_JUMP_IFC:
+    target_optimize = target_optimize | NDS32_RELAX_JUMP_IFC_ON;
+    break;
+  case OPTION_NO_JUMP_IFC:
+    target_optimize = target_optimize & (!NDS32_RELAX_JUMP_IFC_ON);
+    break;
+  case OPTION_IFC_LOOP:
+    target_optimize = target_optimize | NDS32_RELAX_JUMP_IFC_ON;
+    ifc_loop_aware = 1;
+    break;
+#endif
+'
+LDEMUL_AFTER_OPEN=nds32_elf_after_open
+LDEMUL_AFTER_PARSE=nds32_elf_after_parse
+LDEMUL_AFTER_ALLOCATION=nds32_elf_after_allocation
+LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=nds32_elf_create_output_section_statements

ld/gen-doc.texi

@@ -17,6 +17,7 @@
 @set MIPS
 @set MMIX
 @set MSP430
+@set NDS32
 @set POWERPC
 @set POWERPC64
 @set Renesas

ld/ld.texinfo

@@ -29,6 +29,7 @@
 @set MIPS
 @set MMIX
 @set MSP430
+@set NDS32
 @set POWERPC
 @set POWERPC64
 @set Renesas
@@ -6094,6 +6095,9 @@ functionality are not listed.
 @ifset MSP430
 * MSP430::			@command{ld} and MSP430
 @end ifset
+@ifset NDS32
+* NDS32::			@command{ld} and NDS32
+@end ifset
 @ifset POWERPC
 * PowerPC ELF32::		@command{ld} and PowerPC 32-bit ELF Support
 @end ifset
@@ -6684,6 +6688,54 @@ The last two sections are used by gcc.
 @end ifclear
 @end ifset
 
+@ifset NDS32
+@ifclear GENERIC
+@raisesections
+@end ifclear
+
+@node NDS32
+@section @code{ld} and NDS32
+@kindex relaxing on NDS32
+For NDS32, there are some options to select relaxation behavior.  The linker
+relaxes objects according to these options.
+
+@table @code
+@item @samp{--m[no-]fp-as-gp}
+Disable/enable fp-as-gp relaxation.
+
+@item @samp{--mexport-symbols=FILE}
+Exporting symbols and their address into FILE as linker script.
+
+@item @samp{--m[no-]ex9}
+Disable/enable link-time EX9 relaxation.
+
+@item @samp{--mexport-ex9=FILE}
+Export the EX9 table after linking.
+
+@item @samp{--mimport-ex9=FILE}
+Import the Ex9 table for EX9 relaxation.
+
+@item @samp{--mupdate-ex9}
+Update the existing EX9 table.
+
+@item @samp{--mex9-limit=NUM}
+Maximum number of entries in the ex9 table.
+
+@item @samp{--mex9-loop-aware}
+Avoid generating the EX9 instruction inside the loop.
+
+@item @samp{--m[no-]ifc}
+Disable/enable the link-time IFC optimization.
+
+@item @samp{--mifc-loop-aware}
+Avoid generating the IFC instruction inside the loop.
+@end table
+
+@ifclear GENERIC
+@lowersections
+@end ifclear
+@end ifset
+
 @ifset POWERPC
 @ifclear GENERIC
 @raisesections

ld/scripttempl/nds32elf.sc

@@ -0,0 +1,615 @@
+#  This file is variant of elf.sc.  For nds32, because the data will be
+#  classified into different sections according to their size, this script
+#  describe these sections map.  The order is ".sdata_d, .sdata_w, .sdata_h,
+#  .sdata_b, , sdata_f, .sbss_f, .sbss_b, .sbss_h, .sbss_w, .sbss_d".  In
+#  this order we do not have to consider the alignment issue between these
+#  sections.
+
+if test -n "$NOP"; then
+  FILL="=$NOP"
+else
+  FILL=
+fi
+
+test -z "$RODATA_NAME" && RODATA_NAME=rodata
+test -z "$SDATA_NAME" && SDATA_NAME=sdata
+test -z "$SBSS_NAME" && SBSS_NAME=sbss
+test -z "$BSS_NAME" && BSS_NAME=bss
+test -z "$ENTRY" && ENTRY=${USER_LABEL_PREFIX}_start
+test -z "${BIG_OUTPUT_FORMAT}" && BIG_OUTPUT_FORMAT=${OUTPUT_FORMAT}
+test -z "${LITTLE_OUTPUT_FORMAT}" && LITTLE_OUTPUT_FORMAT=${OUTPUT_FORMAT}
+if [ -z "$MACHINE" ]; then OUTPUT_ARCH=${ARCH}; else OUTPUT_ARCH=${ARCH}:${MACHINE}; fi
+test -z "${ELFSIZE}" && ELFSIZE=32
+test -z "${ALIGNMENT}" && ALIGNMENT="${ELFSIZE} / 8"
+test "$LD_FLAG" = "N" && DATA_ADDR=.
+test -z "${ETEXT_NAME}" && ETEXT_NAME=${USER_LABEL_PREFIX}etext
+test -n "$CREATE_SHLIB$CREATE_PIE" && test -n "$SHLIB_DATA_ADDR" && COMMONPAGESIZE=""
+test -z "$CREATE_SHLIB$CREATE_PIE" && test -n "$DATA_ADDR" && COMMONPAGESIZE=""
+test -n "$RELRO_NOW" && unset SEPARATE_GOTPLT
+test -z "$ATTRS_SECTIONS" && ATTRS_SECTIONS=".gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }"
+DATA_SEGMENT_ALIGN="ALIGN(${SEGMENT_SIZE}) + (. & (${MAXPAGESIZE} - 1))"
+DATA_SEGMENT_RELRO_END=""
+DATA_SEGMENT_END=""
+if test -n "${COMMONPAGESIZE}"; then
+  DATA_SEGMENT_ALIGN="ALIGN (${SEGMENT_SIZE}) - ((${MAXPAGESIZE} - .) & (${MAXPAGESIZE} - 1)); . = DATA_SEGMENT_ALIGN (${MAXPAGESIZE}, ${COMMONPAGESIZE})"
+  DATA_SEGMENT_END=". = DATA_SEGMENT_END (.);"
+  DATA_SEGMENT_RELRO_END=". = DATA_SEGMENT_RELRO_END (${SEPARATE_GOTPLT-0}, .);"
+fi
+if test -z "${INITIAL_READONLY_SECTIONS}${CREATE_SHLIB}"; then
+  INITIAL_READONLY_SECTIONS=".interp       ${RELOCATING-0} : { *(.interp) }"
+fi
+if test -z "$PLT"; then
+  IPLT=".iplt         ${RELOCATING-0} : { *(.iplt) }"
+  PLT=".plt          ${RELOCATING-0} : { *(.plt)${IREL_IN_PLT+ *(.iplt)} }
+  ${IREL_IN_PLT-$IPLT}"
+fi
+test -n "${DATA_PLT-${BSS_PLT-text}}" && TEXT_PLT=
+if test -z "$GOT"; then
+  if test -z "$SEPARATE_GOTPLT"; then
+    GOT=".got          ${RELOCATING-0} : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) }"
+  else
+    GOT=".got          ${RELOCATING-0} : { *(.got) *(.igot) }"
+    GOTPLT=".got.plt      ${RELOCATING-0} : { *(.got.plt)  *(.igot.plt) }"
+  fi
+fi
+REL_IFUNC=".rel.ifunc    ${RELOCATING-0} : { *(.rel.ifunc) }"
+RELA_IFUNC=".rela.ifunc   ${RELOCATING-0} : { *(.rela.ifunc) }"
+REL_IPLT=".rel.iplt     ${RELOCATING-0} :
+    {
+      ${RELOCATING+${CREATE_SHLIB-PROVIDE_HIDDEN (${USER_LABEL_PREFIX}__rel_iplt_start = .);}}
+      *(.rel.iplt)
+      ${RELOCATING+${CREATE_SHLIB-PROVIDE_HIDDEN (${USER_LABEL_PREFIX}__rel_iplt_end = .);}}
+    }"
+RELA_IPLT=".rela.iplt    ${RELOCATING-0} :
+    {
+      ${RELOCATING+${CREATE_SHLIB-PROVIDE_HIDDEN (${USER_LABEL_PREFIX}__rela_iplt_start = .);}}
+      *(.rela.iplt)
+      ${RELOCATING+${CREATE_SHLIB-PROVIDE_HIDDEN (${USER_LABEL_PREFIX}__rela_iplt_end = .);}}
+    }"
+DYNAMIC=".dynamic      ${RELOCATING-0} : { *(.dynamic) }"
+RODATA=".${RODATA_NAME}       ${RELOCATING-0} : { *(.${RODATA_NAME}${RELOCATING+ .${RODATA_NAME}.* .gnu.linkonce.r.*}) }"
+DATARELRO=".data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) }"
+DISCARDED="/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }"
+if test -z "${NO_SMALL_DATA}"; then
+  SBSS=".sbss_b         ${RELOCATING-0} :
+  {
+    *(.sbss_b${RELOCATING+ .sbss_b.*})
+    *(.scommon_b${RELOCATING+ .scommon_b.*})
+    ${RELOCATING+. = ALIGN(2);}
+  }
+  .sbss_h         ${RELOCATING-0} :
+  {
+    *(.sbss_h${RELOCATING+ .sbss_h.*})
+    *(.scommon_h${RELOCATING+ .scommon_h.*})
+    ${RELOCATING+. = ALIGN(4);}
+  }
+  .sbss_w         ${RELOCATING-0} :
+  {
+    *(.sbss_w${RELOCATING+ .sbss_w.*})
+    *(.scommon_w${RELOCATING+ .scommon_w.*})
+    *(.dynsbss)
+    *(.scommon)
+    ${RELOCATING+. = ALIGN(8);}
+  }
+  .sbss_d         ${RELOCATING-0} :
+  {
+    *(.sbss_d${RELOCATING+ .sbss_d.*})
+    *(.scommon_d${RELOCATING+ .scommon_d.*})
+    ${RELOCATING+PROVIDE (__sbss_end = .);}
+    ${RELOCATING+PROVIDE (___sbss_end = .);}
+  }"
+  SBSS2=".${SBSS_NAME}2        ${RELOCATING-0} : { *(.${SBSS_NAME}2${RELOCATING+ .${SBSS_NAME}2.* .gnu.linkonce.sb2.*}) }"
+  SDATA="/* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .${SDATA_NAME}        ${RELOCATING-0} :
+  {
+    ${RELOCATING+${SDATA_START_SYMBOLS}}
+    ${CREATE_SHLIB+*(.${SDATA_NAME}2 .${SDATA_NAME}2.* .gnu.linkonce.s2.*)}
+    *(.${SDATA_NAME}${RELOCATING+ .${SDATA_NAME}.* .gnu.linkonce.s.*})
+  }
+  .sdata_d        ${RELOCATING-0} :
+  {
+    *(.sdata_d${RELOCATING+ .sdata_d.*})
+  }
+  .sdata_w        ${RELOCATING-0} :
+  {
+    *(.sdata_w${RELOCATING+ .sdata_w.*})
+  }
+  .sdata_h        ${RELOCATING-0} :
+  {
+    *(.sdata_h${RELOCATING+ .sdata_h.*})
+  }
+  .sdata_b        ${RELOCATING-0} :
+  {
+    *(.sdata_b${RELOCATING+ .sdata_b.*})
+  }
+  .sdata_f        ${RELOCATING-0} :
+  {
+    *(.sdata_f${RELOCATING+ .sdata_f.*})
+  }"
+  SDATA2=".${SDATA_NAME}2       ${RELOCATING-0} :
+  {
+    ${RELOCATING+${SDATA2_START_SYMBOLS}}
+    *(.${SDATA_NAME}2${RELOCATING+ .${SDATA_NAME}2.* .gnu.linkonce.s2.*})
+  }"
+  REL_SDATA=".rel.${SDATA_NAME}    ${RELOCATING-0} : { *(.rel.${SDATA_NAME}${RELOCATING+ .rel.${SDATA_NAME}.* .rel.gnu.linkonce.s.*}) }
+  .rela.${SDATA_NAME}   ${RELOCATING-0} : { *(.rela.${SDATA_NAME}${RELOCATING+ .rela.${SDATA_NAME}.* .rela.gnu.linkonce.s.*}) }"
+  REL_SBSS=".rel.${SBSS_NAME}     ${RELOCATING-0} : { *(.rel.${SBSS_NAME}${RELOCATING+ .rel.${SBSS_NAME}.* .rel.gnu.linkonce.sb.*}) }
+  .rela.${SBSS_NAME}    ${RELOCATING-0} : { *(.rela.${SBSS_NAME}${RELOCATING+ .rela.${SBSS_NAME}.* .rela.gnu.linkonce.sb.*}) }"
+  REL_SDATA2=".rel.${SDATA_NAME}2   ${RELOCATING-0} : { *(.rel.${SDATA_NAME}2${RELOCATING+ .rel.${SDATA_NAME}2.* .rel.gnu.linkonce.s2.*}) }
+  .rela.${SDATA_NAME}2  ${RELOCATING-0} : { *(.rela.${SDATA_NAME}2${RELOCATING+ .rela.${SDATA_NAME}2.* .rela.gnu.linkonce.s2.*}) }"
+  REL_SBSS2=".rel.${SBSS_NAME}2    ${RELOCATING-0} : { *(.rel.${SBSS_NAME}2${RELOCATING+ .rel.${SBSS_NAME}2.* .rel.gnu.linkonce.sb2.*}) }
+  .rela.${SBSS_NAME}2   ${RELOCATING-0} : { *(.rela.${SBSS_NAME}2${RELOCATING+ .rela.${SBSS_NAME}2.* .rela.gnu.linkonce.sb2.*}) }"
+else
+  NO_SMALL_DATA=" "
+fi
+if test -z "${DATA_GOT}"; then
+  if test -n "${NO_SMALL_DATA}"; then
+    DATA_GOT=" "
+  fi
+fi
+if test -z "${SDATA_GOT}"; then
+  if test -z "${NO_SMALL_DATA}"; then
+    SDATA_GOT=" "
+  fi
+fi
+test -n "$SEPARATE_GOTPLT" && SEPARATE_GOTPLT=" "
+test "${LARGE_SECTIONS}" = "yes" && REL_LARGE="
+  .rel.ldata    ${RELOCATING-0} : { *(.rel.ldata${RELOCATING+ .rel.ldata.* .rel.gnu.linkonce.l.*}) }
+  .rela.ldata   ${RELOCATING-0} : { *(.rela.ldata${RELOCATING+ .rela.ldata.* .rela.gnu.linkonce.l.*}) }
+  .rel.lbss     ${RELOCATING-0} : { *(.rel.lbss${RELOCATING+ .rel.lbss.* .rel.gnu.linkonce.lb.*}) }
+  .rela.lbss    ${RELOCATING-0} : { *(.rela.lbss${RELOCATING+ .rela.lbss.* .rela.gnu.linkonce.lb.*}) }
+  .rel.lrodata  ${RELOCATING-0} : { *(.rel.lrodata${RELOCATING+ .rel.lrodata.* .rel.gnu.linkonce.lr.*}) }
+  .rela.lrodata ${RELOCATING-0} : { *(.rela.lrodata${RELOCATING+ .rela.lrodata.* .rela.gnu.linkonce.lr.*}) }"
+test "${LARGE_SECTIONS}" = "yes" && LARGE_BSS="
+  .lbss ${RELOCATING-0} :
+  {
+    *(.dynlbss)
+    *(.lbss${RELOCATING+ .lbss.* .gnu.linkonce.lb.*})
+    *(LARGE_COMMON)
+  }"
+test "${LARGE_SECTIONS}" = "yes" && LARGE_SECTIONS="
+  .lrodata ${RELOCATING-0} ${RELOCATING+ALIGN(${MAXPAGESIZE}) + (. & (${MAXPAGESIZE} - 1))} :
+  {
+    *(.lrodata${RELOCATING+ .lrodata.* .gnu.linkonce.lr.*})
+  }
+  .ldata ${RELOCATING-0} ${RELOCATING+ALIGN(${MAXPAGESIZE}) + (. & (${MAXPAGESIZE} - 1))} :
+  {
+    *(.ldata${RELOCATING+ .ldata.* .gnu.linkonce.l.*})
+    ${RELOCATING+. = ALIGN(. != 0 ? ${ALIGNMENT} : 1);}
+  }"
+if test "${ENABLE_INITFINI_ARRAY}" = "yes"; then
+  SORT_INIT_ARRAY="KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))"
+  SORT_FINI_ARRAY="KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))"
+  CTORS_IN_INIT_ARRAY="EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o $OTHER_EXCLUDE_FILES) .ctors"
+  DTORS_IN_FINI_ARRAY="EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o $OTHER_EXCLUDE_FILES) .dtors"
+else
+  SORT_INIT_ARRAY="KEEP (*(SORT(.init_array.*)))"
+  SORT_FINI_ARRAY="KEEP (*(SORT(.fini_array.*)))"
+  CTORS_IN_INIT_ARRAY=
+  DTORS_IN_FINI_ARRAY=
+fi
+INIT_ARRAY=".init_array   ${RELOCATING-0} :
+  {
+    ${RELOCATING+${CREATE_SHLIB-PROVIDE_HIDDEN (${USER_LABEL_PREFIX}__init_array_start = .);}}
+    ${SORT_INIT_ARRAY}
+    KEEP (*(.init_array ${CTORS_IN_INIT_ARRAY}))
+    ${RELOCATING+${CREATE_SHLIB-PROVIDE_HIDDEN (${USER_LABEL_PREFIX}__init_array_end = .);}}
+  }"
+FINI_ARRAY=".fini_array   ${RELOCATING-0} :
+  {
+    ${RELOCATING+${CREATE_SHLIB-PROVIDE_HIDDEN (${USER_LABEL_PREFIX}__fini_array_start = .);}}
+    ${SORT_FINI_ARRAY}
+    KEEP (*(.fini_array ${DTORS_IN_FINI_ARRAY}))
+    ${RELOCATING+${CREATE_SHLIB-PROVIDE_HIDDEN (${USER_LABEL_PREFIX}__fini_array_end = .);}}
+  }"
+CTOR=".ctors        ${CONSTRUCTING-0} :
+  {
+    ${CONSTRUCTING+${CTOR_START}}
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o $OTHER_EXCLUDE_FILES) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    ${CONSTRUCTING+${CTOR_END}}
+  }"
+DTOR=".dtors        ${CONSTRUCTING-0} :
+  {
+    ${CONSTRUCTING+${DTOR_START}}
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o $OTHER_EXCLUDE_FILES) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    ${CONSTRUCTING+${DTOR_END}}
+  }"
+STACK="  .stack        ${RELOCATING-0}${RELOCATING+${STACK_ADDR}} :
+  {
+    ${RELOCATING+${USER_LABEL_PREFIX}_stack = .;}
+    *(.stack)
+  }"
+
+TEXT_START_ADDR="SEGMENT_START(\"text-segment\", ${TEXT_START_ADDR})"
+SHLIB_TEXT_START_ADDR="SEGMENT_START(\"text-segment\", ${SHLIB_TEXT_START_ADDR:-0})"
+
+if [ -z "$SEPARATE_CODE" ]; then
+  SIZEOF_HEADERS_CODE=" + SIZEOF_HEADERS"
+else
+  SIZEOF_HEADERS_CODE=
+fi
+
+# if this is for an embedded system, don't add SIZEOF_HEADERS.
+if [ -z "$EMBEDDED" ]; then
+   test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR}${SIZEOF_HEADERS_CODE}"
+    NDS32_INIT=""
+else
+   test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR}"
+   NDS32_INIT=".nds32_init     : { KEEP(*(.nds32_init)) }"
+fi
+
+cat <<EOF
+OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}",
+	      "${LITTLE_OUTPUT_FORMAT}")
+OUTPUT_ARCH(${OUTPUT_ARCH})
+${RELOCATING+ENTRY(${ENTRY})}
+
+${RELOCATING+${LIB_SEARCH_DIRS}}
+${RELOCATING+${EXECUTABLE_SYMBOLS}}
+${RELOCATING+${INPUT_FILES}}
+${RELOCATING- /* For some reason, the Solaris linker makes bad executables
+  if gld -r is used and the intermediate file has sections starting
+  at non-zero addresses.  Could be a Solaris ld bug, could be a GNU ld
+  bug.  But for now assigning the zero vmas works.  */}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  ${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+PROVIDE (__executable_start = ${TEXT_START_ADDR}); . = ${TEXT_BASE_ADDRESS};}}}
+  /* Sections saved crt0 and crt1.  */
+  ${NDS32_INIT}
+  ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR}${SIZEOF_HEADERS_CODE};}}
+  ${CREATE_PIE+${RELOCATING+PROVIDE (__executable_start = ${SHLIB_TEXT_START_ADDR}); . = ${SHLIB_TEXT_START_ADDR}${SIZEOF_HEADERS_CODE};}}
+EOF
+
+emit_early_ro()
+{
+  cat <<EOF
+  ${INITIAL_READONLY_SECTIONS}
+  .note.gnu.build-id : { *(.note.gnu.build-id) }
+EOF
+}
+
+test -n "${SEPARATE_CODE}" || emit_early_ro
+
+test -n "${RELOCATING+0}" || unset NON_ALLOC_DYN
+test -z "${NON_ALLOC_DYN}" || TEXT_DYNAMIC=
+cat > ldscripts/dyntmp.$$ <<EOF
+  ${TEXT_DYNAMIC+${DYNAMIC}}
+  .hash         ${RELOCATING-0} : { *(.hash) }
+  .gnu.hash     ${RELOCATING-0} : { *(.gnu.hash) }
+  .dynsym       ${RELOCATING-0} : { *(.dynsym) }
+  .dynstr       ${RELOCATING-0} : { *(.dynstr) }
+  .gnu.version  ${RELOCATING-0} : { *(.gnu.version) }
+  .gnu.version_d ${RELOCATING-0}: { *(.gnu.version_d) }
+  .gnu.version_r ${RELOCATING-0}: { *(.gnu.version_r) }
+EOF
+
+if [ "x$COMBRELOC" = x ]; then
+  COMBRELOCCAT="cat >> ldscripts/dyntmp.$$"
+else
+  COMBRELOCCAT="cat > $COMBRELOC"
+fi
+eval $COMBRELOCCAT <<EOF
+  ${INITIAL_RELOC_SECTIONS}
+  .rel.init     ${RELOCATING-0} : { *(.rel.init) }
+  .rela.init    ${RELOCATING-0} : { *(.rela.init) }
+  .rel.text     ${RELOCATING-0} : { *(.rel.text${RELOCATING+ .rel.text.* .rel.gnu.linkonce.t.*}) }
+  .rela.text    ${RELOCATING-0} : { *(.rela.text${RELOCATING+ .rela.text.* .rela.gnu.linkonce.t.*}) }
+  .rel.fini     ${RELOCATING-0} : { *(.rel.fini) }
+  .rela.fini    ${RELOCATING-0} : { *(.rela.fini) }
+  .rel.${RODATA_NAME}   ${RELOCATING-0} : { *(.rel.${RODATA_NAME}${RELOCATING+ .rel.${RODATA_NAME}.* .rel.gnu.linkonce.r.*}) }
+  .rela.${RODATA_NAME}  ${RELOCATING-0} : { *(.rela.${RODATA_NAME}${RELOCATING+ .rela.${RODATA_NAME}.* .rela.gnu.linkonce.r.*}) }
+  ${OTHER_READONLY_RELOC_SECTIONS}
+  .rel.data.rel.ro ${RELOCATING-0} : { *(.rel.data.rel.ro${RELOCATING+ .rel.data.rel.ro.* .rel.gnu.linkonce.d.rel.ro.*}) }
+  .rela.data.rel.ro ${RELOCATING-0} : { *(.rela.data.rel.ro${RELOCATING+ .rela.data.rel.ro.* .rela.gnu.linkonce.d.rel.ro.*}) }
+  .rel.data     ${RELOCATING-0} : { *(.rel.data${RELOCATING+ .rel.data.* .rel.gnu.linkonce.d.*}) }
+  .rela.data    ${RELOCATING-0} : { *(.rela.data${RELOCATING+ .rela.data.* .rela.gnu.linkonce.d.*}) }
+  ${OTHER_READWRITE_RELOC_SECTIONS}
+  .rel.tdata	${RELOCATING-0} : { *(.rel.tdata${RELOCATING+ .rel.tdata.* .rel.gnu.linkonce.td.*}) }
+  .rela.tdata	${RELOCATING-0} : { *(.rela.tdata${RELOCATING+ .rela.tdata.* .rela.gnu.linkonce.td.*}) }
+  .rel.tbss	${RELOCATING-0} : { *(.rel.tbss${RELOCATING+ .rel.tbss.* .rel.gnu.linkonce.tb.*}) }
+  .rela.tbss	${RELOCATING-0} : { *(.rela.tbss${RELOCATING+ .rela.tbss.* .rela.gnu.linkonce.tb.*}) }
+  .rel.ctors    ${RELOCATING-0} : { *(.rel.ctors) }
+  .rela.ctors   ${RELOCATING-0} : { *(.rela.ctors) }
+  .rel.dtors    ${RELOCATING-0} : { *(.rel.dtors) }
+  .rela.dtors   ${RELOCATING-0} : { *(.rela.dtors) }
+  .rel.got      ${RELOCATING-0} : { *(.rel.got) }
+  .rela.got     ${RELOCATING-0} : { *(.rela.got) }
+  ${OTHER_GOT_RELOC_SECTIONS}
+  ${REL_SDATA}
+  ${REL_SBSS}
+  ${REL_SDATA2}
+  ${REL_SBSS2}
+  .rel.${BSS_NAME}      ${RELOCATING-0} : { *(.rel.${BSS_NAME}${RELOCATING+ .rel.${BSS_NAME}.* .rel.gnu.linkonce.b.*}) }
+  .rela.${BSS_NAME}     ${RELOCATING-0} : { *(.rela.${BSS_NAME}${RELOCATING+ .rela.${BSS_NAME}.* .rela.gnu.linkonce.b.*}) }
+  ${REL_LARGE}
+  ${IREL_IN_PLT+$REL_IFUNC}
+  ${IREL_IN_PLT+$RELA_IFUNC}
+  ${IREL_IN_PLT-$REL_IPLT}
+  ${IREL_IN_PLT-$RELA_IPLT}
+EOF
+
+if [ -n "$COMBRELOC" ]; then
+cat >> ldscripts/dyntmp.$$ <<EOF
+  .rel.dyn      ${RELOCATING-0} :
+    {
+EOF
+sed -e '/^[ 	]*[{}][ 	]*$/d;/:[ 	]*$/d;/\.rela\./d;s/^.*: { *\(.*\)}$/      \1/' $COMBRELOC >> ldscripts/dyntmp.$$
+cat >> ldscripts/dyntmp.$$ <<EOF
+    }
+  .rela.dyn     ${RELOCATING-0} :
+    {
+EOF
+sed -e '/^[ 	]*[{}][ 	]*$/d;/:[ 	]*$/d;/\.rel\./d;s/^.*: { *\(.*\)}/      \1/' $COMBRELOC >> ldscripts/dyntmp.$$
+cat >> ldscripts/dyntmp.$$ <<EOF
+    }
+EOF
+fi
+
+cat >> ldscripts/dyntmp.$$ <<EOF
+  .rel.plt      ${RELOCATING-0} :
+    {
+      *(.rel.plt)
+      ${IREL_IN_PLT+${RELOCATING+${CREATE_SHLIB-PROVIDE_HIDDEN (${USER_LABEL_PREFIX}__rel_iplt_start = .);}}}
+      ${IREL_IN_PLT+${RELOCATING+*(.rel.iplt)}}
+      ${IREL_IN_PLT+${RELOCATING+${CREATE_SHLIB-PROVIDE_HIDDEN (${USER_LABEL_PREFIX}__rel_iplt_end = .);}}}
+    }
+  .rela.plt     ${RELOCATING-0} :
+    {
+      *(.rela.plt)
+      ${IREL_IN_PLT+${RELOCATING+${CREATE_SHLIB-PROVIDE_HIDDEN (${USER_LABEL_PREFIX}__rela_iplt_start = .);}}}
+      ${IREL_IN_PLT+${RELOCATING+*(.rela.iplt)}}
+      ${IREL_IN_PLT+${RELOCATING+${CREATE_SHLIB-PROVIDE_HIDDEN (${USER_LABEL_PREFIX}__rela_iplt_end = .);}}}
+    }
+  ${OTHER_PLT_RELOC_SECTIONS}
+EOF
+
+emit_dyn()
+{
+  if test -z "${NO_REL_RELOCS}${NO_RELA_RELOCS}"; then
+    cat ldscripts/dyntmp.$$
+  else
+    if test -z "${NO_REL_RELOCS}"; then
+      sed -e '/^[ 	]*\.rela\.[^}]*$/,/}/d' -e '/^[ 	]*\.rela\./d' ldscripts/dyntmp.$$
+    fi
+    if test -z "${NO_RELA_RELOCS}"; then
+      sed -e '/^[ 	]*\.rel\.[^}]*$/,/}/d' -e '/^[ 	]*\.rel\./d' ldscripts/dyntmp.$$
+    fi
+  fi
+  rm -f ldscripts/dyntmp.$$
+}
+
+test -n "${NON_ALLOC_DYN}${SEPARATE_CODE}" || emit_dyn
+
+cat <<EOF
+  .init         ${RELOCATING-0} :
+  {
+    ${RELOCATING+${INIT_START}}
+    KEEP (*(SORT_NONE(.init)))
+    ${RELOCATING+${INIT_END}}
+  } ${FILL}
+
+  ${TEXT_PLT+${PLT_NEXT_DATA-${PLT}}}
+  ${TINY_READONLY_SECTION}
+  .text         ${RELOCATING-0} :
+  {
+    ${RELOCATING+${TEXT_START_SYMBOLS}}
+    ${RELOCATING+*(.text.unlikely .text.*_unlikely .text.unlikely.*)}
+    ${RELOCATING+*(.text.exit .text.exit.*)}
+    ${RELOCATING+*(.text.startup .text.startup.*)}
+    ${RELOCATING+*(.text.hot .text.hot.*)}
+    *(.text .stub${RELOCATING+ .text.* .gnu.linkonce.t.*})
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    ${RELOCATING+${OTHER_TEXT_SECTIONS}}
+  } ${FILL}
+  .fini         ${RELOCATING-0} :
+  {
+    ${RELOCATING+${FINI_START}}
+    KEEP (*(SORT_NONE(.fini)))
+    ${RELOCATING+${FINI_END}}
+  } ${FILL}
+  ${RELOCATING+PROVIDE (__${ETEXT_NAME} = .);}
+  ${RELOCATING+PROVIDE (_${ETEXT_NAME} = .);}
+  ${RELOCATING+PROVIDE (${ETEXT_NAME} = .);}
+EOF
+
+if test -n "${SEPARATE_CODE}"; then
+  if test -n "${RODATA_ADDR}"; then
+    RODATA_ADDR="\
+SEGMENT_START(\"rodata-segment\", ${RODATA_ADDR}) + SIZEOF_HEADERS"
+  else
+    RODATA_ADDR="ALIGN(${SEGMENT_SIZE}) + (. & (${MAXPAGESIZE} - 1))"
+    RODATA_ADDR="SEGMENT_START(\"rodata-segment\", ${RODATA_ADDR})"
+  fi
+  if test -n "${SHLIB_RODATA_ADDR}"; then
+    SHLIB_RODATA_ADDR="\
+SEGMENT_START(\"rodata-segment\", ${SHLIB_RODATA_ADDR}) + SIZEOF_HEADERS"
+  else
+    SHLIB_RODATA_ADDR="SEGMENT_START(\"rodata-segment\", ${SHLIB_RODATA_ADDR})"
+    SHLIB_RODATA_ADDR="ALIGN(${SEGMENT_SIZE}) + (. & (${MAXPAGESIZE} - 1))"
+  fi
+  cat <<EOF
+  /* Adjust the address for the rodata segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  ${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+. = ${RODATA_ADDR};}}}
+  ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_RODATA_ADDR};}}
+  ${CREATE_PIE+${RELOCATING+. = ${SHLIB_RODATA_ADDR};}}
+EOF
+  emit_early_ro
+  emit_dyn
+fi
+
+cat <<EOF
+  ${WRITABLE_RODATA-${RODATA}}
+  .${RODATA_NAME}1      ${RELOCATING-0} : { *(.${RODATA_NAME}1) }
+  ${CREATE_SHLIB-${SDATA2}}
+  ${CREATE_SHLIB-${SBSS2}}
+  ${OTHER_READONLY_SECTIONS}
+  .eh_frame_hdr : { *(.eh_frame_hdr) }
+  .eh_frame     ${RELOCATING-0} : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+  .gcc_except_table ${RELOCATING-0} : ONLY_IF_RO { *(.gcc_except_table
+  .gcc_except_table.*) }
+  /* These sections are generated by the Sun/Oracle C++ compiler.  */
+  .exception_ranges ${RELOCATING-0} : ONLY_IF_RO { *(.exception_ranges
+  .exception_ranges*) }
+  ${TEXT_PLT+${PLT_NEXT_DATA+${PLT}}}
+
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  ${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+. = ${DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}}
+  ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}
+  ${CREATE_PIE+${RELOCATING+. = ${SHLIB_DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}
+
+  /* Exception handling  */
+  .eh_frame     ${RELOCATING-0} : ONLY_IF_RW { KEEP (*(.eh_frame)) }
+  .gcc_except_table ${RELOCATING-0} : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }
+  .exception_ranges ${RELOCATING-0} : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) }
+
+  /* Thread Local Storage sections  */
+  .tdata	${RELOCATING-0} : { *(.tdata${RELOCATING+ .tdata.* .gnu.linkonce.td.*}) }
+  .tbss		${RELOCATING-0} : { *(.tbss${RELOCATING+ .tbss.* .gnu.linkonce.tb.*})${RELOCATING+ *(.tcommon)} }
+
+  .preinit_array   ${RELOCATING-0} :
+  {
+    ${RELOCATING+${CREATE_SHLIB-PROVIDE_HIDDEN (${USER_LABEL_PREFIX}__preinit_array_start = .);}}
+    KEEP (*(.preinit_array))
+    ${RELOCATING+${CREATE_SHLIB-PROVIDE_HIDDEN (${USER_LABEL_PREFIX}__preinit_array_end = .);}}
+  }
+  ${RELOCATING+${INIT_ARRAY}}
+  ${RELOCATING+${FINI_ARRAY}}
+  ${SMALL_DATA_CTOR-${RELOCATING+${CTOR}}}
+  ${SMALL_DATA_DTOR-${RELOCATING+${DTOR}}}
+  .jcr          ${RELOCATING-0} : { KEEP (*(.jcr)) }
+
+  ${RELOCATING+${DATARELRO}}
+  ${OTHER_RELRO_SECTIONS}
+  ${TEXT_DYNAMIC-${DYNAMIC}}
+  ${DATA_GOT+${RELRO_NOW+${GOT}}}
+  ${DATA_GOT+${RELRO_NOW+${GOTPLT}}}
+  ${DATA_GOT+${RELRO_NOW-${SEPARATE_GOTPLT+${GOT}}}}
+  ${RELOCATING+${DATA_SEGMENT_RELRO_END}}
+  ${INITIAL_READWRITE_SECTIONS}
+  ${DATA_GOT+${RELRO_NOW-${SEPARATE_GOTPLT-${GOT}}}}
+  ${DATA_GOT+${RELRO_NOW-${GOTPLT}}}
+
+  ${DATA_PLT+${PLT_BEFORE_GOT-${PLT}}}
+
+  /*  For _SDA_BASE_ aligment.  */
+  ${RELOCATING+. = ALIGN(4);}
+
+  .data         ${RELOCATING-0} :
+  {
+    ${RELOCATING+${DATA_START_SYMBOLS}}
+    *(.data${RELOCATING+ .data.* .gnu.linkonce.d.*})
+    ${CONSTRUCTING+SORT(CONSTRUCTORS)}
+  }
+  .data1        ${RELOCATING-0} : { *(.data1) }
+  ${WRITABLE_RODATA+${RODATA}}
+  ${OTHER_READWRITE_SECTIONS}
+  ${SMALL_DATA_CTOR+${RELOCATING+${CTOR}}}
+  ${SMALL_DATA_DTOR+${RELOCATING+${DTOR}}}
+  ${RELOCATING+. = ALIGN(4);}
+  ${DATA_PLT+${PLT_BEFORE_GOT+${PLT}}}
+  ${SDATA_GOT+${RELOCATING+${OTHER_GOT_SYMBOLS+. = .; ${OTHER_GOT_SYMBOLS}}}}
+  ${SDATA_GOT+${GOT}}
+  ${SDATA_GOT+${OTHER_GOT_SECTIONS}}
+  ${SDATA}
+  ${OTHER_SDATA_SECTIONS}
+  ${RELOCATING+. = ALIGN(4);}
+  ${RELOCATING+${DATA_END_SYMBOLS-${USER_LABEL_PREFIX}_edata = .; PROVIDE (${USER_LABEL_PREFIX}edata = .);}}
+  ${RELOCATING+. = .;}
+  ${RELOCATING+${USER_LABEL_PREFIX}__bss_start = .;}
+  ${RELOCATING+${OTHER_BSS_SYMBOLS}}
+  ${SBSS}
+  ${BSS_PLT+${PLT}}
+  .${BSS_NAME}          ${RELOCATING-0} :
+  {
+   *(.dyn${BSS_NAME})
+   *(.${BSS_NAME}${RELOCATING+ .${BSS_NAME}.* .gnu.linkonce.b.*})
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.
+      FIXME: Why do we need it? When there is no .bss section, we don't
+      pad the .data section.  */
+   ${RELOCATING+. = ALIGN(. != 0 ? ${ALIGNMENT} : 1);}
+  }
+  ${OTHER_BSS_SECTIONS}
+  ${LARGE_BSS_AFTER_BSS+${LARGE_BSS}}
+  ${RELOCATING+_end = .;}
+  ${RELOCATING+${OTHER_BSS_END_SYMBOLS}}
+  ${RELOCATING+. = ALIGN(${ALIGNMENT});}
+EOF
+
+LARGE_DATA_ADDR=". = SEGMENT_START(\"ldata-segment\", ${LARGE_DATA_ADDR-.});"
+SHLIB_LARGE_DATA_ADDR=". = SEGMENT_START(\"ldata-segment\", ${SHLIB_LARGE_DATA_ADDR-.});"
+
+  cat <<EOF
+  ${RELOCATING+${CREATE_SHLIB-${CREATE_PIE-${LARGE_DATA_ADDR}}}}
+  ${RELOCATING+${CREATE_SHLIB+${SHLIB_LARGE_DATA_ADDR}}}
+  ${RELOCATING+${CREATE_PIE+${SHLIB_LARGE_DATA_ADDR}}}
+  ${LARGE_SECTIONS}
+  ${LARGE_BSS_AFTER_BSS-${LARGE_BSS}}
+  ${RELOCATING+. = ALIGN(${ALIGNMENT});}
+  ${RELOCATING+${OTHER_END_SYMBOLS}}
+  ${RELOCATING+${END_SYMBOLS-${USER_LABEL_PREFIX}_end = .; PROVIDE (${USER_LABEL_PREFIX}end = .);}}
+  ${RELOCATING+${DATA_SEGMENT_END}}
+EOF
+
+test -z "${NON_ALLOC_DYN}" || emit_dyn
+
+cat <<EOF
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+
+  .comment       0 : { *(.comment) }
+
+EOF
+
+. $srcdir/scripttempl/DWARF.sc
+
+cat <<EOF
+
+  ${TINY_DATA_SECTION}
+  ${TINY_BSS_SECTION}
+
+  ${STACK_ADDR+${STACK}}
+  ${ATTRS_SECTIONS}
+  ${OTHER_SECTIONS}
+  ${RELOCATING+${OTHER_SYMBOLS}}
+  ${RELOCATING+${DISCARDED}}
+}
+EOF

ld/testsuite/ChangeLog

@@ -1,3 +1,29 @@
+2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
+
+	* lib/ld-lib.exp: Add NDS32 to list of targets that do not support
+	shared library generation.
+	* ld-nds32: New directory.
+	* ld-nds32/branch.d: New test.
+	* ld-nds32/branch.ld: New test.
+	* ld-nds32/branch.s: New test.
+	* ld-nds32/diff.d: New test.
+	* ld-nds32/diff.ld: New test.
+	* ld-nds32/diff.s: New test.
+	* ld-nds32/gp.d: New test.
+	* ld-nds32/gp.ld: New test.
+	* ld-nds32/gp.s: New test.
+	* ld-nds32/imm.d: New test.
+	* ld-nds32/imm.ld: New test.
+	* ld-nds32/imm.s: New test.
+	* ld-nds32/imm_symbol.s: New test.
+	* ld-nds32/relax_jmp.d: New test.
+	* ld-nds32/relax_jmp.ld: New test.
+	* ld-nds32/relax_jmp.s: New test.
+	* ld-nds32/relax_load_store.d: New test.
+	* ld-nds32/relax_load_store.ld: New test.
+	* ld-nds32/relax_load_store.s: New test.
+	* ld-nds32/nds32.exp: New file.
+
 2013-12-12  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* ld-elf/ehdr_start-userdef.d: Add "#...".

ld/testsuite/ld-nds32/branch.d

@@ -0,0 +1,24 @@
+#as: -Os
+#ld: -static --relax -T	$srcdir/$subdir/branch.ld
+#objdump: -d --prefix-addresses -j .text
+
+.*:     file format .*nds32.*
+
+
+Disassembly of section .text:
+0+0000 <[^>]*> beq	\$r0, \$r1, 0000002c <main>
+0+0004 <[^>]*> bne	\$r0, \$r1, 0000002c <main>
+0+0008 <[^>]*> bnez38	\$r0, 0000002c <main>
+0+000a <[^>]*> beqz38	\$r0, 0000002c <main>
+0+000c <[^>]*> bgez	\$r0, 0000002c <main>
+.*
+0+0012 <[^>]*> bgezal	\$r0, 0000002c <main>
+0+0016 <[^>]*> bgtz	\$r0, 0000002c <main>
+.*
+0+001c <[^>]*> blez	\$r0, 0000002c <main>
+.*
+0+0022 <[^>]*> bltz	\$r0, 0000002c <main>
+0+0026 <[^>]*> srli45	\$r0, 0
+0+0028 <[^>]*> bltzal	\$r0, 0000002c <main>
+0+002c <main>.*
+

ld/testsuite/ld-nds32/branch.ld

@@ -0,0 +1,6 @@
+SECTIONS
+{
+  .text 0x0 : {
+    * (.text .text.*);
+  }
+}

ld/testsuite/ld-nds32/branch.s

@@ -0,0 +1,18 @@
+.text
+.global	_start
+_start:
+	beq $r0, $r1, main
+	bne $r0, $r1, main
+	beqz $r0, main
+	bnez $r0, main
+	bgez $r0, main
+	bgezal $r0, main
+	bgtz $r0, main
+	blez $r0, main
+	bltz $r0, main
+	bltzal $r0, main
+.section .text.2, "ax"
+.globl main
+main:
+	nop
+

ld/testsuite/ld-nds32/diff.d

@@ -0,0 +1,16 @@
+#as: -Os
+#ld: -static --relax -T $srcdir/$subdir/diff.ld
+#objdump: -D --prefix-addresses -j .data --show-raw-insn
+
+.*:     file format .*nds32.*
+
+
+Disassembly of section .data:
+00008000 <WORD> (7e 00 00 00|00 00 00 7e).*
+00008004 <HALF> (7e 00 7e fe|00 7e 7e fe).*
+00008006 <BYTE> 7e fe 00 fe.*
+00008007 <ULEB128> fe 00.*
+	...
+00008009 <ULEB128_2> fe 00.*
+.*
+.*

ld/testsuite/ld-nds32/diff.ld

@@ -0,0 +1,10 @@
+SECTIONS
+{
+  .text 0x4000 : {
+    * (.text .text.*);
+  }
+
+  .data 0x8000 : {
+    * (.data .data.*);
+  }
+}

ld/testsuite/ld-nds32/diff.s

@@ -0,0 +1,32 @@
+	.global	_start
+	.global	WORD
+	.global	HALF
+	.global	BYTE
+	.global	ULEB128
+.text
+_start:
+	nop
+.L0:
+	l.w	$r0, WORD
+	.zero	122
+.L1:
+	nop
+
+.section	code, "ax"
+FOO:
+	ret
+
+.data
+WORD:
+	.word		.L1-.L0
+HALF:
+	.half		.L1-.L0
+BYTE:
+	.byte		.L1-.L0
+ULEB128:
+	.uleb128	.L1-.L0
+ULEB128_2:
+	.uleb128	.L1-.L0
+	.align 2
+PAD:
+	.long		0

ld/testsuite/ld-nds32/gp.d

@@ -0,0 +1,18 @@
+#as: -Os
+#ld: -static -T	\$srcdir/\$subdir/gp.ld
+#objdump: -d --prefix-addresses -j .text
+
+.*:     file format .*nds32.*
+
+
+Disassembly of section .text:
+0+0000 <[^>]*> addi.gp	\$r0, 8192
+0+0004 <[^>]*> lbi.gp	\$r0, \[\+ 8192\]
+0+0008 <[^>]*> lbsi.gp	\$r0, \[\+ 8192\]
+0+000c <[^>]*> lhi.gp	\$r0, \[\+ 8192\]
+0+0010 <[^>]*> lhsi.gp	\$r0, \[\+ 8192\]
+0+0014 <[^>]*> lwi.gp	\$r0, \[\+ 8192\]
+0+0018 <[^>]*> sbi.gp	\$r0, \[\+ 8192\]
+0+001c <[^>]*> shi.gp	\$r0, \[\+ 8192\]
+0+0020 <[^>]*> swi.gp	\$r0, \[\+ 8192\]
+

ld/testsuite/ld-nds32/gp.ld

@@ -0,0 +1,11 @@
+SECTIONS
+{
+  .text 0x0 : {
+    * (.text .text.*);
+  }
+
+  .data 0x3000 : {
+    * (.data .data.*);
+  }
+  _SDA_BASE_ = 0x1000;
+}

ld/testsuite/ld-nds32/gp.s

@@ -0,0 +1,18 @@
+.data
+.global mydata
+mydata:
+	.word 0x11
+
+.text
+.global	_start
+_start:
+	addi.gp $r0, mydata
+	lbi.gp $r0, [+mydata]
+	lbsi.gp $r0, [+mydata]
+	lhi.gp $r0, [+mydata]
+	lhsi.gp $r0, [+mydata]
+	lwi.gp $r0, [+mydata]
+	sbi.gp $r0, [+mydata]
+	shi.gp $r0, [+mydata]
+	swi.gp $r0, [+mydata]
+

ld/testsuite/ld-nds32/imm.d

@@ -0,0 +1,15 @@
+#source: imm.s
+#source: imm_symbol.s
+#as: -Os
+#ld: -static -T	$srcdir/$subdir/imm.ld --relax
+#objdump: -d --prefix-addresses -j .text
+
+.*:     file format .*nds32.*
+
+
+Disassembly of section .text:
+0+1000 <[^>]*> sethi	\$r0, 0x11223
+0+1004 <[^>]*> ori	\$r0, \$r0, 836
+0+1008 <[^>]*> movi	\$r0, 70179
+0+100c <[^>]*> movi55	\$r0, 15
+

ld/testsuite/ld-nds32/imm.ld

@@ -0,0 +1,6 @@
+SECTIONS
+{
+  .text 0x1000 : {
+    * (.text .text.*);
+  }
+}

ld/testsuite/ld-nds32/imm.s

@@ -0,0 +1,7 @@
+.text
+.global	_start
+_start:
+	la $r0, imm32
+	la $r0, imm20
+	la $r0, imm5
+