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[AArch64] PR target/20667, fix disassembler for the "special" optional SYS_Rt operand for "ic"/"tlbi"
gas/ PR target/20667 * testsuite/gas/aarch64/sys-rt-reg.s: Test source for instructions using SYS_Rt reg. * testsuite/gas/aarch64/sys-rt-reg.d: New testcase. opcodes/ PR target/20667 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's available.
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Jiong Wang
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@ -1,3 +1,10 @@
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2016-10-07 Jiong Wang <jiong.wang@arm.com>
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PR target/20667
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* testsuite/gas/aarch64/sys-rt-reg.s: Test source for instructions using
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SYS_Rt reg.
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* testsuite/gas/aarch64/sys-rt-reg.d: New testcase.
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2016-10-06 Claudiu Zissulescu <claziss@synopsys.com>
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* testsuite/gas/arc/leave_enter.d: New file.
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134
gas/testsuite/gas/aarch64/sys-rt-reg.d
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134
gas/testsuite/gas/aarch64/sys-rt-reg.d
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@ -0,0 +1,134 @@
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#objdump: -dr
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.*: file format .*
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Disassembly of section \.text:
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.* <.*>:
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.*: d508711f ic ialluis
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.*: d508751f ic iallu
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.*: d50b7520 ic ivau, x0
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.*: d50b7523 ic ivau, x3
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.*: d50b752f ic ivau, x15
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.*: d50b753a ic ivau, x26
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.*: d50b753f ic ivau, xzr
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.*: d508871f tlbi vmalle1
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.*: d508831f tlbi vmalle1is
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.*: d50c87df tlbi vmalls12e1
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.*: d50c83df tlbi vmalls12e1is
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.*: d50c871f tlbi alle2
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.*: d50c831f tlbi alle2is
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.*: d50c879f tlbi alle1
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.*: d50c839f tlbi alle1is
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.*: d50e871f tlbi alle3
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.*: d50e831f tlbi alle3is
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.*: d5088720 tlbi vae1, x0
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.*: d5088723 tlbi vae1, x3
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.*: d508872f tlbi vae1, x15
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.*: d508873a tlbi vae1, x26
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.*: d508873f tlbi vae1, xzr
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.*: d5088740 tlbi aside1, x0
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.*: d5088743 tlbi aside1, x3
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.*: d508874f tlbi aside1, x15
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.*: d508875a tlbi aside1, x26
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.*: d508875f tlbi aside1, xzr
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.*: d5088760 tlbi vaae1, x0
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.*: d5088763 tlbi vaae1, x3
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.*: d508876f tlbi vaae1, x15
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.*: d508877a tlbi vaae1, x26
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.*: d508877f tlbi vaae1, xzr
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.*: d5088320 tlbi vae1is, x0
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.*: d5088323 tlbi vae1is, x3
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.*: d508832f tlbi vae1is, x15
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.*: d508833a tlbi vae1is, x26
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.*: d508833f tlbi vae1is, xzr
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.*: d5088340 tlbi aside1is, x0
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.*: d5088343 tlbi aside1is, x3
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.*: d508834f tlbi aside1is, x15
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.*: d508835a tlbi aside1is, x26
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.*: d508835f tlbi aside1is, xzr
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.*: d5088360 tlbi vaae1is, x0
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.*: d5088363 tlbi vaae1is, x3
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.*: d508836f tlbi vaae1is, x15
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.*: d508837a tlbi vaae1is, x26
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.*: d508837f tlbi vaae1is, xzr
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.*: d50c8020 tlbi ipas2e1is, x0
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.*: d50c8023 tlbi ipas2e1is, x3
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.*: d50c802f tlbi ipas2e1is, x15
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.*: d50c803a tlbi ipas2e1is, x26
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.*: d50c803f tlbi ipas2e1is, xzr
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.*: d50c80a0 tlbi ipas2le1is, x0
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.*: d50c80a3 tlbi ipas2le1is, x3
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.*: d50c80af tlbi ipas2le1is, x15
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.*: d50c80ba tlbi ipas2le1is, x26
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.*: d50c80bf tlbi ipas2le1is, xzr
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.*: d50c8420 tlbi ipas2e1, x0
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.*: d50c8423 tlbi ipas2e1, x3
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.*: d50c842f tlbi ipas2e1, x15
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.*: d50c843a tlbi ipas2e1, x26
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.*: d50c843f tlbi ipas2e1, xzr
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.*: d50c84a0 tlbi ipas2le1, x0
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.*: d50c84a3 tlbi ipas2le1, x3
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.*: d50c84af tlbi ipas2le1, x15
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.*: d50c84ba tlbi ipas2le1, x26
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.*: d50c84bf tlbi ipas2le1, xzr
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.*: d50c8720 tlbi vae2, x0
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.*: d50c8723 tlbi vae2, x3
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.*: d50c872f tlbi vae2, x15
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.*: d50c873a tlbi vae2, x26
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.*: d50c873f tlbi vae2, xzr
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.*: d50c8320 tlbi vae2is, x0
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.*: d50c8323 tlbi vae2is, x3
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.*: d50c832f tlbi vae2is, x15
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.*: d50c833a tlbi vae2is, x26
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.*: d50c833f tlbi vae2is, xzr
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.*: d50e8720 tlbi vae3, x0
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.*: d50e8723 tlbi vae3, x3
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.*: d50e872f tlbi vae3, x15
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.*: d50e873a tlbi vae3, x26
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.*: d50e873f tlbi vae3, xzr
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.*: d50e8320 tlbi vae3is, x0
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.*: d50e8323 tlbi vae3is, x3
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.*: d50e832f tlbi vae3is, x15
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.*: d50e833a tlbi vae3is, x26
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.*: d50e833f tlbi vae3is, xzr
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.*: d50883a0 tlbi vale1is, x0
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.*: d50883a3 tlbi vale1is, x3
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.*: d50883af tlbi vale1is, x15
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.*: d50883ba tlbi vale1is, x26
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.*: d50883bf tlbi vale1is, xzr
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.*: d50c83a0 tlbi vale2is, x0
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.*: d50c83a3 tlbi vale2is, x3
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.*: d50c83af tlbi vale2is, x15
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.*: d50c83ba tlbi vale2is, x26
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.*: d50c83bf tlbi vale2is, xzr
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.*: d50e83a0 tlbi vale3is, x0
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.*: d50e83a3 tlbi vale3is, x3
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.*: d50e83af tlbi vale3is, x15
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.*: d50e83ba tlbi vale3is, x26
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.*: d50e83bf tlbi vale3is, xzr
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.*: d50883e0 tlbi vaale1is, x0
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.*: d50883e3 tlbi vaale1is, x3
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.*: d50883ef tlbi vaale1is, x15
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.*: d50883fa tlbi vaale1is, x26
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.*: d50883ff tlbi vaale1is, xzr
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.*: d50887a0 tlbi vale1, x0
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.*: d50887a3 tlbi vale1, x3
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.*: d50887af tlbi vale1, x15
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.*: d50887ba tlbi vale1, x26
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.*: d50887bf tlbi vale1, xzr
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.*: d50c87a0 tlbi vale2, x0
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.*: d50c87a3 tlbi vale2, x3
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.*: d50c87af tlbi vale2, x15
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.*: d50c87ba tlbi vale2, x26
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.*: d50c87bf tlbi vale2, xzr
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.*: d50e87a0 tlbi vale3, x0
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.*: d50e87a3 tlbi vale3, x3
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.*: d50e87af tlbi vale3, x15
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.*: d50e87ba tlbi vale3, x26
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.*: d50e87bf tlbi vale3, xzr
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.*: d50887e0 tlbi vaale1, x0
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.*: d50887e3 tlbi vaale1, x3
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.*: d50887ef tlbi vaale1, x15
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.*: d50887fa tlbi vaale1, x26
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.*: d50887ff tlbi vaale1, xzr
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21
gas/testsuite/gas/aarch64/sys-rt-reg.s
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21
gas/testsuite/gas/aarch64/sys-rt-reg.s
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@ -0,0 +1,21 @@
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// sys-rt-reg.s Test file for AArch64 instructions take SYS_Rt register.
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.text
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.irp ic_op, ialluis, iallu
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ic \ic_op
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.endr
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.irp rt, x0, x3, x15, x26, xzr
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ic ivau, \rt
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.endr
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.irp tlbi_op, vmalle1, vmalle1is, vmalls12e1, vmalls12e1is, alle2, alle2is, alle1, alle1is, alle3, alle3is
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tlbi \tlbi_op
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.endr
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.irp tlbi_op, vae1, aside1, vaae1, vae1is, aside1is, vaae1is, ipas2e1is, ipas2le1is, ipas2e1, ipas2le1, vae2, vae2is, vae3, vae3is, vale1is, vale2is, vale3is, vaale1is, vale1, vale2, vale3, vaale1
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.irp rt, x0, x3, x15, x26, xzr
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tlbi \tlbi_op, \rt
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.endr
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.endr
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@ -1,3 +1,9 @@
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2016-10-07 Jiong Wang <jiong.wang@arm.com>
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PR target/20667
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* aarch64-opc.c (aarch64_print_operand): Always print operand if it's
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available.
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2016-10-07 Alan Modra <amodra@gmail.com>
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* sh-opc.h (sh_merge_bfd_arch): Delete prototype.
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@ -2970,11 +2970,15 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
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/* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
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the <ic_op>, therefore we we use opnd->present to override the
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generic optional-ness information. */
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if (opnd->type == AARCH64_OPND_Rt_SYS && !opnd->present)
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break;
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if (opnd->type == AARCH64_OPND_Rt_SYS)
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{
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if (!opnd->present)
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break;
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}
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/* Omit the operand, e.g. RET. */
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if (optional_operand_p (opcode, idx)
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&& opnd->reg.regno == get_optional_operand_default_value (opcode))
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else if (optional_operand_p (opcode, idx)
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&& (opnd->reg.regno
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== get_optional_operand_default_value (opcode)))
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break;
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assert (opnd->qualifier == AARCH64_OPND_QLF_W
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|| opnd->qualifier == AARCH64_OPND_QLF_X);
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