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o Make tic80 insn file more `cache ready'
o Have igen always zero r0 instead of constantly checking if the designated register is r0.
This commit is contained in:
Andrew Cagney
parent
77bd8dfa1f
commit
37a684b84d
@ -1,3 +1,10 @@
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Fri May 16 11:48:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* gen-semantics.c (print_semantic_body): Add code to clear r0.
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* igen.c (main): Add new option zero-r0, which adds code to clear
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GPR(0) each cycle.
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Wed May 7 12:31:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* igen.c (print_itrace): Fix so line-nr is passed to trace
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@ -173,6 +173,15 @@ print_semantic_body(lf *file,
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/* FIXME - need to log a conditional failure */
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}
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/* Architecture expects r0 to be zero. Instead of having to check
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every read to see if it is refering to r0 just zap the r0
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register */
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if ((code & generate_with_semantic_delayed_branch))
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{
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lf_printf (file, "\n");
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lf_printf (file, "GPR(0) = 0;\n");
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}
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/* generate the code (or at least something */
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lf_printf(file, "\n");
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lf_printf(file, "/* semantics: */\n");
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@ -1,3 +1,20 @@
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Fri May 16 11:57:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* ic (compute): Drop check for REG == 0, now always forced to
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zero.
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* cpu.h (GPR_SET): New macro update the gpr.
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* insns (do_add): Use GPR_SET to update the GPR register.
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* sim-calls.c (sim_fetch_register): Pretend that r0 is zero.
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* Makefile.in (tmp-igen): Specify zero-r0 so that every
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instruction clears r0.
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* interp.c (engine_run_until_stop): Igen now generates code to
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clear r0.
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(engine_step): Ditto.
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Thu May 15 11:45:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* insns (do_shift): When rot==0 and zero/sign merge treat it as
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@ -92,6 +92,7 @@ tmp-igen: $(srcdir)/dc $(srcdir)/insns $(srcdir)/ic ../igen/igen
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-F f \
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-G direct-access \
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-G delayed-branch \
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-G zero-r0 \
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-F short,emul \
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-B 32 -H 31 \
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-o $(srcdir)/dc \
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@ -152,6 +152,7 @@ struct _sim_cpu {
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};
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#define GPR(N) ((CPU)->reg[N])
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#define GPR_SET(N, VAL) ((CPU)->reg[N] = (VAL))
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#define ACC(N) ((CPU)->acc[N])
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#define CR(N) ((CPU)->cr[tic80_index2cr ((N))])
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19
sim/tic80/ic
19
sim/tic80/ic
@ -2,19 +2,25 @@ compute:Dest:Dest:
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compute:Dest:rDest:signed_word *:(&(CPU)->reg[Dest])
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#
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compute:Source1:Source1:
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compute:Source1:rSource1:signed_word:(Source1 == 0 ? 0 : (CPU)->reg[Source1])
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compute:Source1:vSource1:signed_word:(GPR (Source1) + 0)
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#compute:Source1:vSource1:signed_word:(Source1 == 0 ? 0 : (CPU)->reg[Source1])
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#
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compute:Source2:Source2:
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compute:Source2:rSource2:signed_word:(Source2 == 0 ? 0 : (CPU)->reg[Source2])
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compute:Source2:vSource2:signed_word:(GPR (Source2) + 0)
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#compute:Source2:vSource2:signed_word:(Source2 == 0 ? 0 : (CPU)->reg[Source2])
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#
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compute:Source:Source:
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compute:Source:rSource:signed_word:(Source == 0 ? 0 : (CPU)->reg[Source])
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compute:Source:vSource:signed_word:(GPR (Source) + 0)
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#compute:Source:vSource:signed_word:(Source == 0 ? 0 : (CPU)->reg[Source])
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#
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compute:IndOff:IndOff:
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compute:IndOff:rIndOff:signed_word:(IndOff == 0 ? 0 : (CPU)->reg[IndOff])
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compute:IndOff:rIndOff:signed_word:(GPR (IndOff) + 0)
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#compute:IndOff:rIndOff:signed_word:(IndOff == 0 ? 0 : (CPU)->reg[IndOff])
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#
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compute:Base:Base:
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compute:Base:rBase:signed_word:(Base == 0 ? 0 : (CPU)->reg[Base])
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compute:Base:vBase:signed_word:(GPR (Base) + 0)
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compute:Base:rBase:signed_word:(&GPR (Base))
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#compute:Base:vBase:signed_word:(Base == 0 ? 0 : (CPU)->reg[Base])
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#
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compute:Link:Link:
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compute:Link:rLink:signed_word:(&(CPU)->reg[Link])
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@ -40,4 +46,5 @@ compute:SignedOffset:vSignedOffset:signed_word:SEXT (SignedOffset, 14)
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#
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compute:UCRN:UCRN:
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compute:INDCR:INDCR:
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compute:INDCR:UCRN:unsigned32:(INDCR == 0 ? 0 : (CPU)->reg[INDCR])
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compute:INDCR:UCRN:unsigned32:(GPR (INDCR) + 0)
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#compute:INDCR:UCRN:unsigned32:(INDCR == 0 ? 0 : (CPU)->reg[INDCR])
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332
sim/tic80/insns
332
sim/tic80/insns
@ -48,80 +48,82 @@ instruction_address::function::do_branch:int annul, address_word target, int rLi
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return nia;
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// Signed Integer Add - add source1, source2, dest
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void::function::do_add:signed32 *rDest, signed32 Source1, signed32 Source2
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ALU_BEGIN (Source1);
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ALU_ADD (Source2);
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ALU_END (*rDest);
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TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2);
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void::function::do_add:unsigned32 *rDest, signed32 source1, signed32 source2
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unsigned32 result;
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ALU_BEGIN (source1);
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ALU_ADD (source2);
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ALU_END (result);
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*rDest = result;
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TRACE_ALU3 (MY_INDEX, result, source1, source2);
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/* FIXME - a signed add may cause an exception */
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31.Dest,26.Source2,21.0b101100,15.0,14.SignedImmediate::::add i
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do_add (_SD, rDest, vSource1, rSource2);
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do_add (_SD, rDest, vSource1, vSource2);
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31.Dest,26.Source2,21.0b11101100,13.0,12.0,11./,4.Source1::::add r
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do_add (_SD, rDest, rSource1, rSource2);
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do_add (_SD, rDest, vSource1, vSource2);
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31.Dest,26.Source2,21.0b11101100,13.0,12.1,11./::::add l
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long_immediate (LongSignedImmediate);
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do_add (_SD, rDest, LongSignedImmediate, rSource2);
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do_add (_SD, rDest, LongSignedImmediate, vSource2);
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// Unsigned Integer Add - addu source1, source2, dest
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void::function::do_addu:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
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unsigned32 result = Source1 + Source2;
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TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
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void::function::do_addu:unsigned32 *rDest, unsigned32 source1, unsigned32 source2
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unsigned32 result = source1 + source2;
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TRACE_ALU3 (MY_INDEX, result, source1, source2);
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*rDest = result;
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31.Dest,26.Source2,21.0b101100,15.1,14.SignedImmediate::::addu i
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do_addu (_SD, rDest, vSource1, rSource2);
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do_addu (_SD, rDest, vSource1, vSource2);
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31.Dest,26.Source2,21.0b11101100,13.1,12.0,11./,4.Source1::::addu r
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do_addu (_SD, rDest, rSource1, rSource2);
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do_addu (_SD, rDest, vSource1, vSource2);
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31.Dest,26.Source2,21.0b11101100,13.1,12.1,11./::::addu l
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long_immediate (LongSignedImmediate);
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do_addu (_SD, rDest, LongSignedImmediate, rSource2);
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do_addu (_SD, rDest, LongSignedImmediate, vSource2);
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void::function::do_and:signed32 *rDest, signed32 Source1, signed32 Source2
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unsigned32 result = Source1 & Source2;
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TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
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void::function::do_and:signed32 *rDest, signed32 source1, signed32 source2
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unsigned32 result = source1 & source2;
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TRACE_ALU3 (MY_INDEX, result, source1, source2);
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*rDest = result;
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// and, and.tt
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31.Dest,26.Source2,21.0b0010001,14.UnsignedImmediate::::and.tt i
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do_and (_SD, rDest, vSource1, rSource2);
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do_and (_SD, rDest, vSource1, vSource2);
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31.Dest,26.Source2,21.0b110010001,12.0,11./,4.Source1::::and.tt r
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do_and (_SD, rDest, rSource1, rSource2);
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do_and (_SD, rDest, vSource1, vSource2);
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31.Dest,26.Source2,21.0b110010001,12.1,11./::::and.tt l
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long_immediate (LongSignedImmediate);
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do_and (_SD, rDest, LongSignedImmediate, rSource2);
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do_and (_SD, rDest, LongSignedImmediate, vSource2);
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// and.ff
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31.Dest,26.Source2,21.0b0011000,14.UnsignedImmediate::::and.ff i
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do_and (_SD, rDest, ~vSource1, ~rSource2);
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do_and (_SD, rDest, ~vSource1, ~vSource2);
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31.Dest,26.Source2,21.0b110011000,12.0,11./,4.Source1::::and.ff r
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do_and (_SD, rDest, ~rSource1, ~rSource2);
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do_and (_SD, rDest, ~vSource1, ~vSource2);
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31.Dest,26.Source2,21.0b110011000,12.1,11./::::and.ff l
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long_immediate (LongSignedImmediate);
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do_and (_SD, rDest, ~LongSignedImmediate, ~rSource2);
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do_and (_SD, rDest, ~LongSignedImmediate, ~vSource2);
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// and.ft
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31.Dest,26.Source2,21.0b0010100,14.UnsignedImmediate::::and.ft i
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do_and (_SD, rDest, ~vSource1, rSource2);
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do_and (_SD, rDest, ~vSource1, vSource2);
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31.Dest,26.Source2,21.0b110010100,12.0,11./,4.Source1::::and.ft r
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do_and (_SD, rDest, ~rSource1, rSource2);
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do_and (_SD, rDest, ~vSource1, vSource2);
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31.Dest,26.Source2,21.0b110010100,12.1,11./::::and.ft l
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long_immediate (LongSignedImmediate);
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do_and (_SD, rDest, ~LongSignedImmediate, rSource2);
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do_and (_SD, rDest, ~LongSignedImmediate, vSource2);
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// and.tf
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31.Dest,26.Source2,21.0b0010010,14.UnsignedImmediate::::and.tf i
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do_and (_SD, rDest, vSource1, ~rSource2);
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do_and (_SD, rDest, vSource1, ~vSource2);
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31.Dest,26.Source2,21.0b110010010,12.0,11./,4.Source1::::and.tf r
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do_and (_SD, rDest, rSource1, ~rSource2);
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do_and (_SD, rDest, vSource1, ~vSource2);
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31.Dest,26.Source2,21.0b110010010,12.1,11./::::and.tf l
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long_immediate (LongSignedImmediate);
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do_and (_SD, rDest, LongSignedImmediate, ~rSource2);
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do_and (_SD, rDest, LongSignedImmediate, ~vSource2);
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// bbo.[a]
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@ -139,12 +141,12 @@ instruction_address::function::do_bbo:instruction_address nia, int bitnum, unsig
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TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target);
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return nia;
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31.BITNUM,26.Source,21.0b100101,15.A,14.SignedOffset::::bbo i
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nia = do_bbo (_SD, nia, BITNUM, rSource, A, vSignedOffset);
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nia = do_bbo (_SD, nia, BITNUM, vSource, A, vSignedOffset);
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31.BITNUM,26.Source,21.0b11100101,13.A,12.0,11./,4.IndOff::::bbo r
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nia = do_bbo (_SD, nia, BITNUM, rSource, A, rIndOff);
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nia = do_bbo (_SD, nia, BITNUM, vSource, A, rIndOff);
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31.BITNUM,26.Source,21.0b11100101,13.A,12.1,11./::::bbo l
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long_immediate (LongSignedImmediate);
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nia = do_bbo (_SD, nia, BITNUM, rSource, A, LongSignedImmediate);
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nia = do_bbo (_SD, nia, BITNUM, vSource, A, LongSignedImmediate);
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// bbz[.a]
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@ -162,12 +164,12 @@ instruction_address::function::do_bbz:instruction_address nia, int bitnum, unsig
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TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target);
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return nia;
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31.BITNUM,26.Source,21.0b100100,15.A,14.SignedOffset::::bbz i
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nia = do_bbz (_SD, nia, BITNUM, rSource, A, vSignedOffset);
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nia = do_bbz (_SD, nia, BITNUM, vSource, A, vSignedOffset);
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31.BITNUM,26.Source,21.0b11100100,13.A,12.0,11./,4.IndOff::::bbz r
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nia = do_bbz (_SD, nia, BITNUM, rSource, A, rIndOff);
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nia = do_bbz (_SD, nia, BITNUM, vSource, A, rIndOff);
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31.BITNUM,26.Source,21.0b11100100,13.A,12.1,11./::::bbz l
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long_immediate (LongSignedImmediate);
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nia = do_bbz (_SD, nia, BITNUM, rSource, A, LongSignedImmediate);
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nia = do_bbz (_SD, nia, BITNUM, vSource, A, LongSignedImmediate);
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// bcnd[.a]
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@ -202,12 +204,12 @@ instruction_address::function::do_bcnd:instruction_address nia, int Cond, unsign
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TRACE_COND_BR(MY_INDEX, condition, source, target);
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return nia;
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31.Code,26.Source,21.0b100110,15.A,14.SignedOffset::::bcnd i
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nia = do_bcnd (_SD, nia, Code, rSource, A, vSignedOffset);
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nia = do_bcnd (_SD, nia, Code, vSource, A, vSignedOffset);
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31.Code,26.Source,21.0b11100110,13.A,12.0,11./,4.IndOff::::bcnd r
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nia = do_bcnd (_SD, nia, Code, rSource, A, rIndOff);
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nia = do_bcnd (_SD, nia, Code, vSource, A, rIndOff);
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31.Code,26.Source,21.0b11100110,13.A,12.1,11./::::bcnd l
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long_immediate (LongSignedImmediate);
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nia = do_bcnd (_SD, nia, Code, rSource, A, LongSignedImmediate);
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nia = do_bcnd (_SD, nia, Code, vSource, A, LongSignedImmediate);
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// br[.a] - see bbz[.a]
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@ -296,7 +298,7 @@ void::function::do_cmnd:signed32 source
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31./,21.0b0000010,14.UI::::cmnd i
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do_cmnd (_SD, UI);
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31./,21.0b110000010,12.0,11./,4.Source::::cmnd r
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do_cmnd (_SD, rSource);
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do_cmnd (_SD, vSource);
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31./,21.0b110000010,12.1,11./::::cmnd l
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long_immediate (LongUnsignedImmediate);
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do_cmnd (_SD, LongUnsignedImmediate);
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@ -315,22 +317,22 @@ unsigned32::function::cmp_vals:signed32 s1, unsigned32 u1, signed32 s2, unsigned
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if (u1 < u2) field |= 0x100;
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if (u1 >= u2) field |= 0x200;
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return field;
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void::function::do_cmp:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
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void::function::do_cmp:unsigned32 *rDest, unsigned32 source1, unsigned32 source2
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unsigned32 field = 0;
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field |= cmp_vals (_SD, Source1, Source1, Source2, Source2) << 20;
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field |= cmp_vals (_SD, (signed16)Source1, (unsigned16)Source1,
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(signed16)Source2, (unsigned16)Source2) << 10;
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field |= cmp_vals (_SD, (signed8)Source1, (unsigned8)Source1,
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(signed8)Source2, (unsigned8)Source2);
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TRACE_ALU3 (MY_INDEX, field, Source1, Source2);
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field |= cmp_vals (_SD, source1, source1, source2, source2) << 20;
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field |= cmp_vals (_SD, (signed16)source1, (unsigned16)source1,
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(signed16)source2, (unsigned16)source2) << 10;
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field |= cmp_vals (_SD, (signed8)source1, (unsigned8)source1,
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(signed8)source2, (unsigned8)source2);
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TRACE_ALU3 (MY_INDEX, field, source1, source2);
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*rDest = field;
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31.Dest,26.Source2,21.0b1010000,14.SignedImmediate::::cmp i
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do_cmp (_SD, rDest, vSource1, rSource2);
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do_cmp (_SD, rDest, vSource1, vSource2);
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31.Dest,26.Source2,21.0b111010000,12.0,11./,4.Source1::::cmp r
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do_cmp (_SD, rDest, rSource1, rSource2);
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do_cmp (_SD, rDest, vSource1, vSource2);
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31.Dest,26.Source2,21.0b111010000,12.1,11./::::cmp l
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long_immediate (LongSignedImmediate);
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do_cmp (_SD, rDest, LongSignedImmediate, rSource2);
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do_cmp (_SD, rDest, LongSignedImmediate, vSource2);
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// dcache
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@ -348,33 +350,33 @@ void::function::do_cmp:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
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// dld[{.b|.h|.d}]
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void::function::do_dld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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do_ld (_SD, Dest, Base, rBase, m, sz, S, Offset);
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void::function::do_dld:int Dest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
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do_ld (_SD, Dest, base, rBase, m, sz, S, offset);
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31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld r
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do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
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do_dld (_SD, Dest, vBase, rBase, m, sz, S, rIndOff);
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31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.1,9./::::dld l
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long_immediate (LongSignedImmediateOffset);
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do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
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do_dld (_SD, Dest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
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// dld.u[{.b|.h|.d}]
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void::function::do_dld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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do_ld_u (_SD, rDest, Base, rBase, m, sz, S, Offset);
|
||||
void::function::do_dld_u:unsigned32 *rDest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
|
||||
do_ld_u (_SD, rDest, base, rBase, m, sz, S, offset);
|
||||
31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld.u r
|
||||
do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
|
||||
do_dld_u (_SD, rDest, vBase, rBase, m, sz, S, rIndOff);
|
||||
31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.1,9./::::dld.u l
|
||||
long_immediate (LongSignedImmediateOffset);
|
||||
do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
|
||||
do_dld_u (_SD, rDest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
|
||||
|
||||
|
||||
// dst[{.b|.h|.d}]
|
||||
void::function::do_dst:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
|
||||
do_st (_SD, Source, Base, rBase, m, sz, S, Offset);
|
||||
void::function::do_dst:int Source, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
|
||||
do_st (_SD, Source, base, rBase, m, sz, S, offset);
|
||||
31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dst r
|
||||
do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
|
||||
do_dst (_SD, Source, vBase, rBase, m, sz, S, rIndOff);
|
||||
31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.1,9./::::dst l
|
||||
long_immediate (LongSignedImmediateOffset);
|
||||
do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
|
||||
do_dst (_SD, Source, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
|
||||
|
||||
|
||||
// estop
|
||||
@ -404,8 +406,8 @@ sim_fpu::function::get_fp_reg:int reg, unsigned32 val, int precision
|
||||
engine_error (SD, CPU, cia, "DP FP register must be even");
|
||||
if (reg <= 1)
|
||||
engine_error (SD, CPU, cia, "DP FP register must be >= 2");
|
||||
return sim_fpu_64to (INSERTED64 (GPR(reg + 1), 63, 32)
|
||||
| INSERTED64 (GPR(reg), 31, 0));
|
||||
return sim_fpu_64to (INSERTED64 (GPR (reg + 1), 63, 32)
|
||||
| INSERTED64 (GPR (reg), 31, 0));
|
||||
case 2: /* 32 bit signed integer */
|
||||
return sim_fpu_i32to (val);
|
||||
case 3: /* 32 bit unsigned integer */
|
||||
@ -454,17 +456,17 @@ void::function::do_fadd:int Dest, int PD, sim_fpu s1, sim_fpu s2
|
||||
set_fp_reg (_SD, Dest, ans, PD);
|
||||
31.Dest,26.Source2,21.0b111110000,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fadd r
|
||||
do_fadd (_SD, Dest, PD,
|
||||
get_fp_reg (_SD, Source1, rSource1, P1),
|
||||
get_fp_reg (_SD, Source2, rSource2, P2));
|
||||
get_fp_reg (_SD, Source1, vSource1, P1),
|
||||
get_fp_reg (_SD, Source2, vSource2, P2));
|
||||
31.Dest,26.Source2,21.0b111110000,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fadd l
|
||||
long_immediate (SinglePrecisionFloatingPoint);
|
||||
do_fadd (_SD, Dest, PD,
|
||||
get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
|
||||
get_fp_reg (_SD, Source2, rSource2, P2));
|
||||
get_fp_reg (_SD, Source2, vSource2, P2));
|
||||
|
||||
|
||||
// fcmp.{s|d}{s|d}{s|d}
|
||||
void::function::do_fcmp:int Dest, sim_fpu s1, sim_fpu s2
|
||||
void::function::do_fcmp:unsigned32 *rDest, sim_fpu s1, sim_fpu s2
|
||||
unsigned32 result = 0;
|
||||
if (sim_fpu_is_nan (s1) || sim_fpu_is_nan (s2))
|
||||
result |= BIT32 (30);
|
||||
@ -486,17 +488,17 @@ void::function::do_fcmp:int Dest, sim_fpu s1, sim_fpu s2
|
||||
if (sim_fpu_is_le (s1, sim_fpu_i32to (0))
|
||||
|| sim_fpu_is_ge (s1, s2)) result |= BIT32(29);
|
||||
}
|
||||
GPR (Dest) = result;
|
||||
*rDest = result;
|
||||
TRACE_FPU2I (MY_INDEX, result, s1, s2);
|
||||
31.Dest,26.Source2,21.0b111110101,12.0,11./,10.0,8.P2,6.P1,4.Source1::f::fcmp r
|
||||
do_fcmp (_SD, Dest,
|
||||
get_fp_reg (_SD, Source1, rSource1, P1),
|
||||
get_fp_reg (_SD, Source2, rSource2, P2));
|
||||
do_fcmp (_SD, rDest,
|
||||
get_fp_reg (_SD, Source1, vSource1, P1),
|
||||
get_fp_reg (_SD, Source2, vSource2, P2));
|
||||
31.Dest,26.Source2,21.0b111110101,12.1,11./,10.0,8.P2,6.P1,4./::f::fcmp l
|
||||
long_immediate (SinglePrecisionFloatingPoint);
|
||||
do_fcmp (_SD, Dest,
|
||||
do_fcmp (_SD, rDest,
|
||||
get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
|
||||
get_fp_reg (_SD, Source2, rSource2, P2));
|
||||
get_fp_reg (_SD, Source2, vSource2, P2));
|
||||
|
||||
|
||||
|
||||
@ -507,13 +509,13 @@ void::function::do_fdiv:int Dest, int PD, sim_fpu s1, sim_fpu s2
|
||||
set_fp_reg (_SD, Dest, ans, PD);
|
||||
31.Dest,26.Source2,21.0b111110011,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fdiv r
|
||||
do_fdiv (_SD, Dest, PD,
|
||||
get_fp_reg (_SD, Source1, rSource1, P1),
|
||||
get_fp_reg (_SD, Source2, rSource2, P2));
|
||||
get_fp_reg (_SD, Source1, vSource1, P1),
|
||||
get_fp_reg (_SD, Source2, vSource2, P2));
|
||||
31.Dest,26.Source2,21.0b111110011,12.1,11./,10.PD,8.P2,6.P1,4./::f::fdiv l
|
||||
long_immediate (SinglePrecisionFloatingPoint);
|
||||
do_fdiv (_SD, Dest, PD,
|
||||
get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
|
||||
get_fp_reg (_SD, Source2, rSource2, P2));
|
||||
get_fp_reg (_SD, Source2, vSource2, P2));
|
||||
|
||||
|
||||
// fmpy.{s|d|i|u}{s|d|i|u}{s|d|i|u}
|
||||
@ -541,13 +543,13 @@ void::function::do_fmpy:int Dest, int PD, sim_fpu s1, sim_fpu s2
|
||||
}
|
||||
31.Dest,26.Source2,21.0b111110010,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fmpy r
|
||||
do_fmpy (_SD, Dest, PD,
|
||||
get_fp_reg (_SD, Source1, rSource1, P1),
|
||||
get_fp_reg (_SD, Source2, rSource2, P2));
|
||||
get_fp_reg (_SD, Source1, vSource1, P1),
|
||||
get_fp_reg (_SD, Source2, vSource2, P2));
|
||||
31.Dest,26.Source2,21.0b111110010,12.1,11./,10.PD,8.P2,6.P1,4./::f::fmpy l
|
||||
long_immediate (SinglePrecisionFloatingPoint);
|
||||
do_fmpy (_SD, Dest, PD,
|
||||
get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
|
||||
get_fp_reg (_SD, Source2, rSource2, P2));
|
||||
get_fp_reg (_SD, Source2, vSource2, P2));
|
||||
|
||||
|
||||
// frndm.{s|d|i|u}{s|d|i|u}{s|d|i|u}
|
||||
@ -556,7 +558,7 @@ void::function::do_frnd:int Dest, int PD, sim_fpu s1
|
||||
TRACE_FPU1 (MY_INDEX, s1);
|
||||
31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b11,6.P1,4.Source::f::frndm r
|
||||
do_frnd (_SD, Dest, PD,
|
||||
get_fp_reg (_SD, Source, rSource, P1));
|
||||
get_fp_reg (_SD, Source, vSource, P1));
|
||||
31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b11,6.P1,4./::f::frndm l
|
||||
long_immediate (SinglePrecisionFloatingPoint);
|
||||
do_frnd (_SD, Dest, PD,
|
||||
@ -566,7 +568,7 @@ void::function::do_frnd:int Dest, int PD, sim_fpu s1
|
||||
// frndn.{s|d|i|u}{s|d|i|u}{s|d|i|u}
|
||||
31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b00,6.P1,4.Source::f::frndn r
|
||||
do_frnd (_SD, Dest, PD,
|
||||
get_fp_reg (_SD, Source, rSource, P1));
|
||||
get_fp_reg (_SD, Source, vSource, P1));
|
||||
31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b00,6.P1,4./::f::frndn l
|
||||
long_immediate (SinglePrecisionFloatingPoint);
|
||||
do_frnd (_SD, Dest, PD,
|
||||
@ -576,7 +578,7 @@ void::function::do_frnd:int Dest, int PD, sim_fpu s1
|
||||
// frndp.{s|d|i|u}{s|d|i|u}{s|d|i|u}
|
||||
31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b10,6.P1,4.Source::f::frndp r
|
||||
do_frnd (_SD, Dest, PD,
|
||||
get_fp_reg (_SD, Source, rSource, P1));
|
||||
get_fp_reg (_SD, Source, vSource, P1));
|
||||
31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b10,6.P1,4./::f::frndp l
|
||||
long_immediate (SinglePrecisionFloatingPoint);
|
||||
do_frnd (_SD, Dest, PD,
|
||||
@ -586,7 +588,7 @@ void::function::do_frnd:int Dest, int PD, sim_fpu s1
|
||||
// frndz.{s|d|i|u}{s|d|i|u}{s|d|i|u}
|
||||
31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b01,6.P1,4.Source::f::frndz r
|
||||
do_frnd (_SD, Dest, PD,
|
||||
get_fp_reg (_SD, Source, rSource, P1));
|
||||
get_fp_reg (_SD, Source, vSource, P1));
|
||||
31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b01,6.P1,4./::f::frndz l
|
||||
long_immediate (SinglePrecisionFloatingPoint);
|
||||
do_frnd (_SD, Dest, PD,
|
||||
@ -597,9 +599,9 @@ void::function::do_frnd:int Dest, int PD, sim_fpu s1
|
||||
#void::function::do_fsqrt:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
|
||||
# sim_io_error ("fsqrt");
|
||||
31.Dest,26.Source2,21.0b111110111,12.0,11./,10.PD,8.//,6.P1,4.Source1::f::fsqrt r
|
||||
# do_fsqrt (_SD, rDest, rSource1, rSource2);
|
||||
# do_fsqrt (_SD, rDest, vSource1, vSource2);
|
||||
31.Dest,26.Source2,21.0b111110111,12.1,11./,10.PD,8.//,6.P1,4./::f::fsqrt l
|
||||
# do_fsqrt (_SD, rDest, LongSignedImmediate, rSource2);
|
||||
# do_fsqrt (_SD, rDest, LongSignedImmediate, vSource2);
|
||||
|
||||
|
||||
// fsub.{s|d}{s|d}{s|d}
|
||||
@ -609,13 +611,13 @@ void::function::do_fsub:int Dest, int PD, sim_fpu s1, sim_fpu s2
|
||||
set_fp_reg (_SD, Dest, ans, PD);
|
||||
31.Dest,26.Source2,21.0b111110001,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fsub r
|
||||
do_fsub (_SD, Dest, PD,
|
||||
get_fp_reg (_SD, Source1, rSource1, P1),
|
||||
get_fp_reg (_SD, Source2, rSource2, P2));
|
||||
get_fp_reg (_SD, Source1, vSource1, P1),
|
||||
get_fp_reg (_SD, Source2, vSource2, P2));
|
||||
31.Dest,26.Source2,21.0b111110001,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fsub l
|
||||
long_immediate (SinglePrecisionFloatingPoint);
|
||||
do_fsub (_SD, Dest, PD,
|
||||
get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
|
||||
get_fp_reg (_SD, Source2, rSource2, P2));
|
||||
get_fp_reg (_SD, Source2, vSource2, P2));
|
||||
|
||||
|
||||
// illop
|
||||
@ -638,33 +640,33 @@ instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink,
|
||||
(unsigned long) nia.dp);
|
||||
return nia;
|
||||
31.Link,26.Base,21.0b100010,15.A,14.SignedOffset::::jsr i
|
||||
nia = do_jsr (_SD, nia, rLink, A, vSignedOffset, rBase);
|
||||
nia = do_jsr (_SD, nia, rLink, A, vSignedOffset, vBase);
|
||||
31.Link,26.Base,21.0b11100010,13.A,12.0,11./,4.Source1::::jsr r
|
||||
nia = do_jsr (_SD, nia, rLink, A, rSource1, rBase);
|
||||
nia = do_jsr (_SD, nia, rLink, A, vSource1, vBase);
|
||||
31.Link,26.Base,21.0b11100010,13.A,12.1,11./::::jsr l
|
||||
long_immediate (LongSignedImmediate);
|
||||
nia = do_jsr (_SD, nia, rLink, A, LongSignedImmediate, rBase);
|
||||
nia = do_jsr (_SD, nia, rLink, A, LongSignedImmediate, vBase);
|
||||
|
||||
|
||||
// ld[{.b.h.d}]
|
||||
void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
|
||||
void::function::do_ld:int Dest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
|
||||
unsigned32 addr;
|
||||
switch (sz)
|
||||
{
|
||||
case 0:
|
||||
addr = Base + (S ? (Offset << 0) : Offset);
|
||||
addr = base + (S ? (offset << 0) : offset);
|
||||
if (m)
|
||||
*rBase = addr;
|
||||
GPR(Dest) = MEM (signed, addr, 1);
|
||||
break;
|
||||
case 1:
|
||||
addr = Base + (S ? (Offset << 1) : Offset);
|
||||
addr = base + (S ? (offset << 1) : offset);
|
||||
if (m)
|
||||
*rBase = addr;
|
||||
GPR(Dest) = MEM (signed, addr, 2);
|
||||
break;
|
||||
case 2:
|
||||
addr = Base + (S ? (Offset << 2) : Offset);
|
||||
addr = base + (S ? (offset << 2) : offset);
|
||||
if (m)
|
||||
*rBase = addr;
|
||||
GPR(Dest) = MEM (signed, addr, 4);
|
||||
@ -675,7 +677,7 @@ void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int
|
||||
if (Dest & 0x1)
|
||||
engine_error (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
|
||||
cia.ip, Dest);
|
||||
addr = Base + (S ? (Offset << 3) : Offset);
|
||||
addr = base + (S ? (offset << 3) : offset);
|
||||
if (m)
|
||||
*rBase = addr;
|
||||
val = MEM (signed, addr, 8);
|
||||
@ -687,27 +689,27 @@ void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int
|
||||
addr = -1;
|
||||
engine_error (SD, CPU, cia, "ld - invalid sz %d", sz);
|
||||
}
|
||||
TRACE_LD (MY_INDEX, GPR(Dest), m, S, Base, Offset);
|
||||
TRACE_LD (MY_INDEX, GPR(Dest), m, S, base, offset);
|
||||
31.Dest,26.Base,21.0b0100,17.m,16.sz,14.SignedOffset::::ld i
|
||||
do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
|
||||
do_ld (_SD, Dest, vBase, rBase, m, sz, 0, vSignedOffset);
|
||||
31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld r
|
||||
do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
|
||||
do_ld (_SD, Dest, vBase, rBase, m, sz, S, rIndOff);
|
||||
31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.0,9./::::ld l
|
||||
long_immediate (LongSignedImmediateOffset);
|
||||
do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
|
||||
do_ld (_SD, Dest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
|
||||
|
||||
|
||||
// ld.u[{.b.h.d}]
|
||||
void::function::do_ld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
|
||||
void::function::do_ld_u:unsigned32 *rDest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
|
||||
unsigned32 addr;
|
||||
switch (sz)
|
||||
{
|
||||
case 0:
|
||||
addr = Base + (S ? (Offset << 0) : Offset);
|
||||
addr = base + (S ? (offset << 0) : offset);
|
||||
*rDest = MEM (unsigned, addr, 1);
|
||||
break;
|
||||
case 1:
|
||||
addr = Base + (S ? (Offset << 1) : Offset);
|
||||
addr = base + (S ? (offset << 1) : offset);
|
||||
*rDest = MEM (unsigned, addr, 2);
|
||||
break;
|
||||
default:
|
||||
@ -716,23 +718,23 @@ void::function::do_ld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, i
|
||||
}
|
||||
if (m)
|
||||
*rBase = addr;
|
||||
TRACE_LD (MY_INDEX, m, S, *rDest, Base, Offset);
|
||||
TRACE_LD (MY_INDEX, m, S, *rDest, base, offset);
|
||||
31.Dest,26.Base,21.0b0101,17.m,16.sz,14.SignedOffset::::ld.u i
|
||||
do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
|
||||
do_ld_u (_SD, rDest, vBase, rBase, m, sz, 0, vSignedOffset);
|
||||
31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld.u r
|
||||
do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
|
||||
do_ld_u (_SD, rDest, vBase, rBase, m, sz, S, rIndOff);
|
||||
31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.0,9./::::ld.u l
|
||||
long_immediate (LongSignedImmediateOffset);
|
||||
do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
|
||||
do_ld_u (_SD, rDest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
|
||||
|
||||
|
||||
// lmo
|
||||
31.Dest,26.Source,21.0b111111000,12.0,11./::::lmo
|
||||
int b;
|
||||
for (b = 0; b < 32; b++)
|
||||
if (rSource & BIT32 (31 - b))
|
||||
if (vSource & BIT32 (31 - b))
|
||||
break;
|
||||
TRACE_ALU2 (MY_INDEX, b, rSource);
|
||||
TRACE_ALU2 (MY_INDEX, b, vSource);
|
||||
*rDest = b;
|
||||
|
||||
|
||||
@ -747,42 +749,42 @@ void::function::do_or:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
|
||||
|
||||
// or, or.tt
|
||||
31.Dest,26.Source2,21.0b0010111,14.UnsignedImmediate::::or.tt i
|
||||
do_or (_SD, rDest, vSource1, rSource2);
|
||||
do_or (_SD, rDest, vSource1, vSource2);
|
||||
31.Dest,26.Source2,21.0b110010111,12.0,11./,4.Source1::::or.tt r
|
||||
do_or (_SD, rDest, rSource1, rSource2);
|
||||
do_or (_SD, rDest, vSource1, vSource2);
|
||||
31.Dest,26.Source2,21.0b110010111,12.1,11./::::or.tt l
|
||||
long_immediate (LongUnsignedImmediate);
|
||||
do_or (_SD, rDest, LongUnsignedImmediate, rSource2);
|
||||
do_or (_SD, rDest, LongUnsignedImmediate, vSource2);
|
||||
|
||||
|
||||
// or.ff
|
||||
31.Dest,26.Source2,21.0b0011110,14.UnsignedImmediate::::or.ff i
|
||||
do_or (_SD, rDest, ~vSource1, ~rSource2);
|
||||
do_or (_SD, rDest, ~vSource1, ~vSource2);
|
||||
31.Dest,26.Source2,21.0b110011110,12.0,11./,4.Source1::::or.ff r
|
||||
do_or (_SD, rDest, ~rSource1, ~rSource2);
|
||||
do_or (_SD, rDest, ~vSource1, ~vSource2);
|
||||
31.Dest,26.Source2,21.0b110011110,12.1,11./::::or.ff l
|
||||
long_immediate (LongUnsignedImmediate);
|
||||
do_or (_SD, rDest, ~LongUnsignedImmediate, ~rSource2);
|
||||
do_or (_SD, rDest, ~LongUnsignedImmediate, ~vSource2);
|
||||
|
||||
|
||||
// or.ft
|
||||
31.Dest,26.Source2,21.0b0011101,14.UnsignedImmediate::::or.ft i
|
||||
do_or (_SD, rDest, ~vSource1, rSource2);
|
||||
do_or (_SD, rDest, ~vSource1, vSource2);
|
||||
31.Dest,26.Source2,21.0b110011101,12.0,11./,4.Source1::::or.ft r
|
||||
do_or (_SD, rDest, ~rSource1, rSource2);
|
||||
do_or (_SD, rDest, ~vSource1, vSource2);
|
||||
31.Dest,26.Source2,21.0b110011101,12.1,11./::::or.ft l
|
||||
long_immediate (LongUnsignedImmediate);
|
||||
do_or (_SD, rDest, ~LongUnsignedImmediate, rSource2);
|
||||
do_or (_SD, rDest, ~LongUnsignedImmediate, vSource2);
|
||||
|
||||
|
||||
// or.tf
|
||||
31.Dest,26.Source2,21.0b0011011,14.UnsignedImmediate::::or.tf i
|
||||
do_or (_SD, rDest, vSource1, ~rSource2);
|
||||
do_or (_SD, rDest, vSource1, ~vSource2);
|
||||
31.Dest,26.Source2,21.0b110011011,12.0,11./,4.Source1::::or.tf r
|
||||
do_or (_SD, rDest, rSource1, ~rSource2);
|
||||
do_or (_SD, rDest, vSource1, ~vSource2);
|
||||
31.Dest,26.Source2,21.0b110011011,12.1,11./::::or.tf l
|
||||
long_immediate (LongUnsignedImmediate);
|
||||
do_or (_SD, rDest, LongUnsignedImmediate, ~rSource2);
|
||||
do_or (_SD, rDest, LongUnsignedImmediate, ~vSource2);
|
||||
|
||||
|
||||
// rdcr
|
||||
@ -802,11 +804,11 @@ void::function::do_rdcr:unsigned32 Dest, int cr
|
||||
31.Dest,26.Source,21.0b111111001,12.0,11./::::rmo
|
||||
int b;
|
||||
for (b = 0; b < 32; b++)
|
||||
if (rSource & BIT32 (b))
|
||||
if (vSource & BIT32 (b))
|
||||
break;
|
||||
if (b < 32)
|
||||
b = 31 - b;
|
||||
TRACE_ALU2 (MY_INDEX, b, rSource);
|
||||
TRACE_ALU2 (MY_INDEX, b, vSource);
|
||||
*rDest = b;
|
||||
|
||||
|
||||
@ -820,9 +822,9 @@ void::function::do_rdcr:unsigned32 Dest, int cr
|
||||
|
||||
|
||||
// sl.{d|e|i}{m|s|z}
|
||||
void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndMask, int Rotate
|
||||
void::function::do_shift:int Dest, unsigned32 source, int Merge, int i, int n, int EndMask, int Rotate
|
||||
/* see 10-30 for a reasonable description */
|
||||
unsigned32 input = GPR (Source);
|
||||
unsigned32 input = source;
|
||||
unsigned32 rotated;
|
||||
unsigned32 endmask;
|
||||
unsigned32 shiftmask;
|
||||
@ -831,12 +833,12 @@ void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndM
|
||||
/* rotate the source */
|
||||
if (n)
|
||||
{
|
||||
rotated = ROTR32 (GPR (Source), Rotate);
|
||||
rotated = ROTR32 (source, Rotate);
|
||||
nRotate = (- Rotate) & 31;
|
||||
}
|
||||
else
|
||||
{
|
||||
rotated = ROTL32 (GPR (Source), Rotate);
|
||||
rotated = ROTL32 (source, Rotate);
|
||||
nRotate = Rotate;
|
||||
}
|
||||
/* form the end mask */
|
||||
@ -867,7 +869,7 @@ void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndM
|
||||
default:
|
||||
engine_error (SD, CPU, cia,
|
||||
"0x%lx: Invalid merge (%d) for shift",
|
||||
cia.ip, Source);
|
||||
cia.ip, source);
|
||||
shiftmask = 0;
|
||||
}
|
||||
/* and the composite mask */
|
||||
@ -894,14 +896,14 @@ void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndM
|
||||
default:
|
||||
engine_error (SD, CPU, cia,
|
||||
"0x%lx: Invalid merge (%d)",
|
||||
cia.ip, Source);
|
||||
cia.ip, source);
|
||||
|
||||
}
|
||||
TRACE_SHIFT (MY_INDEX, GPR (Dest), input, i, n, Merge, EndMask, Rotate);
|
||||
31.Dest,26.Source,21.0b0001,17.Merge,14./,11.i,10.n,9.EndMask,4.Rotate::::sl i
|
||||
do_shift (_SD, Dest, Source, Merge, i, n, EndMask, Rotate);
|
||||
do_shift (_SD, Dest, vSource, Merge, i, n, EndMask, Rotate);
|
||||
31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.i,10.n,9.EndMask,4.RotReg::::sl r
|
||||
do_shift (_SD, Dest, Source, Merge, i, n, EndMask, GPR (RotReg) & 31);
|
||||
do_shift (_SD, Dest, vSource, Merge, i, n, EndMask, GPR (RotReg) & 31);
|
||||
|
||||
|
||||
// sli.{d|e|i}{m|s|z} - see shift
|
||||
@ -920,20 +922,20 @@ void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndM
|
||||
|
||||
|
||||
// st[{.b|.h|.d}]
|
||||
void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
|
||||
void::function::do_st:int Source, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
|
||||
unsigned32 addr;
|
||||
switch (sz)
|
||||
{
|
||||
case 0:
|
||||
addr = Base + (S ? (Offset << 0) : Offset);
|
||||
addr = base + (S ? (offset << 0) : offset);
|
||||
STORE (addr, 1, GPR(Source));
|
||||
break;
|
||||
case 1:
|
||||
addr = Base + (S ? (Offset << 1) : Offset);
|
||||
addr = base + (S ? (offset << 1) : offset);
|
||||
STORE (addr, 2, GPR(Source));
|
||||
break;
|
||||
case 2:
|
||||
addr = Base + (S ? (Offset << 2) : Offset);
|
||||
addr = base + (S ? (offset << 2) : offset);
|
||||
STORE (addr, 4, GPR(Source));
|
||||
break;
|
||||
case 3:
|
||||
@ -943,7 +945,7 @@ void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , in
|
||||
engine_error (SD, CPU, cia,
|
||||
"0x%lx: st.d with odd source register %d",
|
||||
cia.ip, Source);
|
||||
addr = Base + (S ? (Offset << 3) : Offset);
|
||||
addr = base + (S ? (offset << 3) : offset);
|
||||
val = (V4_H8 (GPR(Source + 1)) | V4_L8 (GPR(Source)));
|
||||
STORE (addr, 8, val);
|
||||
}
|
||||
@ -954,14 +956,14 @@ void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , in
|
||||
}
|
||||
if (m)
|
||||
*rBase = addr;
|
||||
TRACE_ST (MY_INDEX, Source, m, S, Base, Offset);
|
||||
TRACE_ST (MY_INDEX, Source, m, S, base, offset);
|
||||
31.Source,26.Base,21.0b0110,17.m,16.sz,14.SignedOffset::::st i
|
||||
do_st (_SD, Source, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
|
||||
do_st (_SD, Source, vBase, rBase, m, sz, 0, vSignedOffset);
|
||||
31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::st r
|
||||
do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
|
||||
do_st (_SD, Source, vBase, rBase, m, sz, S, rIndOff);
|
||||
31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.0,9./::::st l
|
||||
long_immediate (LongSignedImmediateOffset);
|
||||
do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
|
||||
do_st (_SD, Source, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
|
||||
|
||||
|
||||
// sub
|
||||
@ -971,12 +973,12 @@ void::function::do_sub:signed32 *rDest, signed32 Source1, signed32 Source2
|
||||
ALU_END (*rDest);
|
||||
TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2);
|
||||
31.Dest,26.Source2,21.0b101101,15.0,14.SignedImmediate::::sub i
|
||||
do_sub (_SD, rDest, vSource1, rSource2);
|
||||
do_sub (_SD, rDest, vSource1, vSource2);
|
||||
31.Dest,26.Source2,21.0b11101101,13.0,12.0,11./,4.Source1::::sub r
|
||||
do_sub (_SD, rDest, rSource1, rSource2);
|
||||
do_sub (_SD, rDest, vSource1, vSource2);
|
||||
31.Dest,26.Source2,21.0b11101101,13.0,12.1,11./::::sub l
|
||||
long_immediate (LongSignedImmediate);
|
||||
do_sub (_SD, rDest, LongSignedImmediate, rSource2);
|
||||
do_sub (_SD, rDest, LongSignedImmediate, vSource2);
|
||||
|
||||
|
||||
// subu
|
||||
@ -986,16 +988,16 @@ void::function::do_subu:unsigned32 *rDest, unsigned32 Source1, signed32 Source2
|
||||
*rDest = result;
|
||||
// NOTE - the book has 15.1 which conflicts with subu.
|
||||
31.Dest,26.Source2,21.0b101101,15.1,14.UnsignedImmediate::::subu i
|
||||
do_subu (_SD, rDest, vSource1, rSource2);
|
||||
do_subu (_SD, rDest, vSource1, vSource2);
|
||||
31.Dest,26.Source2,21.0b11101101,13.1,12.0,11./,4.Source1::::subu r
|
||||
do_subu (_SD, rDest, rSource1, rSource2);
|
||||
do_subu (_SD, rDest, vSource1, vSource2);
|
||||
31.Dest,26.Source2,21.0b11101101,13.1,12.1,11./::::subu l
|
||||
long_immediate (LongSignedImmediate);
|
||||
do_subu (_SD, rDest, LongSignedImmediate, rSource2);
|
||||
do_subu (_SD, rDest, LongSignedImmediate, vSource2);
|
||||
|
||||
|
||||
// swcr
|
||||
void::function::do_swcr:int Dest, signed32 rSource, signed32 cr
|
||||
void::function::do_swcr:int Dest, signed32 source, signed32 cr
|
||||
tic80_control_regs reg = tic80_index2cr (cr);
|
||||
/* cache the old CR value */
|
||||
unsigned32 old_cr = CR (cr);
|
||||
@ -1004,22 +1006,22 @@ void::function::do_swcr:int Dest, signed32 rSource, signed32 cr
|
||||
switch (reg)
|
||||
{
|
||||
case INTPEN_CR:
|
||||
CR (cr) &= ~rSource;
|
||||
CR (cr) &= ~source;
|
||||
break;
|
||||
default:
|
||||
CR (cr) = rSource;
|
||||
CR (cr) = source;
|
||||
break;
|
||||
}
|
||||
/* Finish off the read */
|
||||
GPR (Dest) = old_cr;
|
||||
TRACE_SINK3 (MY_INDEX, rSource, cr, Dest);
|
||||
TRACE_SINK3 (MY_INDEX, source, cr, Dest);
|
||||
31.Dest,26.Source,21.0b000010,15.1,14.UCRN::::swcr i
|
||||
do_swcr (_SD, Dest, rSource, UCRN);
|
||||
do_swcr (_SD, Dest, vSource, UCRN);
|
||||
31.Dest,26.Source,21.0b11000010,13.1,12.0,11./,4.INDCR::::swcr r
|
||||
do_swcr (_SD, Dest, rSource, UCRN);
|
||||
do_swcr (_SD, Dest, vSource, UCRN);
|
||||
31.Dest,26.Source,21.0b11000010,13.1,12.1,11./::::swcr l
|
||||
long_immediate (LongUnsignedControlRegister);
|
||||
do_swcr (_SD, Dest, rSource, LongUnsignedControlRegister);
|
||||
do_swcr (_SD, Dest, vSource, LongUnsignedControlRegister);
|
||||
|
||||
|
||||
// trap
|
||||
@ -1163,28 +1165,28 @@ void::function::do_trap:unsigned32 trap_number
|
||||
|
||||
|
||||
// xnor
|
||||
void::function::do_xnor:signed32 *rDest, signed32 Source1, signed32 Source2
|
||||
unsigned32 result = ~ (Source1 ^ Source2);
|
||||
TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
|
||||
void::function::do_xnor:signed32 *rDest, signed32 source1, signed32 source2
|
||||
unsigned32 result = ~ (source1 ^ source2);
|
||||
TRACE_ALU3 (MY_INDEX, result, source1, source2);
|
||||
*rDest = result;
|
||||
31.Dest,26.Source2,21.0b0011001,14.UnsignedImmediate::::xnor i
|
||||
do_xnor (_SD, rDest, vSource1, rSource2);
|
||||
do_xnor (_SD, rDest, vSource1, vSource2);
|
||||
31.Dest,26.Source2,21.0b110011001,12.0,11./,4.Source1::::xnor r
|
||||
do_xnor (_SD, rDest, rSource1, rSource2);
|
||||
do_xnor (_SD, rDest, vSource1, vSource2);
|
||||
31.Dest,26.Source2,21.0b110011001,12.1,11./::::xnor l
|
||||
long_immediate (LongUnsignedImmediate);
|
||||
do_xnor (_SD, rDest, LongUnsignedImmediate, rSource2);
|
||||
do_xnor (_SD, rDest, LongUnsignedImmediate, vSource2);
|
||||
|
||||
|
||||
// xor
|
||||
void::function::do_xor:signed32 *rDest, signed32 Source1, signed32 Source2
|
||||
unsigned32 result = Source1 ^ Source2;
|
||||
TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
|
||||
void::function::do_xor:signed32 *rDest, signed32 source1, signed32 source2
|
||||
unsigned32 result = source1 ^ source2;
|
||||
TRACE_ALU3 (MY_INDEX, result, source1, source2);
|
||||
*rDest = result;
|
||||
31.Dest,26.Source2,21.0b0010110,14.UnsignedImmediate::::xor i
|
||||
do_xor (_SD, rDest, vSource1, rSource2);
|
||||
do_xor (_SD, rDest, vSource1, vSource2);
|
||||
31.Dest,26.Source2,21.0b110010110,12.0,11./,4.Source1::::xor r
|
||||
do_xor (_SD, rDest, rSource1, rSource2);
|
||||
do_xor (_SD, rDest, vSource1, vSource2);
|
||||
31.Dest,26.Source2,21.0b110010110,12.1,11./::::xor l
|
||||
long_immediate (LongUnsignedImmediate);
|
||||
do_xor (_SD, rDest, LongUnsignedImmediate, rSource2);
|
||||
do_xor (_SD, rDest, LongUnsignedImmediate, vSource2);
|
||||
|
||||
@ -114,7 +114,6 @@ engine_run_until_stop (SIM_DESC sd,
|
||||
do
|
||||
{
|
||||
instruction_word insn = IMEM (cia);
|
||||
cpu->reg[0] = 0; /* force r0 to always contain 0 */
|
||||
cia = idecode_issue (sd, insn, cia);
|
||||
}
|
||||
while (*keep_running);
|
||||
@ -136,7 +135,6 @@ engine_step (SIM_DESC sd)
|
||||
sd->restart_ok = 1;
|
||||
cia = cpu->cia;
|
||||
insn = IMEM (cia);
|
||||
cpu->reg[0] = 0; /* force r0 to always contain 0 */
|
||||
cia = idecode_issue (sd, insn, cia);
|
||||
engine_halt (sd, cpu, cia, sim_stopped, SIGTRAP);
|
||||
}
|
||||
|
||||
@ -177,7 +177,9 @@ sim_write (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
|
||||
void
|
||||
sim_fetch_register (SIM_DESC sd, int regnr, unsigned char *buf)
|
||||
{
|
||||
if (regnr >= R0_REGNUM && regnr <= Rn_REGNUM)
|
||||
if (regnr == R0_REGNUM)
|
||||
memset (buf, 0, sizeof (unsigned32));
|
||||
else if (regnr > R0_REGNUM && regnr <= Rn_REGNUM)
|
||||
*(unsigned32*)buf = H2T_4 (STATE_CPU (sd, 0)->reg[regnr - R0_REGNUM]);
|
||||
else if (regnr == PC_REGNUM)
|
||||
*(unsigned32*)buf = H2T_4 (STATE_CPU (sd, 0)->cia.ip);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user