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https://github.com/darlinghq/darling-gdb.git
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2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros. (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac) (fp_inv_sqrt, fpu_format_name): Add paired-single support. (convert): Note that this function is not used for paired-single format conversions. (ps_lower, ps_upper, pack_ps, convert_ps): New functions. * mips.igen (FMT, MOVtf.fmt): Add paired-single support. (check_fmt_p): Enable paired-single support. (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS) (PUU.PS): New instructions. (CVT.S.fmt): Don't use this instruction for paired-single format destinations. * sim-main.h (FP_formats): New value 'fmt_ps.' (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes. (PSLower, PSUpper, PackPS, ConvertPS): New macros.
This commit is contained in:
Chris Demetriou
parent
2ac5a64a8e
commit
3a2b820ef3
@ -1,3 +1,21 @@
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2002-06-13 Chris Demetriou <cgd@broadcom.com>
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* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
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(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
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(fp_inv_sqrt, fpu_format_name): Add paired-single support.
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(convert): Note that this function is not used for paired-single
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format conversions.
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(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
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* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
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(check_fmt_p): Enable paired-single support.
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(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
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(PUU.PS): New instructions.
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(CVT.S.fmt): Don't use this instruction for paired-single format
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destinations.
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* sim-main.h (FP_formats): New value 'fmt_ps.'
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(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
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(PSLower, PSUpper, PackPS, ConvertPS): New macros.
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2002-06-12 Chris Demetriou <cgd@broadcom.com>
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* mips.igen: Fix formatting of function calls in
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209
sim/mips/cp1.c
209
sim/mips/cp1.c
@ -71,13 +71,28 @@ with this program; if not, write to the Free Software Foundation, Inc.,
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siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
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s = 1bit = sign
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i = 63bits = integer
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PAIRED SINGLE precision floating:
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seeeeeeeefffffffffffffffffffffffseeeeeeeefffffffffffffffffffffff
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| upper || lower |
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s = 1bit = sign
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e = 8bits = exponent
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f = 23bits = fraction
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Note: upper = [63..32], lower = [31..0]
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*/
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/* Extract packed single values: */
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#define FP_PS_upper(v) (((v) >> 32) & (unsigned)0xFFFFFFFF)
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#define FP_PS_lower(v) ((v) & (unsigned)0xFFFFFFFF)
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#define FP_PS_cat(u,l) (((unsigned64)((u) & (unsigned)0xFFFFFFFF) << 32) \
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| (unsigned64)((l) & 0xFFFFFFFF))
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/* Explicit QNaN values. */
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#define FPQNaN_SINGLE (0x7FBFFFFF)
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#define FPQNaN_WORD (0x7FFFFFFF)
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#define FPQNaN_DOUBLE (UNSIGNED64 (0x7FF7FFFFFFFFFFFF))
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#define FPQNaN_LONG (UNSIGNED64 (0x7FFFFFFFFFFFFFFF))
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#define FPQNaN_PS (FP_PS_cat (FPQNaN_SINGLE, FPQNaN_SINGLE))
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static const char *fpu_format_name (FP_formats fmt);
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#ifdef DEBUG
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@ -131,6 +146,7 @@ value_fpr (sim_cpu *cpu,
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case fmt_double: value = FPQNaN_DOUBLE; break;
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case fmt_word: value = FPQNaN_WORD; break;
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case fmt_long: value = FPQNaN_LONG; break;
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case fmt_ps: value = FPQNaN_PS; break;
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default: err = -1; break;
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}
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}
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@ -146,6 +162,7 @@ value_fpr (sim_cpu *cpu,
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case fmt_uninterpreted:
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case fmt_double:
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case fmt_long:
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case fmt_ps:
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value = FGR[fpr];
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break;
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@ -183,6 +200,10 @@ value_fpr (sim_cpu *cpu,
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}
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break;
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case fmt_ps:
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SignalException (ReservedInstruction, 0);
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break;
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default:
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err = -1;
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break;
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@ -237,6 +258,7 @@ store_fpr (sim_cpu *cpu,
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case fmt_uninterpreted:
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case fmt_double:
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case fmt_long:
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case fmt_ps:
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FGR[fpr] = value;
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FPR_STATE[fpr] = fmt;
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break;
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@ -280,6 +302,11 @@ store_fpr (sim_cpu *cpu,
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}
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break;
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case fmt_ps:
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FPR_STATE[fpr] = fmt_unknown;
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SignalException (ReservedInstruction, 0);
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break;
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default:
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FPR_STATE[fpr] = fmt_unknown;
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err = -1;
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@ -567,6 +594,18 @@ fp_cmp(sim_cpu *cpu,
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SETFCC (cc, result);
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break;
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}
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case fmt_ps:
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{
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int result0, result1;
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status = fp_test(FP_PS_lower (op1), FP_PS_lower (op2), fmt_single,
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abs, cond, &result0);
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status |= fp_test(FP_PS_upper (op1), FP_PS_upper (op2), fmt_single,
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abs, cond, &result1);
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update_fcsr (cpu, cia, status);
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SETFCC (cc, result0);
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SETFCC (cc+1, result1);
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break;
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}
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default:
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sim_io_eprintf (SD, "Bad switch\n");
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abort ();
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@ -613,6 +652,20 @@ fp_unary(sim_cpu *cpu,
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result = res;
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break;
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}
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case fmt_ps:
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{
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int status_u = 0, status_l = 0;
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unsigned32 res_u, res_l;
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sim_fpu_32to (&wop, FP_PS_upper(op));
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status_u |= (*sim_fpu_op) (&ans, &wop);
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sim_fpu_to32 (&res_u, &ans);
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sim_fpu_32to (&wop, FP_PS_lower(op));
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status_l |= (*sim_fpu_op) (&ans, &wop);
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sim_fpu_to32 (&res_l, &ans);
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result = FP_PS_cat(res_u, res_l);
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status = status_u | status_l;
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break;
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}
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default:
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sim_io_eprintf (SD, "Bad switch\n");
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abort ();
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@ -663,6 +716,22 @@ fp_binary(sim_cpu *cpu,
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result = res;
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break;
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}
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case fmt_ps:
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{
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int status_u = 0, status_l = 0;
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unsigned32 res_u, res_l;
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sim_fpu_32to (&wop1, FP_PS_upper(op1));
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sim_fpu_32to (&wop2, FP_PS_upper(op2));
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status_u |= (*sim_fpu_op) (&ans, &wop1, &wop2);
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sim_fpu_to32 (&res_u, &ans);
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sim_fpu_32to (&wop1, FP_PS_lower(op1));
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sim_fpu_32to (&wop2, FP_PS_lower(op2));
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status_l |= (*sim_fpu_op) (&ans, &wop1, &wop2);
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sim_fpu_to32 (&res_l, &ans);
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result = FP_PS_cat(res_u, res_l);
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status = status_u | status_l;
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break;
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}
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default:
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sim_io_eprintf (SD, "Bad switch\n");
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abort ();
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@ -784,6 +853,20 @@ fp_mac(sim_cpu *cpu,
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status = inner_mac(sim_fpu_op, op1, op2, op3, scale,
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negate, fmt, round, denorm, &result);
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break;
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case fmt_ps:
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{
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int status_u, status_l;
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unsigned64 result_u, result_l;
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status_u = inner_mac(sim_fpu_op, FP_PS_upper(op1), FP_PS_upper(op2),
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FP_PS_upper(op3), scale, negate, fmt_single,
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round, denorm, &result_u);
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status_l = inner_mac(sim_fpu_op, FP_PS_lower(op1), FP_PS_lower(op2),
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FP_PS_lower(op3), scale, negate, fmt_single,
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round, denorm, &result_l);
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result = FP_PS_cat(result_u, result_l);
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status = status_u | status_l;
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break;
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}
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default:
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sim_io_eprintf (SD, "Bad switch\n");
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abort ();
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@ -863,6 +946,18 @@ fp_inv_sqrt(sim_cpu *cpu,
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case fmt_double:
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status = inner_rsqrt (op1, fmt, round, denorm, &result);
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break;
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case fmt_ps:
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{
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int status_u, status_l;
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unsigned64 result_u, result_l;
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status_u = inner_rsqrt (FP_PS_upper(op1), fmt_single, round, denorm,
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&result_u);
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status_l = inner_rsqrt (FP_PS_lower(op1), fmt_single, round, denorm,
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&result_l);
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result = FP_PS_cat(result_u, result_l);
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status = status_u | status_l;
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break;
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}
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default:
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sim_io_eprintf (SD, "Bad switch\n");
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abort ();
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@ -1044,8 +1139,8 @@ convert (sim_cpu *cpu,
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/* The value WOP is converted to the destination format, rounding
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using mode RM. When the destination is a fixed-point format, then
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a source value of Infinity, NaN or one which would round to an
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integer outside the fixed point range then an IEEE Invalid
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Operation condition is raised. */
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integer outside the fixed point range then an IEEE Invalid Operation
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condition is raised. Not used if destination format is PS. */
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switch (to)
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{
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case fmt_single:
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@ -1080,6 +1175,114 @@ convert (sim_cpu *cpu,
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return result64;
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}
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unsigned64
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ps_lower(sim_cpu *cpu,
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address_word cia,
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unsigned64 op)
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{
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return FP_PS_lower (op);
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}
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unsigned64
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ps_upper(sim_cpu *cpu,
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address_word cia,
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unsigned64 op)
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{
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return FP_PS_upper(op);
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}
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unsigned64
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pack_ps(sim_cpu *cpu,
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address_word cia,
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unsigned64 op1,
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unsigned64 op2,
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FP_formats fmt)
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{
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unsigned64 result = 0;
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/* The registers must specify FPRs valid for operands of type
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"fmt". If they are not valid, the result is undefined. */
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/* The format type should already have been checked: */
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switch (fmt)
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{
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case fmt_single:
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{
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sim_fpu wop;
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unsigned32 res_u, res_l;
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sim_fpu_32to (&wop, op1);
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sim_fpu_to32 (&res_u, &wop);
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sim_fpu_32to (&wop, op2);
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sim_fpu_to32 (&res_l, &wop);
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result = FP_PS_cat(res_u, res_l);
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break;
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}
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default:
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sim_io_eprintf (SD, "Bad switch\n");
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abort ();
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}
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return result;
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}
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unsigned64
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convert_ps (sim_cpu *cpu,
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address_word cia,
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int rm,
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unsigned64 op,
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FP_formats from,
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FP_formats to)
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{
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sim_fpu wop_u, wop_l;
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sim_fpu_round round = rounding_mode (rm);
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sim_fpu_denorm denorm = denorm_mode (cpu);
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unsigned32 res_u, res_l;
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unsigned64 result;
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sim_fpu_status status_u = 0, status_l = 0;
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/* As convert, but used only for paired values (formats PS, PW) */
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/* Convert the input to sim_fpu internal format */
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switch (from)
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{
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case fmt_word: /* fmt_pw */
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sim_fpu_i32to (&wop_u, (op >> 32) & (unsigned)0xFFFFFFFF, round);
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sim_fpu_i32to (&wop_l, op & (unsigned)0xFFFFFFFF, round);
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break;
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case fmt_ps:
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sim_fpu_32to (&wop_u, FP_PS_upper(op));
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sim_fpu_32to (&wop_l, FP_PS_lower(op));
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break;
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default:
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sim_io_eprintf (SD, "Bad switch\n");
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abort ();
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}
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/* Convert sim_fpu format into the output */
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switch (to)
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{
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case fmt_word: /* fmt_pw */
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status_u |= sim_fpu_to32i (&res_u, &wop_u, round);
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status_l |= sim_fpu_to32i (&res_l, &wop_l, round);
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result = (((unsigned64)res_u) << 32) | (unsigned64)res_l;
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break;
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case fmt_ps:
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status_u |= sim_fpu_round_32 (&wop_u, 0, round);
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status_l |= sim_fpu_round_32 (&wop_l, 0, round);
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sim_fpu_to32 (&res_u, &wop_u);
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sim_fpu_to32 (&res_l, &wop_l);
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result = FP_PS_cat(res_u, res_l);
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break;
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default:
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result = 0;
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sim_io_eprintf (SD, "Bad switch\n");
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abort ();
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}
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update_fcsr (cpu, cia, status_u | status_l);
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return result;
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}
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static const char *
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fpu_format_name (FP_formats fmt)
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{
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@ -1093,6 +1296,8 @@ fpu_format_name (FP_formats fmt)
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return "word";
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case fmt_long:
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return "long";
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case fmt_ps:
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return "ps";
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case fmt_unknown:
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return "<unknown>";
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case fmt_uninterpreted:
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@ -3522,6 +3522,7 @@
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case fmt_double: return "d";
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case fmt_word: return "w";
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case fmt_long: return "l";
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case fmt_ps: return "ps";
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default: return "?";
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}
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}
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@ -3610,13 +3611,9 @@
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*mipsV:
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*mips64:
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{
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#if 0 /* XXX FIXME: FP code doesn't yet support paired single ops. */
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if ((fmt != fmt_single) && (fmt != fmt_double)
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&& (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
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SignalException (ReservedInstruction, insn);
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#else
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check_fmt (SD_, fmt, insn);
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#endif
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}
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@ -3684,6 +3681,32 @@
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}
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010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
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"alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
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*mipsV:
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*mips64:
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{
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unsigned64 fs;
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unsigned64 ft;
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unsigned64 fd;
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check_fpu (SD_);
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check_u64 (SD_, instruction_0);
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fs = ValueFPR (FS, fmt_ps);
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if ((GPR[RS] & 0x3) != 0)
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Unpredictable ();
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if ((GPR[RS] & 0x4) == 0)
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fd = fs;
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else
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{
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ft = ValueFPR (FT, fmt_ps);
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if (BigEndianCPU)
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fd = PackPS (PSLower (fs), PSUpper (ft));
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else
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fd = PackPS (PSLower (ft), PSUpper (fs));
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}
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StoreFPR (FD, fmt_ps, fd);
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}
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// BC1F
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// BC1FL
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@ -3946,10 +3969,22 @@
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}
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010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
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"cvt.ps.s f<FD>, f<FS>, f<FT>"
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*mipsV:
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*mips64:
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{
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check_fpu (SD_);
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check_u64 (SD_, instruction_0);
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StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
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ValueFPR (FT, fmt_single)));
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}
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//
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// FIXME: Does not correctly differentiate between mips*
|
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//
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010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
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010001,10,3.FMT!6,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
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"cvt.s.%s<FMT> f<FD>, f<FS>"
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*mipsI:
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*mipsII:
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@ -3971,6 +4006,28 @@
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}
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010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
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"cvt.s.pl f<FD>, f<FS>"
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*mipsV:
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*mips64:
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{
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check_fpu (SD_);
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check_u64 (SD_, instruction_0);
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StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
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}
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|
||||
010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
|
||||
"cvt.s.pu f<FD>, f<FS>"
|
||||
*mipsV:
|
||||
*mips64:
|
||||
{
|
||||
check_fpu (SD_);
|
||||
check_u64 (SD_, instruction_0);
|
||||
StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
|
||||
}
|
||||
|
||||
|
||||
010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
|
||||
"cvt.w.%s<FMT> f<FD>, f<FS>"
|
||||
*mipsI:
|
||||
@ -4284,12 +4341,22 @@
|
||||
{
|
||||
int fmt = FMT;
|
||||
check_fpu (SD_);
|
||||
{
|
||||
if (GETFCC(CC) == TF)
|
||||
StoreFPR (FD, fmt, ValueFPR (FS, fmt));
|
||||
else
|
||||
StoreFPR (FD, fmt, ValueFPR (FD, fmt));
|
||||
}
|
||||
if (fmt != fmt_ps)
|
||||
{
|
||||
if (GETFCC(CC) == TF)
|
||||
StoreFPR (FD, fmt, ValueFPR (FS, fmt));
|
||||
else
|
||||
StoreFPR (FD, fmt, ValueFPR (FD, fmt)); /* set fmt */
|
||||
}
|
||||
else
|
||||
{
|
||||
unsigned64 fd;
|
||||
fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
|
||||
fmt_ps)),
|
||||
PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
|
||||
fmt_ps)));
|
||||
StoreFPR (FD, fmt_ps, fd);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -4449,6 +4516,30 @@
|
||||
}
|
||||
|
||||
|
||||
010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
|
||||
"pll.ps f<FD>, f<FS>, f<FT>"
|
||||
*mipsV:
|
||||
*mips64:
|
||||
{
|
||||
check_fpu (SD_);
|
||||
check_u64 (SD_, instruction_0);
|
||||
StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
|
||||
PSLower (ValueFPR (FT, fmt_ps))));
|
||||
}
|
||||
|
||||
|
||||
010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
|
||||
"plu.ps f<FD>, f<FS>, f<FT>"
|
||||
*mipsV:
|
||||
*mips64:
|
||||
{
|
||||
check_fpu (SD_);
|
||||
check_u64 (SD_, instruction_0);
|
||||
StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
|
||||
PSUpper (ValueFPR (FT, fmt_ps))));
|
||||
}
|
||||
|
||||
|
||||
010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
|
||||
"prefx <HINT>, r<INDEX>(r<BASE>)"
|
||||
*mipsIV:
|
||||
@ -4467,6 +4558,31 @@
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
|
||||
"pul.ps f<FD>, f<FS>, f<FT>"
|
||||
*mipsV:
|
||||
*mips64:
|
||||
{
|
||||
check_fpu (SD_);
|
||||
check_u64 (SD_, instruction_0);
|
||||
StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
|
||||
PSLower (ValueFPR (FT, fmt_ps))));
|
||||
}
|
||||
|
||||
|
||||
010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
|
||||
"puu.ps f<FD>, f<FS>, f<FT>"
|
||||
*mipsV:
|
||||
*mips64:
|
||||
{
|
||||
check_fpu (SD_);
|
||||
check_u64 (SD_, instruction_0);
|
||||
StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
|
||||
PSUpper (ValueFPR (FT, fmt_ps))));
|
||||
}
|
||||
|
||||
|
||||
010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
|
||||
"recip.%s<FMT> f<FD>, f<FS>"
|
||||
*mipsIV:
|
||||
|
||||
@ -73,6 +73,7 @@ typedef enum {
|
||||
fmt_double = 1,
|
||||
fmt_word = 4,
|
||||
fmt_long = 5,
|
||||
fmt_ps = 6,
|
||||
/* The following are well outside the normal acceptable format
|
||||
range, and are used in the register status vector. */
|
||||
fmt_unknown = 0x10000000,
|
||||
@ -674,6 +675,12 @@ unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);
|
||||
#define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
|
||||
void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
|
||||
#define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
|
||||
unsigned64 ps_lower (SIM_STATE, unsigned64 op);
|
||||
#define PSLower(op) ps_lower (SIM_ARGS, op)
|
||||
unsigned64 ps_upper (SIM_STATE, unsigned64 op);
|
||||
#define PSUpper(op) ps_upper (SIM_ARGS, op)
|
||||
unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from);
|
||||
#define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single)
|
||||
|
||||
|
||||
/* FCR access. */
|
||||
@ -720,6 +727,9 @@ unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2,
|
||||
#define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt)
|
||||
unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
|
||||
#define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
|
||||
unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from,
|
||||
FP_formats to);
|
||||
#define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to)
|
||||
|
||||
|
||||
/* MDMX access. */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user