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* doc/all.texi: Replace BFIN with Blackfin.
* doc/as.texinfo: Likewise. * doc/c-bfin.texi: Likewise. * doc/asconfig.texi: Likewise. * doc/c-bfin.texi: Update -mcpu= option with bf512, bf514, bf516 and bf518.
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@ -1,3 +1,13 @@
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2009-09-04 Jie Zhang <jie.zhang@analog.com>
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* doc/all.texi: Replace BFIN with Blackfin.
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* doc/as.texinfo: Likewise.
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* doc/c-bfin.texi: Likewise.
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* doc/asconfig.texi: Likewise.
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* doc/c-bfin.texi: Update -mcpu= option with bf512, bf514,
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bf516 and bf518.
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2009-09-04 Jie Zhang <jie.zhang@analog.com>
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2009-09-04 Jie Zhang <jie.zhang@analog.com>
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* Makefile.am (bfin-parse.o): Remove bfin-parse.h from
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* Makefile.am (bfin-parse.o): Remove bfin-parse.h from
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@ -30,7 +30,7 @@
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@set ARC
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@set ARC
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@set ARM
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@set ARM
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@set AVR
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@set AVR
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@set BFIN
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@set Blackfin
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@set CR16
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@set CR16
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@set CRIS
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@set CRIS
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@set D10V
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@set D10V
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@ -6716,8 +6716,8 @@ subject, see the hardware manufacturer's manual.
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@ifset AVR
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@ifset AVR
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* AVR-Dependent:: AVR Dependent Features
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* AVR-Dependent:: AVR Dependent Features
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@end ifset
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@end ifset
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@ifset BFIN
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@ifset Blackfin
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* BFIN-Dependent:: BFIN Dependent Features
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* Blackfin-Dependent:: Blackfin Dependent Features
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@end ifset
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@end ifset
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@ifset CR16
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@ifset CR16
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* CR16-Dependent:: CR16 Dependent Features
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* CR16-Dependent:: CR16 Dependent Features
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@ -6851,7 +6851,7 @@ subject, see the hardware manufacturer's manual.
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@include c-avr.texi
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@include c-avr.texi
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@end ifset
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@end ifset
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@ifset BFIN
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@ifset Blackfin
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@include c-bfin.texi
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@include c-bfin.texi
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@end ifset
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@end ifset
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@ -4,7 +4,7 @@
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@c For copying conditions, see the file as.texinfo.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@ifset GENERIC
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@page
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@page
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@node BFIN-Dependent
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@node Blackfin-Dependent
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@chapter Blackfin Dependent Features
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@chapter Blackfin Dependent Features
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@end ifset
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@end ifset
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@ifclear GENERIC
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@ifclear GENERIC
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@ -34,6 +34,10 @@ is not used in assembler. It's here such that GCC can easily pass down its
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error message if an attempt is made to assemble an instruction which
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error message if an attempt is made to assemble an instruction which
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will not execute on the target processor. The following processor names are
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will not execute on the target processor. The following processor names are
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recognized:
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recognized:
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@code{bf512},
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@code{bf514},
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@code{bf516},
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@code{bf518},
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@code{bf522},
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@code{bf522},
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@code{bf523},
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@code{bf523},
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@code{bf524},
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@code{bf524},
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