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* config/tc-mips.c (append_insn): Don't do branch relaxation for MIPS-3D instructions either. (md_convert_frag): Update the COPx branch mask accordingly. * config/tc-mips.c (md_show_usage): Document --[no-]relax-branch option. * doc/as.texinfo (Overview): Add --relax-branch and --no-relax-branch. * doc/c-mips.texi (MIPS Opts): Document --relax-branch and --no-relax-branch. gas/testsuite/ * gas/mips/relax-bc1any.l: New test. * gas/mips/relax-bc1any.s: New test source. * gas/mips/mips.exp: Run the new test.
This commit is contained in:
Maciej W. Rozycki
parent
10bf68945e
commit
3bf0dbfb15
@ -1,3 +1,16 @@
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2013-06-10 Maciej W. Rozycki <macro@codesourcery.com>
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* config/tc-mips.c (append_insn): Don't do branch relaxation for
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MIPS-3D instructions either.
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(md_convert_frag): Update the COPx branch mask accordingly.
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* config/tc-mips.c (md_show_usage): Document --[no-]relax-branch
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option.
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* doc/as.texinfo (Overview): Add --relax-branch and
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--no-relax-branch.
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* doc/c-mips.texi (MIPS Opts): Document --relax-branch and
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--no-relax-branch.
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2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
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* config/tc-nios2.c (nios2_parse_args): Allow trap argument to
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@ -4394,9 +4394,9 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
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out that the branch was out-of-range, we'll get an error. */
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&& !mips_opts.warn_about_macros
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&& (mips_opts.at || mips_pic == NO_PIC)
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/* Don't relax BPOSGE32/64 as they have no complementing
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branches. */
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&& !(ip->insn_mo->ase & (ASE_DSP64 | ASE_DSP)));
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/* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
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as they have no complementing branches. */
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&& !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
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if (!HAVE_CODE_COMPRESSION
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&& address_expr
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@ -18177,10 +18177,10 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
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switch ((insn >> 28) & 0xf)
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{
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case 4:
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/* bc[0-3][tf]l? and bc1any[24][ft] instructions can
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have the condition reversed by tweaking a single
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bit, and their opcodes all have 0x4???????. */
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gas_assert ((insn & 0xf1000000) == 0x41000000);
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/* bc[0-3][tf]l? instructions can have the condition
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reversed by tweaking a single TF bit, and their
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opcodes all have 0x4???????. */
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gas_assert ((insn & 0xf3e00000) == 0x41000000);
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insn ^= 0x00010000;
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break;
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@ -19725,7 +19725,8 @@ MIPS options:\n\
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-msoft-float do not allow floating-point instructions\n\
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-msingle-float only allow 32-bit floating-point operations\n\
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-mdouble-float allow 32-bit and 64-bit floating-point operations\n\
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--[no-]construct-floats [dis]allow floating point values to be constructed\n"
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--[no-]construct-floats [dis]allow floating point values to be constructed\n\
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--[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n"
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));
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#ifdef OBJ_ELF
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fprintf (stream, _("\
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@ -1349,6 +1349,12 @@ value into the two single width floating point registers that make up
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the double width register. By default @samp{--construct-floats} is
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selected, allowing construction of these floating point constants.
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@item --relax-branch
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@itemx --no-relax-branch
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The @samp{--relax-branch} option enables the relaxation of out-of-range
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branches. By default @samp{--no-relax-branch} is selected, causing any
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out-of-range branches to produce an error.
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@cindex emulation
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@item --emulation=@var{name}
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This option causes @command{@value{AS}} to emulate @command{@value{AS}} configured
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@ -388,6 +388,27 @@ width register by the single width registers.
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By default @code{--construct-floats} is selected, allowing construction
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of these floating point constants.
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@item --relax-branch
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@itemx --no-relax-branch
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The @samp{--relax-branch} option enables the relaxation of out-of-range
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branches. Any branches whose target cannot be reached directly are
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converted to a small instruction sequence including an inverse-condition
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branch to the physically next instruction, and a jump to the original
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target is inserted between the two instructions. In PIC code the jump
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will involve further instructions for address calculation.
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The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T},
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@code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from
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relaxation, because they have no complementing counterparts. They could
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be relaxed with the use of a longer sequence involving another branch,
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however this has not been implemented and if their target turns out of
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reach, they produce an error even if branch relaxation is enabled.
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Also no @sc{mips16} branches are ever relaxed.
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By default @samp{--no-relax-branch} is selected, causing any out-of-range
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branches to produce an error.
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@item --trap
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@itemx --no-break
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@c FIXME! (1) reflect these options (next item too) in option summaries;
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@ -1,3 +1,9 @@
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2013-06-10 Maciej W. Rozycki <macro@codesourcery.com>
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* gas/mips/relax-bc1any.l: New test.
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* gas/mips/relax-bc1any.s: New test source.
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* gas/mips/mips.exp: Run the new test.
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2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
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* gas/nios2/trap.s: Add additional test cases for optional
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@ -842,6 +842,9 @@ if { [istarget mips*-*-vxworks*] } {
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run_dump_test "relax-swap1-mips2"
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run_dump_test "relax-swap2"
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run_dump_test_arches "relax-swap3" [mips_arch_list_all]
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run_list_test_arches "relax-bc1any" "-mips3d -relax-branch" \
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[mips_arch_list_matching mips64 \
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!micromips]
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run_list_test_arches "relax-bposge" "-mdsp -relax-branch" \
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[mips_arch_list_matching mips64r2 \
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!micromips]
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7
gas/testsuite/gas/mips/relax-bc1any.l
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7
gas/testsuite/gas/mips/relax-bc1any.l
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@ -0,0 +1,7 @@
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.*: Assembler messages:
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.*:6: Warning: Relaxed out-of-range branch into a jump
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.*:11: Warning: Relaxed out-of-range branch into a jump
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.*:7: Error: Branch out of range
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.*:8: Error: Branch out of range
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.*:9: Error: Branch out of range
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.*:10: Error: Branch out of range
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14
gas/testsuite/gas/mips/relax-bc1any.s
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14
gas/testsuite/gas/mips/relax-bc1any.s
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@ -0,0 +1,14 @@
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# Source file to test branch relaxation with the BC1ANY2F, BC1ANY2T,
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# BC1ANY4F and BC1ANY4T instructions.
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.text
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foo:
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b bar
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bc1any2f $cc0, bar
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bc1any2t $cc0, bar
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bc1any4f $cc0, bar
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bc1any4t $cc0, bar
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bal bar
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.space 0x20000
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bar:
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