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gas/
2007-09-08 H.J. Lu <hongjiu.lu@intel.com> * configure.in (AC_CHECK_HEADERS): Add limits.h. * configure: Regenerated. * config.in: Likewise. * config/tc-i386.c: Include "opcodes/i386-init.h". (_i386_insn): Use i386_operand_type for types. (cpu_arch_flags): Updated to new types with bitfield. (cpu_arch_tune_flags): Likewise. (cpu_arch_isa_flags): Likewise. (cpu_arch): Likewise. (i386_align_code): Likewise. (set_code_flag): Likewise. (set_16bit_gcc_code_flag): Likewise. (set_cpu_arch): Likewise. (md_assemble): Likewise. (parse_insn): Likewise. (process_operands): Likewise. (output_branch): Likewise. (output_jump): Likewise. (parse_real_register): Likewise. (mode_from_disp_size): Likewise. (smallest_imm_type): Likewise. (pi): Likewise. (type_names): Likewise. (pt): Likewise. (pte): Likewise. (swap_2_operands): Likewise. (optimize_imm): Likewise. (optimize_disp): Likewise. (match_template): Likewise. (check_string): Likewise. (process_suffix): Likewise. (check_byte_reg): Likewise. (check_long_reg): Likewise. (check_qword_reg): Likewise. (check_word_reg): Likewise. (finalize_imm): Likewise. (build_modrm_byte): Likewise. (output_insn): Likewise. (disp_size): Likewise. (imm_size): Likewise. (output_disp): Likewise. (output_imm): Likewise. (gotrel): Likewise. (i386_immediate): Likewise. (i386_displacement): Likewise. (i386_index_check): Likewise. (i386_operand): Likewise. (parse_real_register): Likewise. (i386_intel_operand): Likewise. (intel_e09): Likewise. (intel_bracket_expr): Likewise. (intel_e11): Likewise. (cpu_arch_flags_not): New. (cpu_flags_check_x64): Likewise. (cpu_flags_all_zero): Likewise. (cpu_flags_not): Likewise. (i386_cpu_flags_biop): Likewise. (cpu_flags_biop): Likewise. (cpu_flags_match); Likewise. (acc32): New. (acc64): Likewise. (control): Likewise. (reg16_inoutportreg): Likewise. (disp16): Likewise. (disp32): Likewise. (disp32s): Likewise. (disp16_32): Likewise. (anydisp): Likewise. (baseindex): Likewise. (regxmm): Likewise. (imm8): Likewise. (imm8s): Likewise. (imm16): Likewise. (imm32): Likewise. (imm32s): Likewise. (imm64): Likewise. (imm16_32): Likewise. (imm16_32s): Likewise. (imm16_32_32s): Likewise. (operand_type): Likewise. (operand_type_check): Likewise. (operand_type_match): Likewise. (operand_type_register_match): Likewise. (update_imm): Likewise. (set_code_flag): Also update cpu_arch_flags_not. (set_16bit_gcc_code_flag): Likewise. (md_begin): Likewise. (parse_insn): Use cpu_flags_check_x64 to check 64bit support. Use cpu_flags_match to match instructions. (i386_target_format): Update cpu_arch_isa_flags and cpu_arch_tune_flags to i386_cpu_flags type with bitfield. (smallest_imm_type): Check cpu_arch_tune to tune for i486. (match_template): Don't initialize overlap0, overlap1, overlap2, overlap3 and operand_types. (process_suffix): Handle crc32 with 64bit register. (MATCH): Removed. (CONSISTENT_REGISTER_MATCH): Likewise. * config/tc-i386.h (arch_entry): Updated to i386_cpu_flags type. opcodes/ 2007-09-08 H.J. Lu <hongjiu.lu@intel.com> * configure.in (AC_CHECK_HEADERS): Add limits.h. * configure: Regenerated. * config.in: Likewise. * i386-gen.c: Include "sysdep.h" instead of <stdlib.h> and <string.h>. Use xstrerror instead of strerror. (initializer): New. (cpu_flag_init): Likewise. (bitfield): Likewise. (BITFIELD): New. (cpu_flags): Likewise. (opcode_modifiers): Likewise. (operand_types): Likewise. (compare): Likewise. (set_cpu_flags): Likewise. (output_cpu_flags): Likewise. (process_i386_cpu_flags): Likewise. (output_opcode_modifier): Likewise. (process_i386_opcode_modifier): Likewise. (output_operand_type): Likewise. (process_i386_operand_type): Likewise. (set_bitfield): Likewise. (operand_type_init): Likewise. (process_i386_initializers): Likewise. (process_i386_opcodes): Call process_i386_opcode_modifier to process opcode_modifier. Call process_i386_operand_type to process operand_types. (process_i386_registers): Call process_i386_operand_type to process reg_type. (main): Check unused bits in i386_cpu_flags and i386_operand_type. Sort cpu_flags, opcode_modifiers and operand_types. Call process_i386_initializers. * i386-init.h: New. * i386-tbl.h: Regenerated. * i386-opc.h: Include <limits.h>. (CHAR_BIT): Define as 8 if not defined. (Cpu186): Changed to position of bitfiled. (Cpu286): Likewise. (Cpu386): Likewise. (Cpu486): Likewise. (Cpu586): Likewise. (Cpu686): Likewise. (CpuP4): Likewise. (CpuK6): Likewise. (CpuK8): Likewise. (CpuMMX): Likewise. (CpuMMX2): Likewise. (CpuSSE): Likewise. (CpuSSE2): Likewise. (Cpu3dnow): Likewise. (Cpu3dnowA): Likewise. (CpuSSE3): Likewise. (CpuPadLock): Likewise. (CpuSVME): Likewise. (CpuVMX): Likewise. (CpuSSSE3): Likewise. (CpuSSE4a): Likewise. (CpuABM): Likewise. (CpuSSE4_1): Likewise. (CpuSSE4_2): Likewise. (Cpu64): Likewise. (CpuNo64): Likewise. (D): Likewise. (W): Likewise. (Modrm): Likewise. (ShortForm): Likewise. (Jump): Likewise. (JumpDword): Likewise. (JumpByte): Likewise. (JumpInterSegment): Likewise. (FloatMF): Likewise. (FloatR): Likewise. (FloatD): Likewise. (Size16): Likewise. (Size32): Likewise. (Size64): Likewise. (IgnoreSize): Likewise. (DefaultSize): Likewise. (No_bSuf): Likewise. (No_wSuf): Likewise. (No_lSuf): Likewise. (No_sSuf): Likewise. (No_qSuf): Likewise. (No_xSuf): Likewise. (FWait): Likewise. (IsString): Likewise. (RegKludge): Likewise. (IsPrefix): Likewise. (ImmExt): Likewise. (NoRex64): Likewise. (Rex64): Likewise. (Ugh): Likewise. (Reg8): Likewise. (Reg16): Likewise. (Reg32): Likewise. (Reg64): Likewise. (FloatReg): Likewise. (RegMMX): Likewise. (RegXMM): Likewise. (Imm8): Likewise. (Imm8S): Likewise. (Imm16): Likewise. (Imm32): Likewise. (Imm32S): Likewise. (Imm64): Likewise. (Imm1): Likewise. (BaseIndex): Likewise. (Disp8): Likewise. (Disp16): Likewise. (Disp32): Likewise. (Disp32S): Likewise. (Disp64): Likewise. (InOutPortReg): Likewise. (ShiftCount): Likewise. (Control): Likewise. (Debug): Likewise. (Test): Likewise. (SReg2): Likewise. (SReg3): Likewise. (Acc): Likewise. (FloatAcc): Likewise. (JumpAbsolute): Likewise. (EsSeg): Likewise. (RegMem): Likewise. (OTMax): Likewise. (Reg): Commented out. (WordReg): Likewise. (ImplicitRegister): Likewise. (Imm): Likewise. (EncImm): Likewise. (Disp): Likewise. (AnyMem): Likewise. (LLongMem): Likewise. (LongMem): Likewise. (ShortMem): Likewise. (WordMem): Likewise. (ByteMem): Likewise. (CpuMax): New (CpuLM): Likewise. (CpuNumOfUints): Likewise. (CpuNumOfBits): Likewise. (CpuUnused): Likewise. (OTNumOfUints): Likewise. (OTNumOfBits): Likewise. (OTUnused): Likewise. (i386_cpu_flags): New type. (i386_operand_type): Likewise. (i386_opcode_modifier): Likewise. (CpuSledgehammer): Removed. (CpuSSE4): Likewise. (CpuUnknownFlags): Likewise. (Reg): Likewise. (WordReg): Likewise. (ImplicitRegister): Likewise. (Imm): Likewise. (EncImm): Likewise. (Disp): Likewise. (AnyMem): Likewise. (LLongMem): Likewise. (LongMem): Likewise. (ShortMem): Likewise. (WordMem): Likewise. (ByteMem): Likewise. (template): Use i386_cpu_flags for cpu_flags, use i386_opcode_modifier for opcode_modifier, use i386_operand_type for operand_types. (reg_entry): Use i386_operand_type for reg_type. * Makefile.am (HFILES): Add i386-init.h. ($(srcdir)/i386-init.h): New rule. ($(srcdir)/i386-tbl.h): Depend on $(srcdir)/i386-init.h instead. * Makefile.in: Regenerated.
This commit is contained in:
H.J. Lu
parent
fa956de32a
commit
40fb982012
104
gas/ChangeLog
104
gas/ChangeLog
@ -1,3 +1,107 @@
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2007-09-08 H.J. Lu <hongjiu.lu@intel.com>
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* configure.in (AC_CHECK_HEADERS): Add limits.h.
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* configure: Regenerated.
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* config.in: Likewise.
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* config/tc-i386.c: Include "opcodes/i386-init.h".
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(_i386_insn): Use i386_operand_type for types.
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(cpu_arch_flags): Updated to new types with bitfield.
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(cpu_arch_tune_flags): Likewise.
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(cpu_arch_isa_flags): Likewise.
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(cpu_arch): Likewise.
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(i386_align_code): Likewise.
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(set_code_flag): Likewise.
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(set_16bit_gcc_code_flag): Likewise.
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(set_cpu_arch): Likewise.
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(md_assemble): Likewise.
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(parse_insn): Likewise.
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(process_operands): Likewise.
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(output_branch): Likewise.
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(output_jump): Likewise.
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(parse_real_register): Likewise.
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(mode_from_disp_size): Likewise.
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(smallest_imm_type): Likewise.
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(pi): Likewise.
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(type_names): Likewise.
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(pt): Likewise.
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(pte): Likewise.
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(swap_2_operands): Likewise.
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(optimize_imm): Likewise.
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(optimize_disp): Likewise.
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(match_template): Likewise.
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(check_string): Likewise.
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(process_suffix): Likewise.
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(check_byte_reg): Likewise.
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(check_long_reg): Likewise.
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(check_qword_reg): Likewise.
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(check_word_reg): Likewise.
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(finalize_imm): Likewise.
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(build_modrm_byte): Likewise.
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(output_insn): Likewise.
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(disp_size): Likewise.
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(imm_size): Likewise.
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(output_disp): Likewise.
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(output_imm): Likewise.
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(gotrel): Likewise.
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(i386_immediate): Likewise.
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(i386_displacement): Likewise.
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(i386_index_check): Likewise.
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(i386_operand): Likewise.
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(parse_real_register): Likewise.
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(i386_intel_operand): Likewise.
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(intel_e09): Likewise.
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(intel_bracket_expr): Likewise.
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(intel_e11): Likewise.
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(cpu_arch_flags_not): New.
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(cpu_flags_check_x64): Likewise.
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(cpu_flags_all_zero): Likewise.
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(cpu_flags_not): Likewise.
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(i386_cpu_flags_biop): Likewise.
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(cpu_flags_biop): Likewise.
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(cpu_flags_match); Likewise.
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(acc32): New.
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(acc64): Likewise.
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(control): Likewise.
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(reg16_inoutportreg): Likewise.
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(disp16): Likewise.
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(disp32): Likewise.
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(disp32s): Likewise.
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(disp16_32): Likewise.
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(anydisp): Likewise.
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(baseindex): Likewise.
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(regxmm): Likewise.
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(imm8): Likewise.
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(imm8s): Likewise.
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(imm16): Likewise.
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(imm32): Likewise.
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(imm32s): Likewise.
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(imm64): Likewise.
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(imm16_32): Likewise.
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(imm16_32s): Likewise.
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(imm16_32_32s): Likewise.
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(operand_type): Likewise.
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(operand_type_check): Likewise.
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(operand_type_match): Likewise.
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(operand_type_register_match): Likewise.
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(update_imm): Likewise.
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(set_code_flag): Also update cpu_arch_flags_not.
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(set_16bit_gcc_code_flag): Likewise.
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(md_begin): Likewise.
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(parse_insn): Use cpu_flags_check_x64 to check 64bit support.
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Use cpu_flags_match to match instructions.
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(i386_target_format): Update cpu_arch_isa_flags and
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cpu_arch_tune_flags to i386_cpu_flags type with bitfield.
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(smallest_imm_type): Check cpu_arch_tune to tune for i486.
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(match_template): Don't initialize overlap0, overlap1,
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overlap2, overlap3 and operand_types.
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(process_suffix): Handle crc32 with 64bit register.
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(MATCH): Removed.
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(CONSISTENT_REGISTER_MATCH): Likewise.
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* config/tc-i386.h (arch_entry): Updated to i386_cpu_flags
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type.
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2007-09-06 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (match_template): Handle invlpga, vmload,
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@ -59,6 +59,9 @@
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/* Define to 1 if you have the <inttypes.h> header file. */
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#undef HAVE_INTTYPES_H
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/* Define to 1 if you have the <limits.h> header file. */
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#undef HAVE_LIMITS_H
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/* Define to 1 if you have the <memory.h> header file. */
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#undef HAVE_MEMORY_H
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1853
gas/config/tc-i386.c
1853
gas/config/tc-i386.c
File diff suppressed because it is too large
Load Diff
@ -186,7 +186,7 @@ typedef struct
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{
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const char *name; /* arch name */
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enum processor_type type; /* arch type */
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unsigned int flags; /* cpu feature flags */
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i386_cpu_flags flags; /* cpu feature flags */
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}
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arch_entry;
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3
gas/configure
vendored
3
gas/configure
vendored
@ -12049,7 +12049,8 @@ fi
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for ac_header in string.h stdlib.h memory.h strings.h unistd.h stdarg.h varargs.h errno.h sys/types.h
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for ac_header in string.h stdlib.h memory.h strings.h unistd.h stdarg.h varargs.h errno.h sys/types.h limits.h
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do
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as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
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if eval "test \"\${$as_ac_Header+set}\" = set"; then
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@ -608,7 +608,7 @@ AM_MAINTAINER_MODE
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AM_CONDITIONAL(GENINSRC_NEVER, false)
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AC_EXEEXT
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AC_CHECK_HEADERS(string.h stdlib.h memory.h strings.h unistd.h stdarg.h varargs.h errno.h sys/types.h)
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AC_CHECK_HEADERS(string.h stdlib.h memory.h strings.h unistd.h stdarg.h varargs.h errno.h sys/types.h limits.h)
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# Put this here so that autoconf's "cross-compiling" message doesn't confuse
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# people who are not cross-compiling but are compiling cross-assemblers.
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@ -1,3 +1,181 @@
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2007-09-08 H.J. Lu <hongjiu.lu@intel.com>
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* configure.in (AC_CHECK_HEADERS): Add limits.h.
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* configure: Regenerated.
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* config.in: Likewise.
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* i386-gen.c: Include "sysdep.h" instead of <stdlib.h> and
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<string.h>. Use xstrerror instead of strerror.
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(initializer): New.
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(cpu_flag_init): Likewise.
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(bitfield): Likewise.
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(BITFIELD): New.
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(cpu_flags): Likewise.
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(opcode_modifiers): Likewise.
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(operand_types): Likewise.
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(compare): Likewise.
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(set_cpu_flags): Likewise.
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(output_cpu_flags): Likewise.
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(process_i386_cpu_flags): Likewise.
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(output_opcode_modifier): Likewise.
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(process_i386_opcode_modifier): Likewise.
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(output_operand_type): Likewise.
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(process_i386_operand_type): Likewise.
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(set_bitfield): Likewise.
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(operand_type_init): Likewise.
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(process_i386_initializers): Likewise.
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(process_i386_opcodes): Call process_i386_opcode_modifier to
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process opcode_modifier. Call process_i386_operand_type to
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process operand_types.
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(process_i386_registers): Call process_i386_operand_type to
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process reg_type.
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(main): Check unused bits in i386_cpu_flags and i386_operand_type.
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Sort cpu_flags, opcode_modifiers and operand_types. Call
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process_i386_initializers.
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* i386-init.h: New.
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* i386-tbl.h: Regenerated.
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* i386-opc.h: Include <limits.h>.
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(CHAR_BIT): Define as 8 if not defined.
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(Cpu186): Changed to position of bitfiled.
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(Cpu286): Likewise.
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(Cpu386): Likewise.
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(Cpu486): Likewise.
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(Cpu586): Likewise.
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(Cpu686): Likewise.
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(CpuP4): Likewise.
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(CpuK6): Likewise.
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(CpuK8): Likewise.
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(CpuMMX): Likewise.
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(CpuMMX2): Likewise.
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(CpuSSE): Likewise.
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(CpuSSE2): Likewise.
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(Cpu3dnow): Likewise.
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(Cpu3dnowA): Likewise.
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(CpuSSE3): Likewise.
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(CpuPadLock): Likewise.
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(CpuSVME): Likewise.
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(CpuVMX): Likewise.
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(CpuSSSE3): Likewise.
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(CpuSSE4a): Likewise.
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(CpuABM): Likewise.
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(CpuSSE4_1): Likewise.
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(CpuSSE4_2): Likewise.
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(Cpu64): Likewise.
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(CpuNo64): Likewise.
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(D): Likewise.
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(W): Likewise.
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(Modrm): Likewise.
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(ShortForm): Likewise.
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(Jump): Likewise.
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(JumpDword): Likewise.
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(JumpByte): Likewise.
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(JumpInterSegment): Likewise.
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(FloatMF): Likewise.
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(FloatR): Likewise.
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(FloatD): Likewise.
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(Size16): Likewise.
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(Size32): Likewise.
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(Size64): Likewise.
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(IgnoreSize): Likewise.
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(DefaultSize): Likewise.
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(No_bSuf): Likewise.
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(No_wSuf): Likewise.
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(No_lSuf): Likewise.
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(No_sSuf): Likewise.
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(No_qSuf): Likewise.
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(No_xSuf): Likewise.
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(FWait): Likewise.
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(IsString): Likewise.
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(RegKludge): Likewise.
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(IsPrefix): Likewise.
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(ImmExt): Likewise.
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(NoRex64): Likewise.
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(Rex64): Likewise.
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(Ugh): Likewise.
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(Reg8): Likewise.
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(Reg16): Likewise.
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(Reg32): Likewise.
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(Reg64): Likewise.
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(FloatReg): Likewise.
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(RegMMX): Likewise.
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(RegXMM): Likewise.
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(Imm8): Likewise.
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(Imm8S): Likewise.
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(Imm16): Likewise.
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(Imm32): Likewise.
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(Imm32S): Likewise.
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(Imm64): Likewise.
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(Imm1): Likewise.
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(BaseIndex): Likewise.
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(Disp8): Likewise.
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(Disp16): Likewise.
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(Disp32): Likewise.
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(Disp32S): Likewise.
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(Disp64): Likewise.
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(InOutPortReg): Likewise.
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(ShiftCount): Likewise.
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(Control): Likewise.
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(Debug): Likewise.
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(Test): Likewise.
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(SReg2): Likewise.
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(SReg3): Likewise.
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(Acc): Likewise.
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(FloatAcc): Likewise.
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(JumpAbsolute): Likewise.
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(EsSeg): Likewise.
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(RegMem): Likewise.
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(OTMax): Likewise.
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(Reg): Commented out.
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(WordReg): Likewise.
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(ImplicitRegister): Likewise.
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(Imm): Likewise.
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(EncImm): Likewise.
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(Disp): Likewise.
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(AnyMem): Likewise.
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(LLongMem): Likewise.
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(LongMem): Likewise.
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(ShortMem): Likewise.
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(WordMem): Likewise.
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(ByteMem): Likewise.
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(CpuMax): New
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(CpuLM): Likewise.
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(CpuNumOfUints): Likewise.
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(CpuNumOfBits): Likewise.
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(CpuUnused): Likewise.
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(OTNumOfUints): Likewise.
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(OTNumOfBits): Likewise.
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(OTUnused): Likewise.
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(i386_cpu_flags): New type.
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(i386_operand_type): Likewise.
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(i386_opcode_modifier): Likewise.
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(CpuSledgehammer): Removed.
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(CpuSSE4): Likewise.
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(CpuUnknownFlags): Likewise.
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(Reg): Likewise.
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(WordReg): Likewise.
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(ImplicitRegister): Likewise.
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(Imm): Likewise.
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(EncImm): Likewise.
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(Disp): Likewise.
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(AnyMem): Likewise.
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(LLongMem): Likewise.
|
||||
(LongMem): Likewise.
|
||||
(ShortMem): Likewise.
|
||||
(WordMem): Likewise.
|
||||
(ByteMem): Likewise.
|
||||
(template): Use i386_cpu_flags for cpu_flags, use
|
||||
i386_opcode_modifier for opcode_modifier, use
|
||||
i386_operand_type for operand_types.
|
||||
(reg_entry): Use i386_operand_type for reg_type.
|
||||
|
||||
* Makefile.am (HFILES): Add i386-init.h.
|
||||
($(srcdir)/i386-init.h): New rule.
|
||||
($(srcdir)/i386-tbl.h): Depend on $(srcdir)/i386-init.h
|
||||
instead.
|
||||
* Makefile.in: Regenerated.
|
||||
|
||||
2007-09-06 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386-gen.c (next_field): Updated to take a separator.
|
||||
|
||||
@ -33,6 +33,7 @@ HFILES = \
|
||||
fr30-desc.h fr30-opc.h \
|
||||
frv-desc.h frv-opc.h \
|
||||
h8500-opc.h \
|
||||
i386-init.h \
|
||||
i386-opc.h \
|
||||
i386-tbl.h \
|
||||
ia64-asmtab.h \
|
||||
@ -575,7 +576,10 @@ i386-gen: i386-gen.o
|
||||
|
||||
i386-gen.o: i386-gen.c i386-opc.h
|
||||
|
||||
$(srcdir)/i386-tbl.h: @MAINT@ i386-gen i386-opc.tbl i386-reg.tbl
|
||||
$(srcdir)/i386-tbl.h: $(srcdir)/i386-init.h
|
||||
@echo $@
|
||||
|
||||
$(srcdir)/i386-init.h: @MAINT@ i386-gen i386-opc.tbl i386-reg.tbl
|
||||
./i386-gen --srcdir $(srcdir)
|
||||
|
||||
ia64-gen: ia64-gen.o
|
||||
|
||||
@ -260,6 +260,7 @@ HFILES = \
|
||||
fr30-desc.h fr30-opc.h \
|
||||
frv-desc.h frv-opc.h \
|
||||
h8500-opc.h \
|
||||
i386-init.h \
|
||||
i386-opc.h \
|
||||
i386-tbl.h \
|
||||
ia64-asmtab.h \
|
||||
@ -1126,7 +1127,10 @@ i386-gen: i386-gen.o
|
||||
|
||||
i386-gen.o: i386-gen.c i386-opc.h
|
||||
|
||||
$(srcdir)/i386-tbl.h: @MAINT@ i386-gen i386-opc.tbl i386-reg.tbl
|
||||
$(srcdir)/i386-tbl.h: $(srcdir)/i386-init.h
|
||||
@echo $@
|
||||
|
||||
$(srcdir)/i386-init.h: @MAINT@ i386-gen i386-opc.tbl i386-reg.tbl
|
||||
./i386-gen --srcdir $(srcdir)
|
||||
|
||||
ia64-gen: ia64-gen.o
|
||||
|
||||
@ -18,6 +18,9 @@
|
||||
/* Define to 1 if you have the <inttypes.h> header file. */
|
||||
#undef HAVE_INTTYPES_H
|
||||
|
||||
/* Define to 1 if you have the <limits.h> header file. */
|
||||
#undef HAVE_LIMITS_H
|
||||
|
||||
/* Define to 1 if you have the <memory.h> header file. */
|
||||
#undef HAVE_MEMORY_H
|
||||
|
||||
|
||||
3
opcodes/configure
vendored
3
opcodes/configure
vendored
@ -11108,7 +11108,8 @@ test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
|
||||
|
||||
|
||||
|
||||
for ac_header in string.h strings.h stdlib.h
|
||||
|
||||
for ac_header in string.h strings.h stdlib.h limits.h
|
||||
do
|
||||
as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
|
||||
if eval "test \"\${$as_ac_Header+set}\" = set"; then
|
||||
|
||||
@ -72,7 +72,7 @@ BFD_CC_FOR_BUILD
|
||||
AC_SUBST(HDEFINES)
|
||||
AC_PROG_INSTALL
|
||||
|
||||
AC_CHECK_HEADERS(string.h strings.h stdlib.h)
|
||||
AC_CHECK_HEADERS(string.h strings.h stdlib.h limits.h)
|
||||
|
||||
AC_CHECK_DECLS([basename, stpcpy])
|
||||
|
||||
|
||||
@ -17,9 +17,8 @@
|
||||
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
|
||||
MA 02110-1301, USA. */
|
||||
|
||||
#include "sysdep.h"
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <errno.h>
|
||||
#include "getopt.h"
|
||||
#include "libiberty.h"
|
||||
@ -33,6 +32,300 @@
|
||||
static const char *program_name = NULL;
|
||||
static int debug = 0;
|
||||
|
||||
typedef struct initializer
|
||||
{
|
||||
const char *name;
|
||||
const char *init;
|
||||
} initializer;
|
||||
|
||||
static initializer cpu_flag_init [] =
|
||||
{
|
||||
{ "CPU_UNKNOWN_FLAGS",
|
||||
"unknown" },
|
||||
{ "CPU_GENERIC32_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386" },
|
||||
{ "CPU_GENERIC64_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2" },
|
||||
{ "CPU_NONE_FLAGS",
|
||||
"0" },
|
||||
{ "CPU_I186_FLAGS",
|
||||
"Cpu186" },
|
||||
{ "CPU_I286_FLAGS",
|
||||
"Cpu186|Cpu286" },
|
||||
{ "CPU_I386_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386" },
|
||||
{ "CPU_I486_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486" },
|
||||
{ "CPU_I586_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586" },
|
||||
{ "CPU_I686_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686" },
|
||||
{ "CPU_P2_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX" },
|
||||
{ "CPU_P3_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE" },
|
||||
{ "CPU_P4_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2" },
|
||||
{ "CPU_NOCONA_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuLM" },
|
||||
{ "CPU_CORE_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3" },
|
||||
{ "CPU_CORE2_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuLM" },
|
||||
{ "CPU_K6_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX" },
|
||||
{ "CPU_K6_2_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow" },
|
||||
{ "CPU_ATHLON_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA" },
|
||||
{ "CPU_K8_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuLM" },
|
||||
{ "CPU_AMDFAM10_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM" },
|
||||
{ "CPU_MMX_FLAGS",
|
||||
"CpuMMX" },
|
||||
{ "CPU_SSE_FLAGS",
|
||||
"CpuMMX|CpuMMX2|CpuSSE" },
|
||||
{ "CPU_SSE2_FLAGS",
|
||||
"CpuMMX|CpuMMX2|CpuSSE|CpuSSE2" },
|
||||
{ "CPU_SSE3_FLAGS",
|
||||
"CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3" },
|
||||
{ "CPU_SSSE3_FLAGS",
|
||||
"CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3" },
|
||||
{ "CPU_SSE4_1_FLAGS",
|
||||
"CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1" },
|
||||
{ "CPU_SSE4_2_FLAGS",
|
||||
"CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2" },
|
||||
{ "CPU_3DNOW_FLAGS",
|
||||
"CpuMMX|Cpu3dnow" },
|
||||
{ "CPU_3DNOWA_FLAGS",
|
||||
"CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA" },
|
||||
{ "CPU_PADLOCK_FLAGS",
|
||||
"CpuPadLock" },
|
||||
{ "CPU_SVME_FLAGS",
|
||||
"CpuSVME" },
|
||||
{ "CPU_SSE4A_FLAGS",
|
||||
"CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a" },
|
||||
{ "CPU_ABM_FLAGS",
|
||||
"CpuABM" }
|
||||
};
|
||||
|
||||
static initializer operand_type_init [] =
|
||||
{
|
||||
{ "OPERAND_TYPE_NONE",
|
||||
"0" },
|
||||
{ "OPERAND_TYPE_REG8",
|
||||
"Reg8" },
|
||||
{ "OPERAND_TYPE_REG16",
|
||||
"Reg16" },
|
||||
{ "OPERAND_TYPE_REG32",
|
||||
"Reg32" },
|
||||
{ "OPERAND_TYPE_REG64",
|
||||
"Reg64" },
|
||||
{ "OPERAND_TYPE_IMM1",
|
||||
"Imm1" },
|
||||
{ "OPERAND_TYPE_IMM8",
|
||||
"Imm8" },
|
||||
{ "OPERAND_TYPE_IMM8S",
|
||||
"Imm8S" },
|
||||
{ "OPERAND_TYPE_IMM16",
|
||||
"Imm16" },
|
||||
{ "OPERAND_TYPE_IMM32",
|
||||
"Imm32" },
|
||||
{ "OPERAND_TYPE_IMM32S",
|
||||
"Imm32S" },
|
||||
{ "OPERAND_TYPE_IMM64",
|
||||
"Imm64" },
|
||||
{ "OPERAND_TYPE_BASEINDEX",
|
||||
"BaseIndex" },
|
||||
{ "OPERAND_TYPE_DISP8",
|
||||
"Disp8" },
|
||||
{ "OPERAND_TYPE_DISP16",
|
||||
"Disp16" },
|
||||
{ "OPERAND_TYPE_DISP32",
|
||||
"Disp32" },
|
||||
{ "OPERAND_TYPE_DISP32S",
|
||||
"Disp32S" },
|
||||
{ "OPERAND_TYPE_DISP64",
|
||||
"Disp64" },
|
||||
{ "OPERAND_TYPE_INOUTPORTREG",
|
||||
"InOutPortReg" },
|
||||
{ "OPERAND_TYPE_SHIFTCOUNT",
|
||||
"ShiftCount" },
|
||||
{ "OPERAND_TYPE_CONTROL",
|
||||
"Control" },
|
||||
{ "OPERAND_TYPE_TEST",
|
||||
"Test" },
|
||||
{ "OPERAND_TYPE_DEBUG",
|
||||
"FloatReg" },
|
||||
{ "OPERAND_TYPE_FLOATREG",
|
||||
"FloatReg" },
|
||||
{ "OPERAND_TYPE_FLOATACC",
|
||||
"FloatAcc" },
|
||||
{ "OPERAND_TYPE_SREG2",
|
||||
"SReg2" },
|
||||
{ "OPERAND_TYPE_SREG3",
|
||||
"SReg3" },
|
||||
{ "OPERAND_TYPE_ACC",
|
||||
"Acc" },
|
||||
{ "OPERAND_TYPE_JUMPABSOLUTE",
|
||||
"JumpAbsolute" },
|
||||
{ "OPERAND_TYPE_REGMMX",
|
||||
"RegMMX" },
|
||||
{ "OPERAND_TYPE_REGXMM",
|
||||
"RegXMM" },
|
||||
{ "OPERAND_TYPE_ESSEG",
|
||||
"EsSeg" },
|
||||
{ "OPERAND_TYPE_ACC32",
|
||||
"Reg32|Acc" },
|
||||
{ "OPERAND_TYPE_ACC64",
|
||||
"Reg64|Acc" },
|
||||
{ "OPERAND_TYPE_REG16_INOUTPORTREG",
|
||||
"Reg16|InOutPortReg" },
|
||||
{ "OPERAND_TYPE_DISP16_32",
|
||||
"Disp16|Disp32" },
|
||||
{ "OPERAND_TYPE_ANYDISP",
|
||||
"Disp8|Disp16|Disp32|Disp32S|Disp64" },
|
||||
{ "OPERAND_TYPE_IMM16_32",
|
||||
"Imm16|Imm32" },
|
||||
{ "OPERAND_TYPE_IMM16_32S",
|
||||
"Imm16|Imm32S" },
|
||||
{ "OPERAND_TYPE_IMM16_32_32S",
|
||||
"Imm16|Imm32|Imm32S" },
|
||||
{ "OPERAND_TYPE_IMM32_32S_DISP32",
|
||||
"Imm32|Imm32S|Disp32" },
|
||||
{ "OPERAND_TYPE_IMM64_DISP64",
|
||||
"Imm64|Disp64" },
|
||||
{ "OPERAND_TYPE_IMM32_32S_64_DISP32",
|
||||
"Imm32|Imm32S|Imm64|Disp32" },
|
||||
{ "OPERAND_TYPE_IMM32_32S_64_DISP32_64",
|
||||
"Imm32|Imm32S|Imm64|Disp32|Disp64" },
|
||||
};
|
||||
|
||||
typedef struct bitfield
|
||||
{
|
||||
int position;
|
||||
int value;
|
||||
const char *name;
|
||||
} bitfield;
|
||||
|
||||
#define BITFIELD(n) { n, 0, #n }
|
||||
|
||||
static bitfield cpu_flags[] =
|
||||
{
|
||||
BITFIELD (Cpu186),
|
||||
BITFIELD (Cpu286),
|
||||
BITFIELD (Cpu386),
|
||||
BITFIELD (Cpu486),
|
||||
BITFIELD (Cpu586),
|
||||
BITFIELD (Cpu686),
|
||||
BITFIELD (CpuP4),
|
||||
BITFIELD (CpuK6),
|
||||
BITFIELD (CpuK8),
|
||||
BITFIELD (CpuMMX),
|
||||
BITFIELD (CpuMMX2),
|
||||
BITFIELD (CpuSSE),
|
||||
BITFIELD (CpuSSE2),
|
||||
BITFIELD (CpuSSE3),
|
||||
BITFIELD (CpuSSSE3),
|
||||
BITFIELD (CpuSSE4_1),
|
||||
BITFIELD (CpuSSE4_2),
|
||||
BITFIELD (CpuSSE4a),
|
||||
BITFIELD (Cpu3dnow),
|
||||
BITFIELD (Cpu3dnowA),
|
||||
BITFIELD (CpuPadLock),
|
||||
BITFIELD (CpuSVME),
|
||||
BITFIELD (CpuVMX),
|
||||
BITFIELD (CpuABM),
|
||||
BITFIELD (CpuLM),
|
||||
BITFIELD (Cpu64),
|
||||
BITFIELD (CpuNo64),
|
||||
#ifdef CpuUnused
|
||||
BITFIELD (CpuUnused),
|
||||
#endif
|
||||
};
|
||||
|
||||
static bitfield opcode_modifiers[] =
|
||||
{
|
||||
BITFIELD (D),
|
||||
BITFIELD (W),
|
||||
BITFIELD (Modrm),
|
||||
BITFIELD (ShortForm),
|
||||
BITFIELD (Jump),
|
||||
BITFIELD (JumpDword),
|
||||
BITFIELD (JumpByte),
|
||||
BITFIELD (JumpInterSegment),
|
||||
BITFIELD (FloatMF),
|
||||
BITFIELD (FloatR),
|
||||
BITFIELD (FloatD),
|
||||
BITFIELD (Size16),
|
||||
BITFIELD (Size32),
|
||||
BITFIELD (Size64),
|
||||
BITFIELD (IgnoreSize),
|
||||
BITFIELD (DefaultSize),
|
||||
BITFIELD (No_bSuf),
|
||||
BITFIELD (No_wSuf),
|
||||
BITFIELD (No_lSuf),
|
||||
BITFIELD (No_sSuf),
|
||||
BITFIELD (No_qSuf),
|
||||
BITFIELD (No_xSuf),
|
||||
BITFIELD (FWait),
|
||||
BITFIELD (IsString),
|
||||
BITFIELD (RegKludge),
|
||||
BITFIELD (IsPrefix),
|
||||
BITFIELD (ImmExt),
|
||||
BITFIELD (NoRex64),
|
||||
BITFIELD (Rex64),
|
||||
BITFIELD (Ugh),
|
||||
};
|
||||
|
||||
static bitfield operand_types[] =
|
||||
{
|
||||
BITFIELD (Reg8),
|
||||
BITFIELD (Reg16),
|
||||
BITFIELD (Reg32),
|
||||
BITFIELD (Reg64),
|
||||
BITFIELD (FloatReg),
|
||||
BITFIELD (RegMMX),
|
||||
BITFIELD (RegXMM),
|
||||
BITFIELD (Imm8),
|
||||
BITFIELD (Imm8S),
|
||||
BITFIELD (Imm16),
|
||||
BITFIELD (Imm32),
|
||||
BITFIELD (Imm32S),
|
||||
BITFIELD (Imm64),
|
||||
BITFIELD (Imm1),
|
||||
BITFIELD (BaseIndex),
|
||||
BITFIELD (Disp8),
|
||||
BITFIELD (Disp16),
|
||||
BITFIELD (Disp32),
|
||||
BITFIELD (Disp32S),
|
||||
BITFIELD (Disp64),
|
||||
BITFIELD (InOutPortReg),
|
||||
BITFIELD (ShiftCount),
|
||||
BITFIELD (Control),
|
||||
BITFIELD (Debug),
|
||||
BITFIELD (Test),
|
||||
BITFIELD (SReg2),
|
||||
BITFIELD (SReg3),
|
||||
BITFIELD (Acc),
|
||||
BITFIELD (FloatAcc),
|
||||
BITFIELD (JumpAbsolute),
|
||||
BITFIELD (EsSeg),
|
||||
BITFIELD (RegMem),
|
||||
#ifdef OTUnused
|
||||
BITFIELD (OTUnused),
|
||||
#endif
|
||||
};
|
||||
|
||||
static int
|
||||
compare (const void *x, const void *y)
|
||||
{
|
||||
const bitfield *xp = (const bitfield *) x;
|
||||
const bitfield *yp = (const bitfield *) y;
|
||||
return xp->position - yp->position;
|
||||
}
|
||||
|
||||
static void
|
||||
fail (const char *message, ...)
|
||||
{
|
||||
@ -119,6 +412,171 @@ next_field (char *str, char sep, char **next)
|
||||
return p;
|
||||
}
|
||||
|
||||
static void
|
||||
set_bitfield (const char *f, bitfield *array, unsigned int size)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
if (strcmp (f, "CpuSledgehammer") == 0)
|
||||
f= "CpuK8";
|
||||
|
||||
for (i = 0; i < size; i++)
|
||||
if (strcasecmp (array[i].name, f) == 0)
|
||||
{
|
||||
array[i].value = 1;
|
||||
return;
|
||||
}
|
||||
|
||||
printf ("Unknown bitfield: %s\n", f);
|
||||
abort ();
|
||||
}
|
||||
|
||||
static void
|
||||
output_cpu_flags (FILE *table, bitfield *flags, unsigned int size,
|
||||
int macro, const char *comma, const char *indent)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
fprintf (table, "%s{ { ", indent);
|
||||
|
||||
for (i = 0; i < size - 1; i++)
|
||||
{
|
||||
fprintf (table, "%d, ", flags[i].value);
|
||||
if (((i + 1) % 20) == 0)
|
||||
{
|
||||
/* We need \\ for macro. */
|
||||
if (macro)
|
||||
fprintf (table, " \\\n %s", indent);
|
||||
else
|
||||
fprintf (table, "\n %s", indent);
|
||||
}
|
||||
}
|
||||
|
||||
fprintf (table, "%d } }%s\n", flags[i].value, comma);
|
||||
}
|
||||
|
||||
static void
|
||||
process_i386_cpu_flag (FILE *table, char *flag, int macro,
|
||||
const char *comma, const char *indent)
|
||||
{
|
||||
char *str, *next, *last;
|
||||
bitfield flags [ARRAY_SIZE (cpu_flags)];
|
||||
|
||||
/* Copy the default cpu flags. */
|
||||
memcpy (flags, cpu_flags, sizeof (cpu_flags));
|
||||
|
||||
if (strcasecmp (flag, "unknown") == 0)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
/* We turn on everything except for cpu64 in case of
|
||||
CPU_UNKNOWN_FLAGS. */
|
||||
for (i = 0; i < ARRAY_SIZE (flags); i++)
|
||||
if (flags[i].position != Cpu64)
|
||||
flags[i].value = 1;
|
||||
}
|
||||
else if (strcmp (flag, "0"))
|
||||
{
|
||||
last = flag + strlen (flag);
|
||||
for (next = flag; next && next < last; )
|
||||
{
|
||||
str = next_field (next, '|', &next);
|
||||
if (str)
|
||||
set_bitfield (str, flags, ARRAY_SIZE (flags));
|
||||
}
|
||||
}
|
||||
|
||||
output_cpu_flags (table, flags, ARRAY_SIZE (flags), macro,
|
||||
comma, indent);
|
||||
}
|
||||
|
||||
static void
|
||||
output_opcode_modifier (FILE *table, bitfield *modifier, unsigned int size)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
fprintf (table, " { ");
|
||||
|
||||
for (i = 0; i < size - 1; i++)
|
||||
{
|
||||
fprintf (table, "%d, ", modifier[i].value);
|
||||
if (((i + 1) % 20) == 0)
|
||||
fprintf (table, "\n ");
|
||||
}
|
||||
|
||||
fprintf (table, "%d },\n", modifier[i].value);
|
||||
}
|
||||
|
||||
static void
|
||||
process_i386_opcode_modifier (FILE *table, char *mod)
|
||||
{
|
||||
char *str, *next, *last;
|
||||
bitfield modifiers [ARRAY_SIZE (opcode_modifiers)];
|
||||
|
||||
/* Copy the default opcode modifier. */
|
||||
memcpy (modifiers, opcode_modifiers, sizeof (modifiers));
|
||||
|
||||
if (strcmp (mod, "0"))
|
||||
{
|
||||
last = mod + strlen (mod);
|
||||
for (next = mod; next && next < last; )
|
||||
{
|
||||
str = next_field (next, '|', &next);
|
||||
if (str)
|
||||
set_bitfield (str, modifiers, ARRAY_SIZE (modifiers));
|
||||
}
|
||||
}
|
||||
output_opcode_modifier (table, modifiers, ARRAY_SIZE (modifiers));
|
||||
}
|
||||
|
||||
static void
|
||||
output_operand_type (FILE *table, bitfield *types, unsigned int size,
|
||||
int macro, const char *indent)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
fprintf (table, "{ { ");
|
||||
|
||||
for (i = 0; i < size - 1; i++)
|
||||
{
|
||||
fprintf (table, "%d, ", types[i].value);
|
||||
if (((i + 1) % 20) == 0)
|
||||
{
|
||||
/* We need \\ for macro. */
|
||||
if (macro)
|
||||
fprintf (table, "\\\n%s", indent);
|
||||
else
|
||||
fprintf (table, "\n%s", indent);
|
||||
}
|
||||
}
|
||||
|
||||
fprintf (table, "%d } }", types[i].value);
|
||||
}
|
||||
|
||||
static void
|
||||
process_i386_operand_type (FILE *table, char *op, int macro,
|
||||
const char *indent)
|
||||
{
|
||||
char *str, *next, *last;
|
||||
bitfield types [ARRAY_SIZE (operand_types)];
|
||||
|
||||
/* Copy the default operand type. */
|
||||
memcpy (types, operand_types, sizeof (types));
|
||||
|
||||
if (strcmp (op, "0"))
|
||||
{
|
||||
last = op + strlen (op);
|
||||
for (next = op; next && next < last; )
|
||||
{
|
||||
str = next_field (next, '|', &next);
|
||||
if (str)
|
||||
set_bitfield (str, types, ARRAY_SIZE (types));
|
||||
}
|
||||
}
|
||||
output_operand_type (table, types, ARRAY_SIZE (types), macro,
|
||||
indent);
|
||||
}
|
||||
|
||||
static void
|
||||
process_i386_opcodes (FILE *table)
|
||||
{
|
||||
@ -131,7 +589,7 @@ process_i386_opcodes (FILE *table)
|
||||
|
||||
if (fp == NULL)
|
||||
fail (_("can't find i386-opc.tbl for reading, errno = %s\n"),
|
||||
strerror (errno));
|
||||
xstrerror (errno));
|
||||
|
||||
fprintf (table, "\n/* i386 opcode table. */\n\n");
|
||||
fprintf (table, "const template i386_optab[] =\n{\n");
|
||||
@ -243,11 +701,12 @@ process_i386_opcodes (FILE *table)
|
||||
}
|
||||
}
|
||||
|
||||
fprintf (table, " { \"%s\", %s, %s, %s, %s,\n",
|
||||
name, operands, base_opcode, extension_opcode,
|
||||
cpu_flags);
|
||||
fprintf (table, " { \"%s\", %s, %s, %s,\n",
|
||||
name, operands, base_opcode, extension_opcode);
|
||||
|
||||
fprintf (table, " %s,\n", opcode_modifier);
|
||||
process_i386_cpu_flag (table, cpu_flags, 0, ",", " ");
|
||||
|
||||
process_i386_opcode_modifier (table, opcode_modifier);
|
||||
|
||||
fprintf (table, " { ");
|
||||
|
||||
@ -257,21 +716,31 @@ process_i386_opcodes (FILE *table)
|
||||
|| *operand_types[i] == '0')
|
||||
{
|
||||
if (i == 0)
|
||||
fprintf (table, "0");
|
||||
process_i386_operand_type (table, "0", 0, "\t ");
|
||||
break;
|
||||
}
|
||||
|
||||
if (i != 0)
|
||||
fprintf (table, ",\n ");
|
||||
|
||||
fprintf (table, "%s", operand_types[i]);
|
||||
process_i386_operand_type (table, operand_types[i], 0,
|
||||
"\t ");
|
||||
}
|
||||
fprintf (table, " } },\n");
|
||||
}
|
||||
|
||||
fclose (fp);
|
||||
|
||||
fprintf (table, " { NULL, 0, 0, 0, 0, 0, { 0 } }\n");
|
||||
fprintf (table, " { NULL, 0, 0, 0,\n");
|
||||
|
||||
process_i386_cpu_flag (table, "0", 0, ",", " ");
|
||||
|
||||
process_i386_opcode_modifier (table, "0");
|
||||
|
||||
fprintf (table, " { ");
|
||||
process_i386_operand_type (table, "0", 0, "\t ");
|
||||
fprintf (table, " } }\n");
|
||||
|
||||
fprintf (table, "};\n");
|
||||
}
|
||||
|
||||
@ -285,7 +754,7 @@ process_i386_registers (FILE *table)
|
||||
|
||||
if (fp == NULL)
|
||||
fail (_("can't find i386-reg.tbl for reading, errno = %s\n"),
|
||||
strerror (errno));
|
||||
xstrerror (errno));
|
||||
|
||||
fprintf (table, "\n/* i386 register table. */\n\n");
|
||||
fprintf (table, "const reg_entry i386_regtab[] =\n{\n");
|
||||
@ -339,8 +808,11 @@ process_i386_registers (FILE *table)
|
||||
/* Find reg_num. */
|
||||
reg_num = next_field (str, ',', &str);
|
||||
|
||||
fprintf (table, " { \"%s\", %s, %s, %s },\n",
|
||||
reg_name, reg_type, reg_flags, reg_num);
|
||||
fprintf (table, " { \"%s\",\n ", reg_name);
|
||||
|
||||
process_i386_operand_type (table, reg_type, 0, "\t");
|
||||
|
||||
fprintf (table, ",\n %s, %s },\n", reg_flags, reg_num);
|
||||
}
|
||||
|
||||
fclose (fp);
|
||||
@ -350,6 +822,39 @@ process_i386_registers (FILE *table)
|
||||
fprintf (table, "\nconst unsigned int i386_regtab_size = ARRAY_SIZE (i386_regtab);\n");
|
||||
}
|
||||
|
||||
static void
|
||||
process_i386_initializers (void)
|
||||
{
|
||||
unsigned int i;
|
||||
FILE *fp = fopen ("i386-init.h", "w");
|
||||
char *init;
|
||||
|
||||
if (fp == NULL)
|
||||
fail (_("can't create i386-init.h, errno = %s\n"),
|
||||
xstrerror (errno));
|
||||
|
||||
process_copyright (fp);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE (cpu_flag_init); i++)
|
||||
{
|
||||
fprintf (fp, "\n#define %s \\\n", cpu_flag_init[i].name);
|
||||
init = xstrdup (cpu_flag_init[i].init);
|
||||
process_i386_cpu_flag (fp, init, 1, "", " ");
|
||||
free (init);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE (operand_type_init); i++)
|
||||
{
|
||||
fprintf (fp, "\n\n#define %s \\\n ", operand_type_init[i].name);
|
||||
init = xstrdup (operand_type_init[i].init);
|
||||
process_i386_operand_type (fp, init, 1, " ");
|
||||
free (init);
|
||||
}
|
||||
fprintf (fp, "\n");
|
||||
|
||||
fclose (fp);
|
||||
}
|
||||
|
||||
/* Program options. */
|
||||
#define OPTION_SRCDIR 200
|
||||
|
||||
@ -382,7 +887,7 @@ main (int argc, char **argv)
|
||||
{
|
||||
extern int chdir (char *);
|
||||
char *srcdir = NULL;
|
||||
int c;
|
||||
int c, unused;
|
||||
FILE *table;
|
||||
|
||||
program_name = *argv;
|
||||
@ -415,16 +920,41 @@ main (int argc, char **argv)
|
||||
if (srcdir != NULL)
|
||||
if (chdir (srcdir) != 0)
|
||||
fail (_("unable to change directory to \"%s\", errno = %s\n"),
|
||||
srcdir, strerror (errno));
|
||||
srcdir, xstrerror (errno));
|
||||
|
||||
/* Check the unused bitfield in i386_cpu_flags. */
|
||||
#ifndef CpuUnused
|
||||
unused = CpuNumOfBits - CpuMax - 1;
|
||||
if (unused)
|
||||
fail (_("%d unused bits in i386_cpu_flags.\n"), unused);
|
||||
#endif
|
||||
|
||||
/* Check the unused bitfield in i386_operand_type. */
|
||||
#ifndef OTUnused
|
||||
unused = OTNumOfBits - OTMax - 1;
|
||||
if (unused)
|
||||
fail (_("%d unused bits in i386_operand_type.\n"), unused);
|
||||
#endif
|
||||
|
||||
qsort (cpu_flags, ARRAY_SIZE (cpu_flags), sizeof (cpu_flags [0]),
|
||||
compare);
|
||||
|
||||
qsort (opcode_modifiers, ARRAY_SIZE (opcode_modifiers),
|
||||
sizeof (opcode_modifiers [0]), compare);
|
||||
|
||||
qsort (operand_types, ARRAY_SIZE (operand_types),
|
||||
sizeof (operand_types [0]), compare);
|
||||
|
||||
table = fopen ("i386-tbl.h", "w");
|
||||
if (table == NULL)
|
||||
fail (_("can't create i386-tbl.h, errno = %s\n"), strerror (errno));
|
||||
fail (_("can't create i386-tbl.h, errno = %s\n"),
|
||||
xstrerror (errno));
|
||||
|
||||
process_copyright (table);
|
||||
|
||||
process_i386_opcodes (table);
|
||||
process_i386_registers (table);
|
||||
process_i386_initializers ();
|
||||
|
||||
fclose (table);
|
||||
|
||||
|
||||
332
opcodes/i386-init.h
Normal file
332
opcodes/i386-init.h
Normal file
@ -0,0 +1,332 @@
|
||||
/* This file is automatically generated by i386-gen. Do not edit! */
|
||||
/* Copyright 2007 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU opcodes library.
|
||||
|
||||
This library is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
It is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
|
||||
MA 02110-1301, USA. */
|
||||
|
||||
#define CPU_UNKNOWN_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
|
||||
#define CPU_GENERIC32_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_GENERIC64_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NONE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I186_FLAGS \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I286_FLAGS \
|
||||
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I386_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I486_FLAGS \
|
||||
{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I586_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I686_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NOCONA_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ATHLON_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K8_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AMDFAM10_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
|
||||
1, 1, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOWA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PADLOCK_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SVME_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4A_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ABM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG8 \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG16 \
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG32 \
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG64 \
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM1 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM8 \
|
||||
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM8S \
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_BASEINDEX \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP8 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP16 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_INOUTPORTREG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SHIFTCOUNT \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_CONTROL \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_TEST \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DEBUG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_FLOATREG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_FLOATACC \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SREG2 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SREG3 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_JUMPABSOLUTE \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGMMX \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGXMM \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ESSEG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC32 \
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC64 \
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG16_INOUTPORTREG \
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP16_32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ANYDISP \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32_32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM64_DISP64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32_64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
@ -20,6 +20,365 @@
|
||||
02110-1301, USA. */
|
||||
|
||||
#include "opcode/i386.h"
|
||||
#ifdef HAVE_LIMITS_H
|
||||
#include <limits.h>
|
||||
#endif
|
||||
|
||||
#ifndef CHAR_BIT
|
||||
#define CHAR_BIT 8
|
||||
#endif
|
||||
|
||||
/* Position of cpu flags bitfiled. */
|
||||
|
||||
/* i186 or better required */
|
||||
#define Cpu186 0
|
||||
/* i286 or better required */
|
||||
#define Cpu286 (Cpu186 + 1)
|
||||
/* i386 or better required */
|
||||
#define Cpu386 (Cpu286 + 1)
|
||||
/* i486 or better required */
|
||||
#define Cpu486 (Cpu386 + 1)
|
||||
/* i585 or better required */
|
||||
#define Cpu586 (Cpu486 + 1)
|
||||
/* i686 or better required */
|
||||
#define Cpu686 (Cpu586 + 1)
|
||||
/* Pentium4 or better required */
|
||||
#define CpuP4 (Cpu686 + 1)
|
||||
/* AMD K6 or better required*/
|
||||
#define CpuK6 (CpuP4 + 1)
|
||||
/* AMD K8 or better required */
|
||||
#define CpuK8 (CpuK6 + 1)
|
||||
/* MMX support required */
|
||||
#define CpuMMX (CpuK8 + 1)
|
||||
/* extended MMX support (with SSE or 3DNow!Ext) required */
|
||||
#define CpuMMX2 (CpuMMX + 1)
|
||||
/* SSE support required */
|
||||
#define CpuSSE (CpuMMX2 + 1)
|
||||
/* SSE2 support required */
|
||||
#define CpuSSE2 (CpuSSE + 1)
|
||||
/* 3dnow! support required */
|
||||
#define Cpu3dnow (CpuSSE2 + 1)
|
||||
/* 3dnow! Extensions support required */
|
||||
#define Cpu3dnowA (Cpu3dnow + 1)
|
||||
/* SSE3 support required */
|
||||
#define CpuSSE3 (Cpu3dnowA + 1)
|
||||
/* VIA PadLock required */
|
||||
#define CpuPadLock (CpuSSE3 + 1)
|
||||
/* AMD Secure Virtual Machine Ext-s required */
|
||||
#define CpuSVME (CpuPadLock + 1)
|
||||
/* VMX Instructions required */
|
||||
#define CpuVMX (CpuSVME + 1)
|
||||
/* SSSE3 support required */
|
||||
#define CpuSSSE3 (CpuVMX + 1)
|
||||
/* SSE4a support required */
|
||||
#define CpuSSE4a (CpuSSSE3 + 1)
|
||||
/* ABM New Instructions required */
|
||||
#define CpuABM (CpuSSE4a + 1)
|
||||
/* SSE4.1 support required */
|
||||
#define CpuSSE4_1 (CpuABM + 1)
|
||||
/* SSE4.2 support required */
|
||||
#define CpuSSE4_2 (CpuSSE4_1 + 1)
|
||||
/* 64bit support available, used by -march= in assembler. */
|
||||
#define CpuLM (CpuSSE4_2 + 1)
|
||||
/* 64bit support required */
|
||||
#define Cpu64 (CpuLM + 1)
|
||||
/* Not supported in the 64bit mode */
|
||||
#define CpuNo64 (Cpu64 + 1)
|
||||
/* The last bitfield in i386_cpu_flags. */
|
||||
#define CpuMax CpuNo64
|
||||
|
||||
#define CpuNumOfUints \
|
||||
(CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
|
||||
#define CpuNumOfBits \
|
||||
(CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
|
||||
|
||||
/* If you get a compiler error for zero width of the unused field,
|
||||
comment it out. */
|
||||
#define CpuUnused (CpuNo64 + 1)
|
||||
|
||||
/* We can check if an instruction is available with array instead
|
||||
of bitfield. */
|
||||
typedef union i386_cpu_flags
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int cpui186:1;
|
||||
unsigned int cpui286:1;
|
||||
unsigned int cpui386:1;
|
||||
unsigned int cpui486:1;
|
||||
unsigned int cpui586:1;
|
||||
unsigned int cpui686:1;
|
||||
unsigned int cpup4:1;
|
||||
unsigned int cpuk6:1;
|
||||
unsigned int cpuk8:1;
|
||||
unsigned int cpummx:1;
|
||||
unsigned int cpummx2:1;
|
||||
unsigned int cpusse:1;
|
||||
unsigned int cpusse2:1;
|
||||
unsigned int cpua3dnow:1;
|
||||
unsigned int cpua3dnowa:1;
|
||||
unsigned int cpusse3:1;
|
||||
unsigned int cpupadlock:1;
|
||||
unsigned int cpusvme:1;
|
||||
unsigned int cpuvmx:1;
|
||||
unsigned int cpussse3:1;
|
||||
unsigned int cpusse4a:1;
|
||||
unsigned int cpuabm:1;
|
||||
unsigned int cpusse4_1:1;
|
||||
unsigned int cpusse4_2:1;
|
||||
unsigned int cpulm:1;
|
||||
unsigned int cpu64:1;
|
||||
unsigned int cpuno64:1;
|
||||
#ifdef CpuUnused
|
||||
unsigned int unused:(CpuNumOfBits - CpuUnused);
|
||||
#endif
|
||||
} bitfield;
|
||||
unsigned int array[CpuNumOfUints];
|
||||
} i386_cpu_flags;
|
||||
|
||||
/* Position of opcode_modifier bits. */
|
||||
|
||||
/* has direction bit. */
|
||||
#define D 0
|
||||
/* set if operands can be words or dwords encoded the canonical way */
|
||||
#define W (D + 1)
|
||||
/* insn has a modrm byte. */
|
||||
#define Modrm (W + 1)
|
||||
/* register is in low 3 bits of opcode */
|
||||
#define ShortForm (Modrm + 1)
|
||||
/* special case for jump insns. */
|
||||
#define Jump (ShortForm + 1)
|
||||
/* call and jump */
|
||||
#define JumpDword (Jump + 1)
|
||||
/* loop and jecxz */
|
||||
#define JumpByte (JumpDword + 1)
|
||||
/* special case for intersegment leaps/calls */
|
||||
#define JumpInterSegment (JumpByte + 1)
|
||||
/* FP insn memory format bit, sized by 0x4 */
|
||||
#define FloatMF (JumpInterSegment + 1)
|
||||
/* src/dest swap for floats. */
|
||||
#define FloatR (FloatMF + 1)
|
||||
/* has float insn direction bit. */
|
||||
#define FloatD (FloatR + 1)
|
||||
/* needs size prefix if in 32-bit mode */
|
||||
#define Size16 (FloatD + 1)
|
||||
/* needs size prefix if in 16-bit mode */
|
||||
#define Size32 (Size16 + 1)
|
||||
/* needs size prefix if in 64-bit mode */
|
||||
#define Size64 (Size32 + 1)
|
||||
/* instruction ignores operand size prefix */
|
||||
#define IgnoreSize (Size64 + 1)
|
||||
/* default insn size depends on mode */
|
||||
#define DefaultSize (IgnoreSize + 1)
|
||||
/* b suffix on instruction illegal */
|
||||
#define No_bSuf (DefaultSize + 1)
|
||||
/* w suffix on instruction illegal */
|
||||
#define No_wSuf (No_bSuf + 1)
|
||||
/* l suffix on instruction illegal */
|
||||
#define No_lSuf (No_wSuf + 1)
|
||||
/* s suffix on instruction illegal */
|
||||
#define No_sSuf (No_lSuf + 1)
|
||||
/* q suffix on instruction illegal */
|
||||
#define No_qSuf (No_sSuf + 1)
|
||||
/* x suffix on instruction illegal */
|
||||
#define No_xSuf (No_qSuf + 1)
|
||||
/* instruction needs FWAIT */
|
||||
#define FWait (No_xSuf + 1)
|
||||
/* quick test for string instructions */
|
||||
#define IsString (FWait + 1)
|
||||
/* fake an extra reg operand for clr, imul and special register
|
||||
processing for some instructions. */
|
||||
#define RegKludge (IsString + 1)
|
||||
/* opcode is a prefix */
|
||||
#define IsPrefix (RegKludge + 1)
|
||||
/* instruction has extension in 8 bit imm */
|
||||
#define ImmExt (IsPrefix + 1)
|
||||
/* instruction don't need Rex64 prefix. */
|
||||
#define NoRex64 (ImmExt + 1)
|
||||
/* instruction require Rex64 prefix. */
|
||||
#define Rex64 (NoRex64 + 1)
|
||||
/* deprecated fp insn, gets a warning */
|
||||
#define Ugh (Rex64 + 1)
|
||||
/* The last bitfield in i386_opcode_modifier. */
|
||||
#define Opcode_Modifier_Max Ugh
|
||||
|
||||
typedef struct i386_opcode_modifier
|
||||
{
|
||||
unsigned int d:1;
|
||||
unsigned int w:1;
|
||||
unsigned int modrm:1;
|
||||
unsigned int shortform:1;
|
||||
unsigned int jump:1;
|
||||
unsigned int jumpdword:1;
|
||||
unsigned int jumpbyte:1;
|
||||
unsigned int jumpintersegment:1;
|
||||
unsigned int floatmf:1;
|
||||
unsigned int floatr:1;
|
||||
unsigned int floatd:1;
|
||||
unsigned int size16:1;
|
||||
unsigned int size32:1;
|
||||
unsigned int size64:1;
|
||||
unsigned int ignoresize:1;
|
||||
unsigned int defaultsize:1;
|
||||
unsigned int no_bsuf:1;
|
||||
unsigned int no_wsuf:1;
|
||||
unsigned int no_lsuf:1;
|
||||
unsigned int no_ssuf:1;
|
||||
unsigned int no_qsuf:1;
|
||||
unsigned int no_xsuf:1;
|
||||
unsigned int fwait:1;
|
||||
unsigned int isstring:1;
|
||||
unsigned int regkludge:1;
|
||||
unsigned int isprefix:1;
|
||||
unsigned int immext:1;
|
||||
unsigned int norex64:1;
|
||||
unsigned int rex64:1;
|
||||
unsigned int ugh:1;
|
||||
} i386_opcode_modifier;
|
||||
|
||||
/* Position of operand_type bits. */
|
||||
|
||||
/* Registers */
|
||||
|
||||
/* 8 bit reg */
|
||||
#define Reg8 0
|
||||
/* 16 bit reg */
|
||||
#define Reg16 (Reg8 + 1)
|
||||
/* 32 bit reg */
|
||||
#define Reg32 (Reg16 + 1)
|
||||
/* 64 bit reg */
|
||||
#define Reg64 (Reg32 + 1)
|
||||
|
||||
/* immediate */
|
||||
|
||||
/* 8 bit immediate */
|
||||
#define Imm8 (Reg64 + 1)
|
||||
/* 8 bit immediate sign extended */
|
||||
#define Imm8S (Imm8 + 1)
|
||||
/* 16 bit immediate */
|
||||
#define Imm16 (Imm8S + 1)
|
||||
/* 32 bit immediate */
|
||||
#define Imm32 (Imm16 + 1)
|
||||
/* 32 bit immediate sign extended */
|
||||
#define Imm32S (Imm32 + 1)
|
||||
/* 64 bit immediate */
|
||||
#define Imm64 (Imm32S + 1)
|
||||
/* 1 bit immediate */
|
||||
#define Imm1 (Imm64 + 1)
|
||||
|
||||
/* memory */
|
||||
|
||||
#define BaseIndex (Imm1 + 1)
|
||||
/* Disp8,16,32 are used in different ways, depending on the
|
||||
instruction. For jumps, they specify the size of the PC relative
|
||||
displacement, for baseindex type instructions, they specify the
|
||||
size of the offset relative to the base register, and for memory
|
||||
offset instructions such as `mov 1234,%al' they specify the size of
|
||||
the offset relative to the segment base. */
|
||||
/* 8 bit displacement */
|
||||
#define Disp8 (BaseIndex + 1)
|
||||
/* 16 bit displacement */
|
||||
#define Disp16 (Disp8 + 1)
|
||||
/* 32 bit displacement */
|
||||
#define Disp32 (Disp16 + 1)
|
||||
/* 32 bit signed displacement */
|
||||
#define Disp32S (Disp32 + 1)
|
||||
/* 64 bit displacement */
|
||||
#define Disp64 (Disp32S + 1)
|
||||
|
||||
/* specials */
|
||||
|
||||
/* register to hold in/out port addr = dx */
|
||||
#define InOutPortReg (Disp64 + 1)
|
||||
/* register to hold shift count = cl */
|
||||
#define ShiftCount (InOutPortReg + 1)
|
||||
/* Control register */
|
||||
#define Control (ShiftCount + 1)
|
||||
/* Debug register */
|
||||
#define Debug (Control + 1)
|
||||
/* Test register */
|
||||
#define Test (Debug + 1)
|
||||
/* Float register */
|
||||
#define FloatReg (Test + 1)
|
||||
/* Float stack top %st(0) */
|
||||
#define FloatAcc (FloatReg + 1)
|
||||
/* 2 bit segment register */
|
||||
#define SReg2 (FloatAcc + 1)
|
||||
/* 3 bit segment register */
|
||||
#define SReg3 (SReg2 + 1)
|
||||
/* Accumulator %al or %ax or %eax */
|
||||
#define Acc (SReg3 + 1)
|
||||
#define JumpAbsolute (Acc + 1)
|
||||
/* MMX register */
|
||||
#define RegMMX (JumpAbsolute + 1)
|
||||
/* XMM registers in PIII */
|
||||
#define RegXMM (RegMMX + 1)
|
||||
/* String insn operand with fixed es segment */
|
||||
#define EsSeg (RegXMM + 1)
|
||||
|
||||
/* RegMem is for instructions with a modrm byte where the register
|
||||
destination operand should be encoded in the mod and regmem fields.
|
||||
Normally, it will be encoded in the reg field. We add a RegMem
|
||||
flag to the destination register operand to indicate that it should
|
||||
be encoded in the regmem field. */
|
||||
#define RegMem (EsSeg + 1)
|
||||
|
||||
/* The last bitfield in i386_operand_type. */
|
||||
#define OTMax RegMem
|
||||
|
||||
#define OTNumOfUints \
|
||||
(OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
|
||||
#define OTNumOfBits \
|
||||
(OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
|
||||
|
||||
/* If you get a compiler error for zero width of the unused field,
|
||||
comment it out. */
|
||||
#if 0
|
||||
#define OTUnused (RegMem + 1)
|
||||
#endif
|
||||
|
||||
typedef union i386_operand_type
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int reg8:1;
|
||||
unsigned int reg16:1;
|
||||
unsigned int reg32:1;
|
||||
unsigned int reg64:1;
|
||||
unsigned int imm8:1;
|
||||
unsigned int imm8s:1;
|
||||
unsigned int imm16:1;
|
||||
unsigned int imm32:1;
|
||||
unsigned int imm32s:1;
|
||||
unsigned int imm64:1;
|
||||
unsigned int imm1:1;
|
||||
unsigned int baseindex:1;
|
||||
unsigned int disp8:1;
|
||||
unsigned int disp16:1;
|
||||
unsigned int disp32:1;
|
||||
unsigned int disp32s:1;
|
||||
unsigned int disp64:1;
|
||||
unsigned int inoutportreg:1;
|
||||
unsigned int shiftcount:1;
|
||||
unsigned int control:1;
|
||||
unsigned int debug:1;
|
||||
unsigned int test:1;
|
||||
unsigned int floatreg:1;
|
||||
unsigned int floatacc:1;
|
||||
unsigned int sreg2:1;
|
||||
unsigned int sreg3:1;
|
||||
unsigned int acc:1;
|
||||
unsigned int jumpabsolute:1;
|
||||
unsigned int regmmx:1;
|
||||
unsigned int regxmm:1;
|
||||
unsigned int esseg:1;
|
||||
unsigned int regmem:1;
|
||||
#ifdef OTUnused
|
||||
unsigned int unused:(OTNumOfBits - OTUnused);
|
||||
#endif
|
||||
} bitfield;
|
||||
unsigned int array[OTNumOfUints];
|
||||
} i386_operand_type;
|
||||
|
||||
typedef struct template
|
||||
{
|
||||
@ -46,159 +405,18 @@ typedef struct template
|
||||
#define None 0xffff /* If no extension_opcode is possible. */
|
||||
|
||||
/* cpu feature flags */
|
||||
unsigned int cpu_flags;
|
||||
#define Cpu186 0x1 /* i186 or better required */
|
||||
#define Cpu286 0x2 /* i286 or better required */
|
||||
#define Cpu386 0x4 /* i386 or better required */
|
||||
#define Cpu486 0x8 /* i486 or better required */
|
||||
#define Cpu586 0x10 /* i585 or better required */
|
||||
#define Cpu686 0x20 /* i686 or better required */
|
||||
#define CpuP4 0x40 /* Pentium4 or better required */
|
||||
#define CpuK6 0x80 /* AMD K6 or better required*/
|
||||
#define CpuSledgehammer 0x100 /* Sledgehammer or better required */
|
||||
#define CpuMMX 0x200 /* MMX support required */
|
||||
#define CpuMMX2 0x400 /* extended MMX support (with SSE or 3DNow!Ext) required */
|
||||
#define CpuSSE 0x800 /* Streaming SIMD extensions required */
|
||||
#define CpuSSE2 0x1000 /* Streaming SIMD extensions 2 required */
|
||||
#define Cpu3dnow 0x2000 /* 3dnow! support required */
|
||||
#define Cpu3dnowA 0x4000 /* 3dnow!Extensions support required */
|
||||
#define CpuSSE3 0x8000 /* Streaming SIMD extensions 3 required */
|
||||
#define CpuPadLock 0x10000 /* VIA PadLock required */
|
||||
#define CpuSVME 0x20000 /* AMD Secure Virtual Machine Ext-s required */
|
||||
#define CpuVMX 0x40000 /* VMX Instructions required */
|
||||
#define CpuSSSE3 0x80000 /* Supplemental Streaming SIMD extensions 3 required */
|
||||
#define CpuSSE4a 0x100000 /* SSE4a New Instuctions required */
|
||||
#define CpuABM 0x200000 /* ABM New Instructions required */
|
||||
#define CpuSSE4_1 0x400000 /* SSE4.1 Instructions required */
|
||||
#define CpuSSE4_2 0x800000 /* SSE4.2 Instructions required */
|
||||
|
||||
/* SSE4.1/4.2 Instructions required */
|
||||
#define CpuSSE4 (CpuSSE4_1|CpuSSE4_2)
|
||||
|
||||
/* These flags are set by gas depending on the flag_code. */
|
||||
#define Cpu64 0x4000000 /* 64bit support required */
|
||||
#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
|
||||
|
||||
/* The default value for unknown CPUs - enable all features to avoid problems. */
|
||||
#define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
|
||||
|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \
|
||||
|Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \
|
||||
|CpuSSE4_2|CpuABM|CpuSSE4a)
|
||||
i386_cpu_flags cpu_flags;
|
||||
|
||||
/* the bits in opcode_modifier are used to generate the final opcode from
|
||||
the base_opcode. These bits also are used to detect alternate forms of
|
||||
the same instruction */
|
||||
unsigned int opcode_modifier;
|
||||
|
||||
/* opcode_modifier bits: */
|
||||
#define D 0x1 /* has direction bit. */
|
||||
#define W 0x2 /* set if operands can be words or dwords
|
||||
encoded the canonical way */
|
||||
#define Modrm 0x4 /* insn has a modrm byte. */
|
||||
#define ShortForm 0x8 /* register is in low 3 bits of opcode */
|
||||
#define Jump 0x10 /* special case for jump insns. */
|
||||
#define JumpDword 0x20 /* call and jump */
|
||||
#define JumpByte 0x40 /* loop and jecxz */
|
||||
#define JumpInterSegment 0x80 /* special case for intersegment leaps/calls */
|
||||
#define FloatMF 0x100 /* FP insn memory format bit, sized by 0x4 */
|
||||
#define FloatR 0x200 /* src/dest swap for floats. */
|
||||
#define FloatD 0x400 /* has float insn direction bit. */
|
||||
#define Size16 0x800 /* needs size prefix if in 32-bit mode */
|
||||
#define Size32 0x1000 /* needs size prefix if in 16-bit mode */
|
||||
#define Size64 0x2000 /* needs size prefix if in 64-bit mode */
|
||||
#define IgnoreSize 0x4000 /* instruction ignores operand size prefix */
|
||||
#define DefaultSize 0x8000 /* default insn size depends on mode */
|
||||
#define No_bSuf 0x10000 /* b suffix on instruction illegal */
|
||||
#define No_wSuf 0x20000 /* w suffix on instruction illegal */
|
||||
#define No_lSuf 0x40000 /* l suffix on instruction illegal */
|
||||
#define No_sSuf 0x80000 /* s suffix on instruction illegal */
|
||||
#define No_qSuf 0x100000 /* q suffix on instruction illegal */
|
||||
#define No_xSuf 0x200000 /* x suffix on instruction illegal */
|
||||
#define FWait 0x400000 /* instruction needs FWAIT */
|
||||
#define IsString 0x800000 /* quick test for string instructions */
|
||||
#define RegKludge 0x1000000 /* fake an extra reg operand for clr, imul
|
||||
and special register processing for
|
||||
some instructions. */
|
||||
#define IsPrefix 0x2000000 /* opcode is a prefix */
|
||||
#define ImmExt 0x4000000 /* instruction has extension in 8 bit imm */
|
||||
#define NoRex64 0x8000000 /* instruction don't need Rex64 prefix. */
|
||||
#define Rex64 0x10000000 /* instruction require Rex64 prefix. */
|
||||
#define Ugh 0x20000000 /* deprecated fp insn, gets a warning */
|
||||
i386_opcode_modifier opcode_modifier;
|
||||
|
||||
/* operand_types[i] describes the type of operand i. This is made
|
||||
by OR'ing together all of the possible type masks. (e.g.
|
||||
'operand_types[i] = Reg|Imm' specifies that operand i can be
|
||||
either a register or an immediate operand. */
|
||||
unsigned int operand_types[MAX_OPERANDS];
|
||||
|
||||
/* operand_types[i] bits */
|
||||
/* register */
|
||||
#define Reg8 0x1 /* 8 bit reg */
|
||||
#define Reg16 0x2 /* 16 bit reg */
|
||||
#define Reg32 0x4 /* 32 bit reg */
|
||||
#define Reg64 0x8 /* 64 bit reg */
|
||||
/* immediate */
|
||||
#define Imm8 0x10 /* 8 bit immediate */
|
||||
#define Imm8S 0x20 /* 8 bit immediate sign extended */
|
||||
#define Imm16 0x40 /* 16 bit immediate */
|
||||
#define Imm32 0x80 /* 32 bit immediate */
|
||||
#define Imm32S 0x100 /* 32 bit immediate sign extended */
|
||||
#define Imm64 0x200 /* 64 bit immediate */
|
||||
#define Imm1 0x400 /* 1 bit immediate */
|
||||
/* memory */
|
||||
#define BaseIndex 0x800
|
||||
/* Disp8,16,32 are used in different ways, depending on the
|
||||
instruction. For jumps, they specify the size of the PC relative
|
||||
displacement, for baseindex type instructions, they specify the
|
||||
size of the offset relative to the base register, and for memory
|
||||
offset instructions such as `mov 1234,%al' they specify the size of
|
||||
the offset relative to the segment base. */
|
||||
#define Disp8 0x1000 /* 8 bit displacement */
|
||||
#define Disp16 0x2000 /* 16 bit displacement */
|
||||
#define Disp32 0x4000 /* 32 bit displacement */
|
||||
#define Disp32S 0x8000 /* 32 bit signed displacement */
|
||||
#define Disp64 0x10000 /* 64 bit displacement */
|
||||
/* specials */
|
||||
#define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */
|
||||
#define ShiftCount 0x40000 /* register to hold shift count = cl */
|
||||
#define Control 0x80000 /* Control register */
|
||||
#define Debug 0x100000 /* Debug register */
|
||||
#define Test 0x200000 /* Test register */
|
||||
#define FloatReg 0x400000 /* Float register */
|
||||
#define FloatAcc 0x800000 /* Float stack top %st(0) */
|
||||
#define SReg2 0x1000000 /* 2 bit segment register */
|
||||
#define SReg3 0x2000000 /* 3 bit segment register */
|
||||
#define Acc 0x4000000 /* Accumulator %al or %ax or %eax */
|
||||
#define JumpAbsolute 0x8000000
|
||||
#define RegMMX 0x10000000 /* MMX register */
|
||||
#define RegXMM 0x20000000 /* XMM registers in PIII */
|
||||
#define EsSeg 0x40000000 /* String insn operand with fixed es segment */
|
||||
|
||||
/* RegMem is for instructions with a modrm byte where the register
|
||||
destination operand should be encoded in the mod and regmem fields.
|
||||
Normally, it will be encoded in the reg field. We add a RegMem
|
||||
flag to the destination register operand to indicate that it should
|
||||
be encoded in the regmem field. */
|
||||
#define RegMem 0x80000000
|
||||
|
||||
#define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
|
||||
#define WordReg (Reg16|Reg32|Reg64)
|
||||
#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
|
||||
#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
|
||||
#define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
|
||||
#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
|
||||
#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex) /* General memory */
|
||||
/* The following aliases are defined because the opcode table
|
||||
carefully specifies the allowed memory types for each instruction.
|
||||
At the moment we can only tell a memory reference size by the
|
||||
instruction suffix, so there's not much point in defining Mem8,
|
||||
Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
|
||||
the suffix directly to check memory operands. */
|
||||
#define LLongMem AnyMem /* 64 bits (or more) */
|
||||
#define LongMem AnyMem /* 32 bit memory ref */
|
||||
#define ShortMem AnyMem /* 16 bit memory ref */
|
||||
#define WordMem AnyMem /* 16, 32 or 64 bit memory ref */
|
||||
#define ByteMem AnyMem /* 8 bit memory ref */
|
||||
i386_operand_type operand_types[MAX_OPERANDS];
|
||||
}
|
||||
template;
|
||||
|
||||
@ -208,7 +426,7 @@ extern const template i386_optab[];
|
||||
typedef struct
|
||||
{
|
||||
char *reg_name;
|
||||
unsigned int reg_type;
|
||||
i386_operand_type reg_type;
|
||||
unsigned int reg_flags;
|
||||
#define RegRex 0x1 /* Extended register. */
|
||||
#define RegRex64 0x2 /* Extended 8 bit register. */
|
||||
|
||||
14764
opcodes/i386-tbl.h
14764
opcodes/i386-tbl.h
File diff suppressed because it is too large
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