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gas/testsuite/
2007-10-05 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run smx. * gas/i386/smx.d: New. * gas/i386/smx.s: Likewise. opcodes/ 2007-10-05 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (dis386_twobyte): Add getsec. * i386-gen.c (cpu_flags): Add CpuSMX. * i386-opc.h (CpuSMX): New. (CpuSSSE3): Updated. (i386_cpu_flags): Add cpusmx. * i386-opc.tbl: Add getsec. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
This commit is contained in:
H.J. Lu
parent
768a5a741d
commit
47dd174cba
@ -1,3 +1,10 @@
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2007-10-05 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/i386.exp: Run smx.
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* gas/i386/smx.d: New.
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* gas/i386/smx.s: Likewise.
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2007-10-04 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/simd.s: Add tests for unpckhpd and unpckhps.
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@ -48,6 +48,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "sib"
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run_dump_test "sib-intel"
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run_dump_test "vmx"
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run_dump_test "smx"
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run_dump_test "suffix"
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run_dump_test "immed32"
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run_dump_test "equ"
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10
gas/testsuite/gas/i386/smx.d
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10
gas/testsuite/gas/i386/smx.d
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@ -0,0 +1,10 @@
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#objdump: -dw
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#name: i386 SMX
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.*: +file format .*
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Disassembly of section .text:
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0+000 <foo>:
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[ ]*[a-f0-9]+: 0f 37 getsec
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#pass
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5
gas/testsuite/gas/i386/smx.s
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5
gas/testsuite/gas/i386/smx.s
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@ -0,0 +1,5 @@
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# SMX Instructions
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.text
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foo:
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getsec
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@ -1,3 +1,17 @@
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2007-10-05 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (dis386_twobyte): Add getsec.
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* i386-gen.c (cpu_flags): Add CpuSMX.
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* i386-opc.h (CpuSMX): New.
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(CpuSSSE3): Updated.
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(i386_cpu_flags): Add cpusmx.
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* i386-opc.tbl: Add getsec.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2007-10-05 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (reg_table): Use "{ XX }" on "(bad)".
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@ -1075,7 +1075,7 @@ static const struct dis386 dis386_twobyte[] = {
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{ "sysenter", { XX } },
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{ "sysexit", { XX } },
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "getsec", { XX } },
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/* 38 */
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{ THREE_BYTE_TABLE (THREE_BYTE_0F38) },
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{ "(bad)", { XX } },
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@ -239,6 +239,7 @@ static bitfield cpu_flags[] =
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BITFIELD (CpuPadLock),
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BITFIELD (CpuSVME),
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BITFIELD (CpuVMX),
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BITFIELD (CpuSMX),
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BITFIELD (CpuABM),
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BITFIELD (CpuLM),
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BITFIELD (Cpu64),
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@ -20,143 +20,143 @@
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#define CPU_UNKNOWN_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 0, 1, 1 } }
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1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
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#define CPU_GENERIC32_FLAGS \
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{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_GENERIC64_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_NONE_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I186_FLAGS \
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{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I286_FLAGS \
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{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I386_FLAGS \
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{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I486_FLAGS \
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{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I586_FLAGS \
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{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I686_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_P2_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_P3_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_P4_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_NOCONA_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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#define CPU_CORE_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_CORE2_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, \
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0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
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1, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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#define CPU_K6_FLAGS \
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{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_K6_2_FLAGS \
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{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_ATHLON_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_K8_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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#define CPU_AMDFAM10_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
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1, 1, 0, 0, 0, 1, 0, 0, 0 } }
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0, 1, 1, 0, 0, 0, 1, 0, 0, 0 } }
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#define CPU_MMX_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_SSE_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_SSE2_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_SSE3_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_SSSE3_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
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1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_SSE4_1_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, \
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0, 0, 1, 0, 0, 0, 0, 0, 0 } }
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
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1, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
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#define CPU_SSE4_2_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 1, \
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0, 0, 1, 1, 0, 0, 0, 0, 0 } }
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
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1, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
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#define CPU_3DNOW_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_3DNOWA_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_PADLOCK_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_SVME_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_SSE4A_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
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1, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_ABM_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 1, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_SSE5_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
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1, 1, 0, 0, 1, 0, 0, 0, 0 } }
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0, 1, 1, 0, 0, 1, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_NONE \
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@ -68,8 +68,10 @@
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#define CpuSVME (CpuPadLock + 1)
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/* VMX Instructions required */
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#define CpuVMX (CpuSVME + 1)
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/* SMX Instructions required */
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#define CpuSMX (CpuVMX + 1)
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/* SSSE3 support required */
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#define CpuSSSE3 (CpuVMX + 1)
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#define CpuSSSE3 (CpuSMX + 1)
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/* SSE4a support required */
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#define CpuSSE4a (CpuSSSE3 + 1)
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/* ABM New Instructions required */
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@ -123,6 +125,7 @@ typedef union i386_cpu_flags
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unsigned int cpupadlock:1;
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unsigned int cpusvme:1;
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unsigned int cpuvmx:1;
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unsigned int cpusmx:1;
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unsigned int cpussse3:1;
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unsigned int cpusse4a:1;
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unsigned int cpuabm:1;
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@ -1308,6 +1308,7 @@ mwait, 2, 0xf01, 0xc9, 2, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS
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mwait, 2, 0xf01, 0xc9, 2, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg64, Reg64 }
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// VMX instructions.
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vmcall, 0, 0xf01, 0xc1, 2, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
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vmclear, 1, 0x660fc7, 0x6, 2, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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vmlaunch, 0, 0xf01, 0xc2, 2, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
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@ -1321,6 +1322,10 @@ vmwrite, 2, 0xf79, None, 2, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|
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vmxoff, 0, 0xf01, 0xc4, 2, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
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vmxon, 1, 0xf30fc7, 0x6, 2, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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// SMX instructions.
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getsec, 0, 0xf37, None, 2, CpuSMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 }
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// SSSE3 instructions.
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phaddw, 2, 0xf3801, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX }
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2937
opcodes/i386-tbl.h
2937
opcodes/i386-tbl.h
File diff suppressed because it is too large
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