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sim: bfin: note missing parallel handling of SEARCH

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The SEARCH insn is an oddball when it comes to parallel usage.  It places a
big limit on what other insns it can run in parallel with, but we don't
currently track the amount of state needed to verify this (since no other insn
really requires this).  Add a note for now in case we get around to it.
This commit is contained in:
Mike Frysinger 2013-06-24 02:06:32 +00:00
parent 03dccef1ab
commit 48a9389710
2 changed files with 18 additions and 0 deletions
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5
sim/bfin/ChangeLog
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@ -1,3 +1,8 @@
2013-06-23 Mike Frysinger <vapier@gentoo.org>
* bfin-sim.c (decode_dsp32alu_0): Add note about broken handling of
SEARCH with parallel insns.
2013-06-23 Mike Frysinger <vapier@gentoo.org>
* bfin-sim.c (decode_dsp32shift_0): Make sure HLs is 0 after last

13
sim/bfin/bfin-sim.c
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@ -5148,6 +5148,19 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
TRACE_INSN (cpu, "(R%i, R%i) = SEARCH R%i (%s);",
dst1, dst0, src0, searchmodes[aop]);
/* XXX: The parallel version is a bit weird in its limits:
This instruction can be issued in parallel with the combination of one
16-bit length load instruction to the P0 register and one 16-bit NOP.
No other instructions can be issued in parallel with the Vector Search
instruction. Note the following legal and illegal forms.
(r1, r0) = search r2 (LT) || r2 = [p0++p3]; // ILLEGAL
(r1, r0) = search r2 (LT) || r2 = [p0++]; // LEGAL
(r1, r0) = search r2 (LT) || r2 = [p0++]; // LEGAL
Unfortunately, our parallel insn state doesn't (currently) track enough
details to be able to check this. */
if (dst0 == dst1)
illegal_instruction_combination (cpu);