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Correct test for ISA dependent bits
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@ -450,7 +450,19 @@ typedef struct instruction {
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the normal instruction space. */
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#define MASK_ISA (0x000000FF) /* Start by leaving 8bits for the ISA ID */
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/* The other bits are allocated downwards, to avoid renumbering if we
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have to extend the bits allocated to the pure ISA number. */
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have to extend the bits allocated to the pure ISA number.
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These architecture bits come in two flavors:
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ISA dependent - marking insns that should be included in the opcode
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set if that architecture is requested on the gencode command line
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AND the ISA of the insn is <= requested ISA;
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ISA independent - marking insn that should be included in the opcode
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set if that architecture is requested
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OR the ISA of the insn is <= requested ISA.
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Independent bits are listed in MASK_ISA_INDEP, the rest are dependent.
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*/
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#define ARCH_VR4100 ((unsigned)1 << 31) /* NEC VR4100 extension instructions */
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/* start-sanitize-r5900 */
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#define ARCH_R5900 ((unsigned)1 << 30) /* Toshiba r5900 extension instructions */
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@ -463,7 +475,7 @@ typedef struct instruction {
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/* end-sanitize-r5900 */ \
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| 0)
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#define MASK_ISA_DEP ~(MASK_ISA_INDEP | MASK_ISA)
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/* Very short names for use in the table below to keep it neet. */
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@ -1842,10 +1854,10 @@ process_instructions(doarch,features)
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valid, then if the instruction matches any of the
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architecture specific flags. NOTE: We allow a selected ISA of
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zero to be used to match all standard instructions. */
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if (((MIPS_DECODE[loop].isa & doarch & MASK_ISA_INDEP)
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|| (((MIPS_DECODE[loop].isa & MASK_ISA) <= doisa)
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&& (((MIPS_DECODE[loop].isa & ~MASK_ISA) == 0)
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|| ((MIPS_DECODE[loop].isa & ~MASK_ISA) & doarch) != 0)))
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unsigned int isa = MIPS_DECODE[loop].isa;
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if (((isa & doarch & MASK_ISA_INDEP)
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|| (((isa & MASK_ISA) <= doisa)
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&& (((isa & MASK_ISA_DEP) == 0) || ((isa & MASK_ISA_DEP) & doarch) != 0)))
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&& (!(MIPS_DECODE[loop].flags & FP) || ((MIPS_DECODE[loop].flags & FP) && dofp))) {
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unsigned int onemask;
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unsigned int zeromask;
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