mirror of
https://github.com/darlinghq/darling-gdb.git
synced 2025-02-23 02:51:56 +00:00
o Fixes to repeated watchpoints
o Add mips ISA instructions needed to handle interrupts
This commit is contained in:
Andrew Cagney
parent
f131deb19f
commit
56e7c84918
@ -1,3 +1,28 @@
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Tue Jun 3 04:52:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-watch.c (schedule_watchpoint): Use sim_unschedule_watchpoint
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to remove the old watchpoint, not delete_watchpoint.
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(watch_option_handler): Action the correct watchpoint, not just
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cycles.
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Wed May 28 14:47:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-n-core.h (sim_core_write_aligned_N): For 8byte reads, output
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both low and high word.
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(sim_core_write_aligned_N): Ditto.
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* sim-trace.c (set_trace_options): Delete code explicitly setting
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core->trace.
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* sim-options.c (sim_print_help): Call the list commands if not a
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standalone simulator.
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(sim_print_help): Advise that some options may not be applicable.
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* sim-trace.c (set_trace_options): Assume core present.
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* sim-events.c (sim_events_schedule_after_signal): Overflow signal
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buffer when full not almost full.
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Tue May 27 14:32:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-events.c (sim_events_process): Don't blat the event queue
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@ -1,3 +1,35 @@
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start-sanitize-r5900
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Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (SignalException): Clear the simDELAYSLOT flag when an
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exception has been taken.
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* interp.c: Implement the ERET and mt/f sr instructions.
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Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* gencode.c (build_instruction): For paddu, extract unsigned
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sub-fields.
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* gencode.c (build_instruction): Saturate padds instead of padd
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instructions.
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end-sanitize-r5900
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Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (SignalException): Don't bother restarting an
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interrupt.
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Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (SignalException): Really take an interrupt.
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(interrupt_event): Only deliver interrupts when enabled.
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Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (sim_info): Only print info when verbose.
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(sim_info) Use sim_io_printf for output.
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Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (CoProcPresent): Add UNUSED attribute - not used by all
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@ -192,8 +224,8 @@ Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
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Change values to avoid overloading DOUBLEWORD which is tested
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for all insns.
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* gencode.c: reinstate "offending code".
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end-sanitize-r5900
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end-sanitize-r5900
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Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
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* interp.c: Fix printing of addresses for non-64-bit targets.
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@ -385,6 +385,8 @@ static ut_reg DSPC = 0; /* delay-slot PC */
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#define ksu_user (0x2)
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#define ksu_unknown (0x3)
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#define status_IE (1 << 0) /* Interrupt enable */
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#define status_EXL (1 << 1) /* Exception level */
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#define status_RE (1 << 25) /* Reverse Endian in user mode */
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#define status_FR (1 << 26) /* enables MIPS III additional FP registers */
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#define status_SR (1 << 20) /* soft reset or NMI */
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@ -746,10 +748,18 @@ static const OPTION mips_options[] =
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};
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int interrupt_pending;
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static void
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interrupt_event (SIM_DESC sd, void *data)
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{
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SignalException (Interrupt);
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if (SR & status_IE)
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{
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interrupt_pending = 0;
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SignalException (Interrupt);
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}
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else if (!interrupt_pending)
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sim_events_schedule (sd, 1, interrupt_event, data);
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}
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@ -1240,43 +1250,49 @@ sim_info (sd,verbose)
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SIM_DESC sd;
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int verbose;
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{
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/* Accessed from the GDB "info files" command: */
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callback->printf_filtered(callback,"MIPS %d-bit simulator\n",(PROCESSOR_64BIT ? 64 : 32));
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callback->printf_filtered(callback,"%s endian memory model\n",
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(CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN
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? "Big" : "Little"));
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callback->printf_filtered(callback,"0x%08X bytes of memory at 0x%s\n",
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STATE_MEM_SIZE (sd),
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pr_addr (STATE_MEM_BASE (sd)));
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#if !defined(FASTSIM)
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if (instruction_fetch_overflow != 0)
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callback->printf_filtered(callback,"Instruction fetches = 0x%08X%08X\n",instruction_fetch_overflow,instruction_fetches);
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else
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callback->printf_filtered(callback,"Instruction fetches = %d\n",instruction_fetches);
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callback->printf_filtered(callback,"Pipeline ticks = %ld\n",
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(long) sim_events_time (sd));
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/* It would be a useful feature, if when performing multi-cycle
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simulations (rather than single-stepping) we keep the start and
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end times of the execution, so that we can give a performance
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figure for the simulator. */
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#endif /* !FASTSIM */
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/* print information pertaining to MIPS ISA and architecture being simulated */
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/* things that may be interesting */
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/* instructions executed - if available */
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/* cycles executed - if available */
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/* pipeline stalls - if available */
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/* virtual time taken */
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/* profiling size */
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/* profiling frequency */
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/* profile minpc */
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/* profile maxpc */
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return;
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/* Accessed from the GDB "info files" command: */
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if (STATE_VERBOSE_P (sd) || verbose)
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{
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sim_io_printf (sd, "MIPS %d-bit %s endian simulator\n",
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(PROCESSOR_64BIT ? 64 : 32),
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(CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN ? "Big" : "Little"));
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sim_io_printf (sd, "0x%08X bytes of memory at 0x%s\n",
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STATE_MEM_SIZE (sd),
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pr_addr (STATE_MEM_BASE (sd)));
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#if !defined(FASTSIM)
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#if 0
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/* at present this simulator executes one instruction per
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simulator cycle. Consequently this data never changes */
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if (instruction_fetch_overflow != 0)
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sim_io_printf (sd, "Instruction fetches = 0x%08X%08X\n",
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instruction_fetch_overflow, instruction_fetches);
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else
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sim_io_printf (sd, "Instruction fetches = %d\n", instruction_fetches);
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#endif
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/* It would be a useful feature, if when performing multi-cycle
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simulations (rather than single-stepping) we keep the start and
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end times of the execution, so that we can give a performance
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figure for the simulator. */
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#endif /* !FASTSIM */
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sim_io_printf (sd, "Number of execution cycles = %ld\n",
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(long) sim_events_time (sd));
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/* print information pertaining to MIPS ISA and architecture being simulated */
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/* things that may be interesting */
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/* instructions executed - if available */
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/* cycles executed - if available */
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/* pipeline stalls - if available */
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/* virtual time taken */
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/* profiling size */
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/* profiling frequency */
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/* profile minpc */
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/* profile maxpc */
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}
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}
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SIM_RC
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@ -2731,6 +2747,7 @@ SyncOperation(stype)
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static void
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SignalException (int exception,...)
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{
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int vector;
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SIM_DESC sd = &simulator;
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/* Ensure that any active atomic read/modify/write operation will fail: */
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LLBIT = 0;
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@ -2805,22 +2822,40 @@ SignalException (int exception,...)
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}
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}
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/* See figure 5-17 for an outline of the code below */
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if (! (SR & status_EXL))
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{
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CAUSE = (exception << 2);
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if (state & simDELAYSLOT)
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{
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state &= ~simDELAYSLOT;
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CAUSE |= cause_BD;
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EPC = (IPC - 4); /* reference the branch instruction */
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}
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else
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EPC = IPC;
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/* FIXME: TLB et.al. */
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vector = 0x180;
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}
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else
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{
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CAUSE = 0;
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vector = 0x180;
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}
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SR |= status_EXL;
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/* Store exception code into current exception id variable (used
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by exit code): */
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CAUSE = (exception << 2);
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if (state & simDELAYSLOT) {
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CAUSE |= cause_BD;
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EPC = (IPC - 4); /* reference the branch instruction */
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} else
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EPC = IPC;
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/* The following is so that the simulator will continue from the
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exception address on breakpoint operations. */
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PC = EPC;
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if (SR & status_BEV)
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PC = (signed)0xBFC00200 + 0x180;
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else
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PC = (signed)0x80000000 + 0x180;
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switch ((CAUSE >> 2) & 0x1F)
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{
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case Interrupt:
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sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
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sim_stopped, SIGINT);
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/* Interrupts arrive during event processing, no need to
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restart */
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return;
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case TLBModification:
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case TLBLoad:
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@ -2829,11 +2864,15 @@ SignalException (int exception,...)
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case AddressStore:
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case InstructionFetch:
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case DataReference:
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/* The following is so that the simulator will continue from the
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exception address on breakpoint operations. */
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PC = EPC;
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sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
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sim_stopped, SIGBUS);
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case ReservedInstruction:
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case CoProcessorUnusable:
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PC = EPC;
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sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
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sim_stopped, SIGILL);
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@ -2846,10 +2885,12 @@ SignalException (int exception,...)
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case Watch:
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case SystemCall:
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case BreakPoint:
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PC = EPC;
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sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
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sim_stopped, SIGTRAP);
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default : /* Unknown internal exception */
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PC = EPC;
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sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
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sim_stopped, SIGQUIT);
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@ -4026,85 +4067,105 @@ decode_coproc(instruction)
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{
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int coprocnum = ((instruction >> 26) & 3);
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switch (coprocnum) {
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switch (coprocnum)
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{
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case 0: /* standard CPU control and cache registers */
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{
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/* NOTEs:
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Standard CP0 registers
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0 = Index R4000 VR4100 VR4300
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1 = Random R4000 VR4100 VR4300
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2 = EntryLo0 R4000 VR4100 VR4300
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3 = EntryLo1 R4000 VR4100 VR4300
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4 = Context R4000 VR4100 VR4300
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5 = PageMask R4000 VR4100 VR4300
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6 = Wired R4000 VR4100 VR4300
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8 = BadVAddr R4000 VR4100 VR4300
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9 = Count R4000 VR4100 VR4300
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10 = EntryHi R4000 VR4100 VR4300
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11 = Compare R4000 VR4100 VR4300
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12 = SR R4000 VR4100 VR4300
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13 = Cause R4000 VR4100 VR4300
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14 = EPC R4000 VR4100 VR4300
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15 = PRId R4000 VR4100 VR4300
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16 = Config R4000 VR4100 VR4300
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17 = LLAddr R4000 VR4100 VR4300
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18 = WatchLo R4000 VR4100 VR4300
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19 = WatchHi R4000 VR4100 VR4300
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20 = XContext R4000 VR4100 VR4300
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26 = PErr or ECC R4000 VR4100 VR4300
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27 = CacheErr R4000 VR4100
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28 = TagLo R4000 VR4100 VR4300
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29 = TagHi R4000 VR4100 VR4300
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30 = ErrorEPC R4000 VR4100 VR4300
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*/
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int code = ((instruction >> 21) & 0x1F);
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/* R4000 Users Manual (second edition) lists the following CP0
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instructions:
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DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
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DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
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MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
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MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
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TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
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TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
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TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
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TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
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CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
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ERET Exception return (VR4100 = 01000010000000000000000000011000)
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*/
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if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0)) {
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int rt = ((instruction >> 16) & 0x1F);
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#if 0
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int rd = ((instruction >> 11) & 0x1F);
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#endif
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if (code == 0x00) { /* MF : move from */
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#if 0 /* message should be controlled by configuration option */
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callback->printf_filtered(callback,"Warning: MFC0 %d,%d not handled yet (architecture specific)\n",rt,rd);
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#endif
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GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
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} else { /* MT : move to */
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/* CPR[0,rd] = GPR[rt]; */
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#if 0 /* should be controlled by configuration option */
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callback->printf_filtered(callback,"Warning: MTC0 %d,%d not handled yet (architecture specific)\n",rt,rd);
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#endif
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}
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} else
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sim_warning("Unrecognised COP0 instruction 0x%08X at IPC = 0x%s : No handler present",instruction,pr_addr(IPC));
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DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
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DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
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MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
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MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
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TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
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TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
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TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
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TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
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CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
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ERET Exception return (VR4100 = 01000010000000000000000000011000)
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*/
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if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0))
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{
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int rt = ((instruction >> 16) & 0x1F);
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int rd = ((instruction >> 11) & 0x1F);
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switch (rd) /* NOTEs: Standard CP0 registers */
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{
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/* 0 = Index R4000 VR4100 VR4300 */
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/* 1 = Random R4000 VR4100 VR4300 */
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/* 2 = EntryLo0 R4000 VR4100 VR4300 */
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/* 3 = EntryLo1 R4000 VR4100 VR4300 */
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/* 4 = Context R4000 VR4100 VR4300 */
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/* 5 = PageMask R4000 VR4100 VR4300 */
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/* 6 = Wired R4000 VR4100 VR4300 */
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/* 8 = BadVAddr R4000 VR4100 VR4300 */
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/* 9 = Count R4000 VR4100 VR4300 */
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/* 10 = EntryHi R4000 VR4100 VR4300 */
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/* 11 = Compare R4000 VR4100 VR4300 */
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/* 12 = SR R4000 VR4100 VR4300 */
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case 12:
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if (code == 0x00)
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GPR[rt] = SR;
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else
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SR = GPR[rt];
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break;
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/* 13 = Cause R4000 VR4100 VR4300 */
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/* 14 = EPC R4000 VR4100 VR4300 */
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/* 15 = PRId R4000 VR4100 VR4300 */
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/* 16 = Config R4000 VR4100 VR4300 */
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/* 17 = LLAddr R4000 VR4100 VR4300 */
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/* 18 = WatchLo R4000 VR4100 VR4300 */
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/* 19 = WatchHi R4000 VR4100 VR4300 */
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/* 20 = XContext R4000 VR4100 VR4300 */
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/* 26 = PErr or ECC R4000 VR4100 VR4300 */
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/* 27 = CacheErr R4000 VR4100 */
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/* 28 = TagLo R4000 VR4100 VR4300 */
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/* 29 = TagHi R4000 VR4100 VR4300 */
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/* 30 = ErrorEPC R4000 VR4100 VR4300 */
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GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
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/* CPR[0,rd] = GPR[rt]; */
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default:
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if (code == 0x00)
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callback->printf_filtered(callback,"Warning: MFC0 %d,%d not handled yet (architecture specific)\n",rt,rd);
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else
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callback->printf_filtered(callback,"Warning: MTC0 %d,%d not handled yet (architecture specific)\n",rt,rd);
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}
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}
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else if (code == 0x10 && (instruction & 0x3f) == 0x18)
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{
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/* ERET */
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if (SR & status_ERL)
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{
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/* Oops, not yet available */
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callback->printf_filtered(callback,"Warning: ERET when SR[ERL] set not handled yet");
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PC = EPC;
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SR &= ~status_ERL;
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}
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else
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{
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PC = EPC;
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SR &= ~status_EXL;
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}
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}
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else
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sim_warning("Unrecognised COP0 instruction 0x%08X at IPC = 0x%s : No handler present",instruction,pr_addr(IPC));
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/* TODO: When executing an ERET or RFE instruction we should
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clear LLBIT, to ensure that any out-standing atomic
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read/modify/write sequence fails. */
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}
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break;
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break;
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|
||||
case 2: /* undefined co-processor */
|
||||
sim_warning("COP2 instruction 0x%08X at IPC = 0x%s : No handler present",instruction,pr_addr(IPC));
|
||||
break;
|
||||
|
||||
|
||||
case 1: /* should not occur (FPU co-processor) */
|
||||
case 3: /* should not occur (FPU co-processor) */
|
||||
SignalException(ReservedInstruction,instruction);
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user