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* mips.h (INSN_STORE_MEMORY): Define.

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PR 5433.
This commit is contained in:
Ian Lance Taylor 1994-09-06 15:39:52 +00:00
parent 146d1b553f
commit 57ec4ed5dc
2 changed files with 21 additions and 3 deletions
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8
include/opcode/ChangeLog
View File

@ -1,3 +1,11 @@
Tue Sep 6 11:39:08 1994 Ian Lance Taylor (ian@sanguine.cygnus.com)
* mips.h (INSN_STORE_MEMORY): Define.
Thu Jul 28 19:28:07 1994 Ken Raeburn (raeburn@cujo.cygnus.com)
* sparc.h: Document new operand type 'x'.
Tue Jul 26 17:48:05 1994 Ken Raeburn (raeburn@cujo.cygnus.com) Tue Jul 26 17:48:05 1994 Ken Raeburn (raeburn@cujo.cygnus.com)
* i960.h (I_CX2): New instruction category. * i960.h (I_CX2): New instruction category.

16
include/opcode/mips.h
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@ -62,6 +62,8 @@ Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
#define OP_SH_RT 16 #define OP_SH_RT 16
#define OP_MASK_FT 0x1f #define OP_MASK_FT 0x1f
#define OP_SH_FT 16 #define OP_SH_FT 16
#define OP_MASK_CACHE 0x1f
#define OP_SH_CACHE 16
#define OP_MASK_RD 0x1f #define OP_MASK_RD 0x1f
#define OP_SH_RD 11 #define OP_SH_RD 11
#define OP_MASK_FS 0x1f #define OP_MASK_FS 0x1f
@ -120,12 +122,14 @@ struct mips_opcode
Each of these characters corresponds to a mask field defined above. Each of these characters corresponds to a mask field defined above.
"<" 5 bit shift amount (OP_*_SHAMT) "<" 5 bit shift amount (OP_*_SHAMT)
">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
"a" 26 bit target address (OP_*_TARGET) "a" 26 bit target address (OP_*_TARGET)
"b" 5 bit base register (OP_*_RS) "b" 5 bit base register (OP_*_RS)
"c" 10 bit breakpoint code (OP_*_CODE) "c" 10 bit breakpoint code (OP_*_CODE)
"d" 5 bit destination register specifier (OP_*_RD) "d" 5 bit destination register specifier (OP_*_RD)
"i" 16 bit unsigned immediate (OP_*_IMMEDIATE) "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
"j" 16 bit signed immediate (OP_*_DELTA) "j" 16 bit signed immediate (OP_*_DELTA)
"k" 5 bit cache opcode in target register position (OP_*_CACHE)
"o" 16 bit signed offset (OP_*_DELTA) "o" 16 bit signed offset (OP_*_DELTA)
"p" 16 bit PC relative branch target address (OP_*_DELTA) "p" 16 bit PC relative branch target address (OP_*_DELTA)
"r" 5 bit same register used as both source and target (OP_*_RS) "r" 5 bit same register used as both source and target (OP_*_RS)
@ -137,6 +141,7 @@ struct mips_opcode
"C" 25 bit coprocessor function code (OP_*_COPZ) "C" 25 bit coprocessor function code (OP_*_COPZ)
"B" 20 bit syscall function code (OP_*_SYSCALL) "B" 20 bit syscall function code (OP_*_SYSCALL)
"x" accept and ignore register name "x" accept and ignore register name
"z" must be zero register
Floating point instructions: Floating point instructions:
"D" 5 bit destination register (OP_*_FD) "D" 5 bit destination register (OP_*_FD)
@ -213,7 +218,9 @@ struct mips_opcode
#define INSN_WRITE_HI 0x01000000 #define INSN_WRITE_HI 0x01000000
/* Modifies the LO register. */ /* Modifies the LO register. */
#define INSN_WRITE_LO 0x02000000 #define INSN_WRITE_LO 0x02000000
/* Takes a trap (FIXME: why is this interesting?). */ /* Instruction stores value into memory. */
#define INSN_STORE_MEMORY 0x04000000
/* Takes a trap (easier to keep out of delay slot). */
#define INSN_TRAP 0x04000000 #define INSN_TRAP 0x04000000
/* MIPS ISA 2 instruction (R6000 or R4000). */ /* MIPS ISA 2 instruction (R6000 or R4000). */
#define INSN_ISA2 0x10000000 #define INSN_ISA2 0x10000000
@ -234,7 +241,6 @@ struct mips_opcode
*/ */
enum { enum {
M_ABS, M_ABS,
M_ABSU,
M_ADD_I, M_ADD_I,
M_ADDU_I, M_ADDU_I,
M_AND_I, M_AND_I,
@ -274,6 +280,7 @@ enum {
M_BLTUL_I, M_BLTUL_I,
M_BNE_I, M_BNE_I,
M_BNEL_I, M_BNEL_I,
M_DABS,
M_DADD_I, M_DADD_I,
M_DADDU_I, M_DADDU_I,
M_DDIV_3, M_DDIV_3,
@ -296,9 +303,12 @@ enum {
M_DREMU_3I, M_DREMU_3I,
M_DSUB_I, M_DSUB_I,
M_DSUBU_I, M_DSUBU_I,
M_J_A,
M_JAL_1,
M_JAL_2,
M_JAL_A,
M_L_DOB, M_L_DOB,
M_L_DAB, M_L_DAB,
M_LA,
M_LA_AB, M_LA_AB,
M_LB_A, M_LB_A,
M_LB_AB, M_LB_AB,