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sim: bfin: unify se_all*opcodes tests
The current se_all*opcodes tests are very similar in how they work. In preparation for adding more tests along these lines, unify the common bits into a framework that others can include and build off of easily. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
6aafca16ed
commit
5f2804c950
@ -1,3 +1,9 @@
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2012-03-19 Mike Frysinger <vapier@gentoo.org>
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* se_allopcodes.h: New framework for testing opcode regions.
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* se_all16bitopcodes.S: Convert over to se_allopcodes.h.
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* se_all32bitopcodes.S: Likewise.
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2012-03-19 Stuart Henderson <stuart.henderson@analog.com>
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* c_dsp32shiftim_amix.s: Check edge cases in shift behavior.
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@ -12,122 +12,20 @@
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# sim: --environment operating
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#include "test.h"
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#include "se_allopcodes.h"
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.include "testutils.inc"
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start
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/* Set up exception handler */
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imm32 P4, EVT3;
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loadsym R1, _evx;
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[P4] = R1;
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/* set up the _location */
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loadsym P0, _location
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loadsym P1, _table;
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[P0] = P1;
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/* Enable single stepping */
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R0 = 1;
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SYSCFG = R0;
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/* Lower to the code we want to single step through */
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loadsym P1, _usr;
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RETI = P1;
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/* set up pointers to valid data (32Meg), to reduce address violations */
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.macro reset_regs
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imm32 r0, 0x2000000;
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l0 = 0; l1 = 0; l2 = 0; l3 = 0;
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p0 = r0; p1 = r0; p2 = r0; p3 = r0; p4 = r0; p5 = r0;
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usp = r0; fp = r0;
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i0 = r0; i1 = r0; i2 = r0; i3 = r0;
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b0 = r0; b1 = r0; b2 = r0; b3 = r0;
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.endm
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reset_regs
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RTI;
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.align 4;
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_evx:
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/* Make sure exception reason is single step */
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R3 = SEQSTAT;
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R4 = 0x3f;
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R3 = R3 & R4;
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/* find a match */
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loadsym P5, _usr;
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loadsym P4, _location;
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.macro se_all_load_insn
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R2 = W[P5];
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P1 = [P4];
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R0 = R2;
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_match:
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P2 = P1;
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.endm
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.macro se_all_load_table
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R7 = W[P1++];
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R6 = W[P1++];
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R5 = W[P1++];
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.endm
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/* is this the end of the table? */
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R4 = 0;
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CC = R4 == R7;
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IF CC jump _new_instruction;
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/* is the opcode (R0) greater than the 2nd entry in the table (R6) */
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/* if so look at the next line in the table */
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CC = R6 < R0;
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if CC jump _match;
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/* is the opcode (R0) smaller than the first entry in the table (R7) */
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/* this means it's somewhere between the two lines, and should be legal */
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CC = R7 <= R0;
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if !CC jump _legal_instruction;
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/* is the current EXCAUSE (R3), the same as the table (R5) */
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/* if not, fail */
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CC = R3 == R5
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if !CC jump fail_lvl;
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_match_done:
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/* back up, and store the location to search next */
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[P4] = P2;
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/* it matches, so fall through */
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jump _next_instruction;
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_new_instruction:
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jump _legal_instruction;
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/* output the insn (R0) and excause (R3) if diff from last */
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loadsym P0, _last_excause;
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R2 = [P0];
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CC = R2 == R3;
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IF CC jump _next_instruction;
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[P0] = R3;
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.ifdef BFIN_JTAG_xxxxx
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R1 = R0;
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R0 = 0x4;
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call __emu_out;
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R0 = R1 << 16;
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R0 = R0 | R3;
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call __emu_out;
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.else
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loadsym P0, _next_location;
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P1 = [P0];
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W[P1++] = R0;
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W[P1++] = R3;
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[P0] = P1;
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.endif
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jump _next_instruction;
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_legal_instruction:
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R4 = 0x10;
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CC = R3 == R4;
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IF !CC JUMP fail_lvl;
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/* it wasn't in the list, and was a single step, so fall through */
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_next_instruction:
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.macro se_all_next_insn
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/* increment, and go again. */
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R0 = R2;
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@ -138,44 +36,20 @@ _next_instruction:
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IF CC JUMP pass_lvl;
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W[P5] = R0;
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.endm
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/* Make sure the opcode isn't in a write buffer */
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SSYNC;
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.macro se_all_new_insn_stub
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jump _legal_instruction;
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.endm
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.macro se_all_new_insn_log
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se_all_new_16bit_insn_log
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.endm
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R1 = P5;
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RETX = R1;
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/* set up pointers to valid data (32Meg), to reduce address violations */
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reset_regs
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RETS = r0;
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RETN = r0;
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RETE = r0;
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RETI = r0;
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RTX;
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pass_lvl:
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dbg_pass;
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fail_lvl:
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dbg_fail;
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.section .text.usr
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.align 4
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_usr:
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.macro se_all_insn_init
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.dw 0x0000;
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loadsym P0, fail_lvl;
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JUMP (P0);
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.endm
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.macro se_all_insn_table
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/* this table must be sorted, and end with zero */
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.data
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.align 4;
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_last_excause:
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.dd 0xffff
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_next_location:
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.dd _table_end
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_location:
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.dd 0
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_table:
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/* start end SEQSTAT */
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.dw 0x0001, 0x000f, 0x21
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.dw 0x0011, 0x0013, 0x2e
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@ -475,4 +349,6 @@ _table:
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.dw 0x9ef0, 0x9eff, 0x21
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.dw 0x9f70, 0x9f7f, 0x21
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.dw 0x0000, 0x0000, 0x00
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_table_end:
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.endm
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se_all_test
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@ -14,125 +14,22 @@
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# xfail: too many invalid insns are decoded as valid
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#include "test.h"
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#include "se_allopcodes.h"
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.include "testutils.inc"
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start
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/* Set up exception handler */
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imm32 P4, EVT3;
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loadsym R1, _evx;
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[P4] = R1;
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/* set up the _location */
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loadsym P0, _location
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loadsym P1, _table;
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[P0] = P1;
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/* Enable single stepping */
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R0 = 1;
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SYSCFG = R0;
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/* Lower to the code we want to single step through */
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loadsym P1, _usr;
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RETI = P1;
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/* set up pointers to valid data (32Meg), to reduce address violations */
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.macro reset_regs
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imm32 r0, 0x2000000;
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l0 = 0; l1 = 0; l2 = 0; l3 = 0;
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p0 = r0; p1 = r0; p2 = r0; p3 = r0; p4 = r0; p5 = r0;
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usp = r0; fp = r0;
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i0 = r0; i1 = r0; i2 = r0; i3 = r0;
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b0 = r0; b1 = r0; b2 = r0; b3 = r0;
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.endm
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reset_regs
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RTI;
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.align 4;
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_evx:
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/* Make sure exception reason is single step */
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R3 = SEQSTAT;
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R4 = 0x3f;
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R3 = R3 & R4;
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/* find a match */
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loadsym P5, _usr;
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loadsym P4, _location;
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.macro se_all_load_insn
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R2 = [P5];
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P1 = [P4];
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R0 = R2 << 16;
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R1 = R2 >> 16;
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R0 = R0 | R1;
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_match:
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P2 = P1;
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.endm
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.macro se_all_load_table
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R7 = [P1++];
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R6 = [P1++];
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R5 = [P1++];
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.endm
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/* is this the end of the table? */
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R4 = 0;
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CC = R4 == R7;
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IF CC jump _new_instruction;
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/* is the opcode (R0) greater than the 2nd entry in the table (R6) */
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/* if so look at the next line in the table */
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CC = R6 < R0;
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if CC jump _match;
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/* is the opcode (R0) smaller than the first entry in the table (R7) */
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/* this means it's somewhere between the two lines, and should be legal */
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CC = R7 <= R0;
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if !CC jump _legal_instruction;
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/* is the current EXCAUSE (R3), the same as the table (R5) */
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/* if not, fail */
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CC = R3 == R5
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if !CC jump fail_lvl;
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_match_done:
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/* back up, and store the location to search next */
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[P4] = P2;
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/* it matches, so fall through */
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jump _next_instruction;
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_new_instruction:
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jump fail_lvl;
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/* output the insn (R0) and excause (R3) if diff from last */
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loadsym P0, _last_excause;
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R2 = [P0];
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CC = R2 == R3;
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IF CC jump _next_instruction;
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[P0] = R3;
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.ifdef BFIN_JTAG_xxxxx
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R1 = R0;
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R0 = 0x8;
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call __emu_out;
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R0 = R1;
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call __emu_out;
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R0 = R3;
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call __emu_out;
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.else
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loadsym P0, _next_location;
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P1 = [P0];
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[P1++] = R0;
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[P1++] = R3;
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[P0] = P1;
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.endif
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jump _next_instruction;
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_legal_instruction:
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R4 = 0x10;
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CC = R3 == R4;
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IF !CC JUMP fail_lvl;
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/* it wasn't in the list, and was a single step, so fall through */
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_next_instruction:
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.macro se_all_next_insn
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/* increment, and go again. */
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R0 = R2;
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@ -169,45 +66,21 @@ _next_instruction:
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1:
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[P5] = R0;
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.endm
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/* Make sure the opcode isn't in a write buffer */
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SSYNC;
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.macro se_all_new_insn_stub
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jump fail_lvl;
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.endm
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.macro se_all_new_insn_log
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se_all_new_32bit_insn_log
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.endm
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R1 = P5;
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RETX = R1;
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/* set up pointers to valid data (32Meg), to reduce address violations */
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reset_regs
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RETS = r0;
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RETN = r0;
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RETE = r0;
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RETI = r0;
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RTX;
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pass_lvl:
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dbg_pass;
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fail_lvl:
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dbg_fail;
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.section .text.usr
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.align 4
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_usr:
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.macro se_all_insn_init
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.dw 0xc000;
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.dw 0x0000;
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loadsym P0, fail_lvl;
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JUMP (P0);
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.endm
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.macro se_all_insn_table
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/* this table must be sorted, and end with zero */
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.data
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.align 4;
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_last_excause:
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.dd 0xffff
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_next_location:
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.dd _table_end
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_location:
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.dd 0
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_table:
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/* start end SEQSTAT */
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.dw 0x1a00, 0xc000, 0x1fff, 0xc000, 0x21, 0
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.dw 0x3a00, 0xc000, 0x3fff, 0xc000, 0x21, 0
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@ -34301,4 +34174,6 @@ _table:
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.dw 0x0000, 0xe740, 0xffff, 0xe7ff, 0x21, 0
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.dw 0x0000, 0xf001, 0xffff, 0xffff, 0x21, 0
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.dw 0x0000, 0x0000, 0x0000, 0x0000, 0x00, 0
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_table_end:
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.endm
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se_all_test
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211
sim/testsuite/sim/bfin/se_allopcodes.h
Normal file
211
sim/testsuite/sim/bfin/se_allopcodes.h
Normal file
@ -0,0 +1,211 @@
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/*
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* set up pointers to valid data (32Meg), to reduce address violations
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*/
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.macro reset_dags
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imm32 r0, 0x2000000;
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l0 = 0; l1 = 0; l2 = 0; l3 = 0;
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p0 = r0; p1 = r0; p2 = r0; p3 = r0; p4 = r0; p5 = r0;
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usp = r0; fp = r0;
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i0 = r0; i1 = r0; i2 = r0; i3 = r0;
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b0 = r0; b1 = r0; b2 = r0; b3 = r0;
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.endm
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/*
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* execute a test of an opcode space. host test
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* has to fill out a number of callbacks.
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*
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* se_all_insn_init
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* the first insn to start executing
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* se_all_insn_table
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* the table of insn ranges and expected seqstat
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*
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* se_all_load_insn
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* in: P5
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* out: R0, R2
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* scratch: R1
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* load current user insn via register P5 into R0.
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* register R2 is available for caching with se_all_next_insn.
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* se_all_load_table
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* in: P1
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* out: R7, R6, R5
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* scratch: R1
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* load insn range/seqstat entry from table via register P1
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* R7: low range
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* R6: high range
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* R5: seqstat
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*
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* se_all_next_insn
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* in: P5, R2
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* out: <nothing>
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* scratch: all but P5
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* advance current insn to next one for testing. register R2
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* is retained from se_all_load_insn. write out new insn to
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* the location via register P5.
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*
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* se_all_new_insn_stub
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* se_all_new_insn_log
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* for handling of new insns ... generally not needed once done
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*/
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.macro se_all_test
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start
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/* Set up exception handler */
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imm32 P4, EVT3;
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loadsym R1, _evx;
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[P4] = R1;
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/* set up the _location */
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loadsym P0, _location
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loadsym P1, _table;
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[P0] = P1;
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/* Enable single stepping */
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R0 = 1;
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SYSCFG = R0;
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/* Lower to the code we want to single step through */
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loadsym P1, _usr;
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RETI = P1;
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/* set up pointers to valid data (32Meg), to reduce address violations */
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reset_dags
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RTI;
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pass_lvl:
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dbg_pass;
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fail_lvl:
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dbg_fail;
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_evx:
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/* Make sure exception reason is as we expect */
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R3 = SEQSTAT;
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R4 = 0x3f;
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R3 = R3 & R4;
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/* find a match */
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loadsym P5, _usr;
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loadsym P4, _location;
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P1 = [P4];
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se_all_load_insn
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_match:
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P2 = P1;
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se_all_load_table
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/* is this the end of the table? */
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R4 = 0;
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CC = R4 == R7;
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IF CC jump _new_instruction;
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/* is the opcode (R0) greater than the 2nd entry in the table (R6) */
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/* if so look at the next line in the table */
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CC = R6 < R0;
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if CC jump _match;
|
||||
|
||||
/* is the opcode (R0) smaller than the first entry in the table (R7) */
|
||||
/* this means it's somewhere between the two lines, and should be legal */
|
||||
CC = R7 <= R0;
|
||||
if !CC jump _legal_instruction;
|
||||
|
||||
/* is the current EXCAUSE (R3), the same as the table (R5) */
|
||||
/* if not, fail */
|
||||
CC = R3 == R5
|
||||
if !CC jump fail_lvl;
|
||||
|
||||
_match_done:
|
||||
/* back up, and store the location to search next */
|
||||
[P4] = P2;
|
||||
|
||||
/* it matches, so fall through */
|
||||
jump _next_instruction;
|
||||
|
||||
_new_instruction:
|
||||
se_all_new_insn_stub
|
||||
|
||||
/* output the insn (R0) and excause (R3) if diff from last */
|
||||
loadsym P0, _last_excause;
|
||||
R2 = [P0];
|
||||
CC = R2 == R3;
|
||||
IF CC jump _next_instruction;
|
||||
[P0] = R3;
|
||||
|
||||
se_all_new_insn_log
|
||||
|
||||
_legal_instruction:
|
||||
R4 = 0x10;
|
||||
CC = R3 == R4;
|
||||
IF !CC JUMP fail_lvl;
|
||||
/* it wasn't in the list, and was a single step, so fall through */
|
||||
|
||||
_next_instruction:
|
||||
se_all_next_insn
|
||||
|
||||
/* Make sure the opcode isn't in a write buffer */
|
||||
SSYNC;
|
||||
|
||||
R1 = P5;
|
||||
RETX = R1;
|
||||
|
||||
/* set up pointers to valid data (32Meg), to reduce address violations */
|
||||
reset_dags
|
||||
RETS = r0;
|
||||
RETN = r0;
|
||||
RETE = r0;
|
||||
RETI = r0;
|
||||
|
||||
RTX;
|
||||
|
||||
.section .text.usr
|
||||
.align 4
|
||||
_usr:
|
||||
se_all_insn_init
|
||||
loadsym P0, fail_lvl;
|
||||
JUMP (P0);
|
||||
|
||||
.data
|
||||
.align 4;
|
||||
_last_excause:
|
||||
.dd 0xffff
|
||||
_next_location:
|
||||
.dd _table_end
|
||||
_location:
|
||||
.dd 0
|
||||
_table:
|
||||
se_all_insn_table
|
||||
_table_end:
|
||||
.endm
|
||||
|
||||
.macro se_all_new_16bit_insn_log
|
||||
.ifdef BFIN_JTAG_xxxxx
|
||||
R1 = R0;
|
||||
R0 = 0x4;
|
||||
call __emu_out;
|
||||
R0 = R1 << 16;
|
||||
R0 = R0 | R3;
|
||||
call __emu_out;
|
||||
.else
|
||||
loadsym P0, _next_location;
|
||||
P1 = [P0];
|
||||
W[P1++] = R0;
|
||||
W[P1++] = R3;
|
||||
[P0] = P1;
|
||||
.endif
|
||||
.endm
|
||||
.macro se_all_new_32bit_insn_log
|
||||
.ifdef BFIN_JTAG_xxxxx
|
||||
R1 = R0;
|
||||
R0 = 0x8;
|
||||
call __emu_out;
|
||||
R0 = R1;
|
||||
call __emu_out;
|
||||
R0 = R3;
|
||||
call __emu_out;
|
||||
.else
|
||||
loadsym P0, _next_location;
|
||||
P1 = [P0];
|
||||
[P1++] = R0;
|
||||
[P1++] = R3;
|
||||
[P0] = P1;
|
||||
.endif
|
||||
.endm
|
||||
Loading…
x
Reference in New Issue
Block a user