mirror of
https://github.com/darlinghq/darling-gdb.git
synced 2025-02-10 19:24:29 +00:00
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181, vr5400 and vr5500. Add entry for -mfix-vr4122-bugs. * config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros. (hilo_interlocks): True for CPU_VR5500. (gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500. (mips_fix_vr4122_bugs): New. (append_insn): Work around 4122 errors if mips_fix_vr4122_bugs. (mips_emit_delays): Likewise. (macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR. [M_ROLI]: Likewise ror if CPU_HAS_ROR. (validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'. (OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options. (md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs. (OPTION_ELF_BASE): Bump. (md_parse_option): Handle the new options. (mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181, vr5400 and vr5500. [gas/testsuite/] * gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to... * gas/mips/vr4111.[sd]: ...this new test. * gas/mips/vr4120.[sd], * gas/mips/vr4122.[sd], * gas/mips/vr5400.[sd], * gas/mips/vr5500.[sd]: New tests. * mips.exp: Run them.
This commit is contained in:
Richard Sandiford
parent
9752cf1b67
commit
60b63b728f
@ -1,3 +1,29 @@
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2002-09-30 Gavin Romig-Koch <gavin@redhat.com>
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Ken Raeburn <raeburn@cygnus.com>
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Aldy Hernandez <aldyh@redhat.com>
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DJ Delorie <dj@redhat.com>
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Michael Meissner <meissner@redhat.com>
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Eric Christopher <echristo@redhat.com>
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Richard Sandiford <rsandifo@redhat.com>
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* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
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vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
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* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
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(hilo_interlocks): True for CPU_VR5500.
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(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
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(mips_fix_vr4122_bugs): New.
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(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
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(mips_emit_delays): Likewise.
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(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
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[M_ROLI]: Likewise ror if CPU_HAS_ROR.
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(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
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(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
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(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
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(OPTION_ELF_BASE): Bump.
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(md_parse_option): Handle the new options.
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(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
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vr5400 and vr5500.
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2002-09-29 H.J. Lu <hjl@gnu.org>
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* config/tc-mips.c (md_apply_fix3): Subtract the symbol value
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@ -296,11 +296,18 @@ static int mips_32bitmode = 0;
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#define CPU_HAS_MDMX(cpu) (false \
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)
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/* True if CPU has a dror instruction. */
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#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
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/* True if CPU has a ror instruction. */
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#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
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/* Whether the processor uses hardware interlocks to protect
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reads from the HI and LO registers, and thus does not
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require nops to be inserted. */
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#define hilo_interlocks (mips_arch == CPU_R4010 \
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|| mips_arch == CPU_VR5500 \
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|| mips_arch == CPU_SB1 \
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)
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@ -308,12 +315,16 @@ static int mips_32bitmode = 0;
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from the GPRs, and thus does not require nops to be inserted. */
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#define gpr_interlocks \
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(mips_opts.isa != ISA_MIPS1 \
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|| mips_arch == CPU_VR5400 \
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|| mips_arch == CPU_VR5500 \
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|| mips_arch == CPU_R3900)
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/* As with other "interlocks" this is used by hardware that has FP
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(co-processor) interlocks. */
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/* Itbl support may require additional care here. */
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#define cop_interlocks (mips_arch == CPU_R4300 \
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|| mips_arch == CPU_VR5400 \
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|| mips_arch == CPU_VR5500 \
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|| mips_arch == CPU_SB1 \
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)
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@ -550,6 +561,8 @@ static const unsigned int mips16_to_32_reg_map[] =
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{
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16, 17, 2, 3, 4, 5, 6, 7
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};
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static int mips_fix_4122_bugs;
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/* Since the MIPS does not have multiple forms of PC relative
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instructions, we do not have to do relaxing as is done on other
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@ -1689,6 +1702,50 @@ append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
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if (prev_prev_nop && nops == 0)
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++nops;
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if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
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{
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/* We're out of bits in pinfo, so we must resort to string
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ops here. Shortcuts are selected based on opcodes being
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limited to the VR4122 instruction set. */
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int min_nops = 0;
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const char *pn = prev_insn.insn_mo->name;
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const char *tn = ip->insn_mo->name;
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if (strncmp(pn, "macc", 4) == 0
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|| strncmp(pn, "dmacc", 5) == 0)
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{
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/* Errata 21 - [D]DIV[U] after [D]MACC */
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if (strstr (tn, "div"))
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{
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min_nops = 1;
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}
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/* Errata 23 - Continuous DMULT[U]/DMACC instructions */
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if (pn[0] == 'd' /* dmacc */
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&& (strncmp(tn, "dmult", 5) == 0
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|| strncmp(tn, "dmacc", 5) == 0))
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{
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min_nops = 1;
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}
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/* Errata 24 - MT{LO,HI} after [D]MACC */
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if (strcmp (tn, "mtlo") == 0
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|| strcmp (tn, "mthi") == 0)
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{
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min_nops = 1;
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}
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}
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else if (strncmp(pn, "dmult", 5) == 0
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&& (strncmp(tn, "dmult", 5) == 0
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|| strncmp(tn, "dmacc", 5) == 0))
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{
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/* Here is the rest of errata 23. */
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min_nops = 1;
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}
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if (nops < min_nops)
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nops = min_nops;
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}
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/* If we are being given a nop instruction, don't bother with
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one of the nops we would otherwise output. This will only
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happen when a nop instruction is used with mips_optimize set
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@ -2586,6 +2643,20 @@ mips_emit_delays (insns)
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++nops;
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}
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if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
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{
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int min_nops = 0;
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const char *pn = prev_insn.insn_mo->name;
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if (strncmp(pn, "macc", 4) == 0
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|| strncmp(pn, "dmacc", 5) == 0
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|| strncmp(pn, "dmult", 5) == 0)
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{
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min_nops = 1;
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}
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if (nops < min_nops)
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nops = min_nops;
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}
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if (nops > 0)
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{
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struct insn_label_list *l;
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@ -6714,6 +6785,17 @@ macro2 (ip)
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if (imm_expr.X_op != O_constant)
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as_bad (_("rotate count too large"));
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rot = imm_expr.X_add_number & 0x3f;
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if (CPU_HAS_DROR (mips_arch))
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{
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rot = (64 - rot) & 0x3f;
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if (rot >= 32)
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macro_build ((char *) NULL, &icnt, NULL, "dror32",
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"d,w,<", dreg, sreg, rot - 32);
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else
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macro_build ((char *) NULL, &icnt, NULL, "dror",
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"d,w,<", dreg, sreg, rot);
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break;
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}
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if (rot == 0)
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
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"d,w,<", dreg, sreg, 0);
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@ -6741,6 +6823,12 @@ macro2 (ip)
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if (imm_expr.X_op != O_constant)
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as_bad (_("rotate count too large"));
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rot = imm_expr.X_add_number & 0x1f;
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if (CPU_HAS_ROR (mips_arch))
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{
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macro_build ((char *) NULL, &icnt, NULL, "ror",
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"d,w,<", dreg, sreg, (32 - rot) & 0x1f);
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break;
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}
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if (rot == 0)
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
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"d,w,<", dreg, sreg, 0);
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@ -7716,6 +7804,10 @@ validate_mips_insn (opc)
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case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
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case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
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USE_BITS (OP_MASK_RT, OP_SH_RT); break;
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case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
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case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
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case '[': break;
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case ']': break;
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default:
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as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
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c, opc->name, opc->args);
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@ -7907,6 +7999,8 @@ mips_ip (str, ip)
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return;
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case ')': /* these must match exactly */
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case '[':
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case ']':
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if (*s++ == *args)
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continue;
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break;
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@ -8828,6 +8922,41 @@ mips_ip (str, ip)
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ip->insn_opcode |= c;
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continue;
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case 'e':
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/* Must be at least one digit. */
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my_getExpression (&imm_expr, s);
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check_absolute_expr (ip, &imm_expr);
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if ((unsigned long) imm_expr.X_add_number
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> (unsigned long) OP_MASK_VECBYTE)
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{
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as_bad (_("bad byte vector index (%ld)"),
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(long) imm_expr.X_add_number);
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imm_expr.X_add_number = 0;
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}
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ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
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imm_expr.X_op = O_absent;
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s = expr_end;
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continue;
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case '%':
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my_getExpression (&imm_expr, s);
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check_absolute_expr (ip, &imm_expr);
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if ((unsigned long) imm_expr.X_add_number
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> (unsigned long) OP_MASK_VECALIGN)
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{
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as_bad (_("bad byte vector index (%ld)"),
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(long) imm_expr.X_add_number);
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imm_expr.X_add_number = 0;
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}
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ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
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imm_expr.X_op = O_absent;
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s = expr_end;
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continue;
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default:
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as_bad (_("bad char = '%c'\n"), *args);
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internalError ();
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@ -9992,8 +10121,12 @@ struct option md_longopts[] =
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{"mdmx", no_argument, NULL, OPTION_MDMX},
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#define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
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{"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
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#define OPTION_FIX_VR4122 (OPTION_MD_BASE + 37)
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#define OPTION_NO_FIX_VR4122 (OPTION_MD_BASE + 38)
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{"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122},
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{"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122},
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#ifdef OBJ_ELF
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#define OPTION_ELF_BASE (OPTION_MD_BASE + 37)
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#define OPTION_ELF_BASE (OPTION_MD_BASE + 39)
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#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
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{"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
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{"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
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@ -10194,6 +10327,14 @@ md_parse_option (c, arg)
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g_switch_value = 0x7fffffff;
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break;
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case OPTION_FIX_VR4122:
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mips_fix_4122_bugs = 1;
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break;
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case OPTION_NO_FIX_VR4122:
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mips_fix_4122_bugs = 0;
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break;
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#ifdef OBJ_ELF
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/* When generating ELF code, we permit -KPIC and -call_shared to
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select SVR4_PIC, and -non_shared to select no PIC. This is
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@ -13644,6 +13785,9 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
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{ "r4010", 0, ISA_MIPS2, CPU_R4010 },
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{ "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
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{ "vr4111", 0, ISA_MIPS3, CPU_R4111 },
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{ "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
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{ "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
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{ "vr4181", 0, ISA_MIPS3, CPU_R4111 },
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{ "vr4300", 0, ISA_MIPS3, CPU_R4300 },
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{ "r4400", 0, ISA_MIPS3, CPU_R4400 },
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{ "r4600", 0, ISA_MIPS3, CPU_R4600 },
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@ -13655,6 +13799,8 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
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{ "r10000", 0, ISA_MIPS4, CPU_R10000 },
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{ "r12000", 0, ISA_MIPS4, CPU_R12000 },
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{ "vr5000", 0, ISA_MIPS4, CPU_R5000 },
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{ "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
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{ "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
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{ "rm5200", 0, ISA_MIPS4, CPU_R5000 },
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{ "rm5230", 0, ISA_MIPS4, CPU_R5000 },
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{ "rm5231", 0, ISA_MIPS4, CPU_R5000 },
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@ -116,6 +116,12 @@ This tells the assembler to accept MDMX instructions.
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Cause nops to be inserted if the read of the destination register
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of an mfhi or mflo instruction occurs in the following two instructions.
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@item -mfix-vr4122-bugs
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@itemx -no-mfix-vr4122-bugs
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Insert @samp{nop} instructions to avoid errors in certain versions of
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the vr4122 core. This option is intended to be used on GCC-generated
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code: it is not designed to catch errors in hand-written assembler code.
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@item -m4010
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@itemx -no-m4010
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Generate code for the LSI @sc{r4010} chip. This tells the assembler to
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@ -152,6 +158,9 @@ understood. Valid @var{cpu} value are:
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4010,
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4100,
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4111,
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vr4120,
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vr4130,
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vr4181,
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4300,
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4400,
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4600,
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@ -162,6 +171,8 @@ rm5230,
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rm5231,
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rm5261,
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rm5721,
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vr5400,
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vr5500,
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6000,
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rm7000,
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8000,
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@ -1,3 +1,19 @@
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2002-09-30 Gavin Romig-Koch <gavin@redhat.com>
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Ken Raeburn <raeburn@cygnus.com>
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Aldy Hernandez <aldyh@redhat.com>
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DJ Delorie <dj@redhat.com>
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Michael Meissner <meissner@redhat.com>
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Eric Christopher <echristo@redhat.com>
|
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Richard Sandiford <rsandifo@redhat.com>
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* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
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* gas/mips/vr4111.[sd]: ...this new test.
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* gas/mips/vr4120.[sd],
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* gas/mips/vr4122.[sd],
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* gas/mips/vr5400.[sd],
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* gas/mips/vr5500.[sd]: New tests.
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* mips.exp: Run them.
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2002-09-27 Kaz Kojima <kkojima@rr.iij4u.or.jp>
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* gas/sh/pcrel2.s: New.
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@ -153,6 +153,11 @@ if { [istarget mips*-*-*] } then {
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run_dump_test "mips4010"
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run_dump_test "mips4650"
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run_dump_test "mips4100"
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run_dump_test "vr4111"
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run_dump_test "vr4120"
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run_dump_test "vr4122"
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run_dump_test "vr5400"
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run_dump_test "vr5500"
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run_dump_test "perfcount"
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run_dump_test "lineno"
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run_dump_test "sync"
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@ -6,10 +6,7 @@
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.*: +file format .*mips.*
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Disassembly of section \.text:
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0+0000 <stuff> dmadd16 a0,a1
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...
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0+000c <stuff\+0xc> madd16 a1,a2
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0+0010 <stuff\+0x10> hibernate
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0+0014 <stuff\+0x14> standby
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0+0018 <stuff\+0x18> suspend
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0+001c <stuff\+0x1c> nop
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0+0000 <stuff> hibernate
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0+0004 <stuff\+0x4> standby
|
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0+0008 <stuff\+0x8> suspend
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0+000c <stuff\+0xc> nop
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@ -2,8 +2,6 @@
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stuff:
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.ent stuff
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dmadd16 $4,$5
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madd16 $5,$6
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hibernate
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standby
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suspend
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11
gas/testsuite/gas/mips/vr4111.d
Normal file
11
gas/testsuite/gas/mips/vr4111.d
Normal file
@ -0,0 +1,11 @@
|
||||
#objdump: -dr
|
||||
#name: MIPS VR4111
|
||||
#as: -march=vr4111
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section \.text:
|
||||
0+000 <\.text>:
|
||||
+ 0: 00850029 dmadd16 a0,a1
|
||||
\.\.\.
|
||||
+ c: 00a60028 madd16 a1,a2
|
||||
2
gas/testsuite/gas/mips/vr4111.s
Normal file
2
gas/testsuite/gas/mips/vr4111.s
Normal file
@ -0,0 +1,2 @@
|
||||
dmadd16 $4,$5
|
||||
madd16 $5,$6
|
||||
29
gas/testsuite/gas/mips/vr4120.d
Normal file
29
gas/testsuite/gas/mips/vr4120.d
Normal file
@ -0,0 +1,29 @@
|
||||
#objdump: -dr
|
||||
#name: MIPS VR4120
|
||||
#as: -march=vr4120
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section \.text:
|
||||
0+000 <\.text>:
|
||||
+ 0: 00002012 mflo a0
|
||||
\.\.\.
|
||||
+ c: 00a62029 dmacc a0,a1,a2
|
||||
+10: 00a62229 dmacchi a0,a1,a2
|
||||
+14: 00a62629 dmacchis a0,a1,a2
|
||||
+18: 00a62269 dmacchiu a0,a1,a2
|
||||
+1c: 00a62669 dmacchius a0,a1,a2
|
||||
+20: 00a62429 dmaccs a0,a1,a2
|
||||
+24: 00a62069 dmaccu a0,a1,a2
|
||||
+28: 00a62469 dmaccus a0,a1,a2
|
||||
+2c: 00002012 mflo a0
|
||||
\.\.\.
|
||||
+38: 00a62028 macc a0,a1,a2
|
||||
+3c: 00a62228 macchi a0,a1,a2
|
||||
+40: 00a62628 macchis a0,a1,a2
|
||||
+44: 00a62268 macchiu a0,a1,a2
|
||||
+48: 00a62668 macchius a0,a1,a2
|
||||
+4c: 00a62428 maccs a0,a1,a2
|
||||
+50: 00a62068 maccu a0,a1,a2
|
||||
+54: 00a62468 maccus a0,a1,a2
|
||||
#...
|
||||
19
gas/testsuite/gas/mips/vr4120.s
Normal file
19
gas/testsuite/gas/mips/vr4120.s
Normal file
@ -0,0 +1,19 @@
|
||||
# Include mflos to check for nop insertion.
|
||||
mflo $4
|
||||
dmacc $4,$5,$6
|
||||
dmacchi $4,$5,$6
|
||||
dmacchis $4,$5,$6
|
||||
dmacchiu $4,$5,$6
|
||||
dmacchius $4,$5,$6
|
||||
dmaccs $4,$5,$6
|
||||
dmaccu $4,$5,$6
|
||||
dmaccus $4,$5,$6
|
||||
mflo $4
|
||||
macc $4,$5,$6
|
||||
macchi $4,$5,$6
|
||||
macchis $4,$5,$6
|
||||
macchiu $4,$5,$6
|
||||
macchius $4,$5,$6
|
||||
maccs $4,$5,$6
|
||||
maccu $4,$5,$6
|
||||
maccus $4,$5,$6
|
||||
68
gas/testsuite/gas/mips/vr4122.d
Normal file
68
gas/testsuite/gas/mips/vr4122.d
Normal file
@ -0,0 +1,68 @@
|
||||
#objdump: -dz --prefix-addresses -m mips:4120
|
||||
#as: -march=vr4120 -mtune=vr4120 -mfix-vr4122-bugs
|
||||
#name: MIPS vr4122 workarounds
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <[^>]*> macc a0,a1,a2
|
||||
0+0004 <[^>]*> nop
|
||||
0+0008 <[^>]*> div zero,a3,t0
|
||||
0+000c <[^>]*> or a0,a0,a1
|
||||
0+0010 <[^>]*> dmacc a0,a1,a2
|
||||
0+0014 <[^>]*> nop
|
||||
0+0018 <[^>]*> div zero,a3,t0
|
||||
0+001c <[^>]*> or a0,a0,a1
|
||||
0+0020 <[^>]*> macc a0,a1,a2
|
||||
0+0024 <[^>]*> nop
|
||||
0+0028 <[^>]*> divu zero,a3,t0
|
||||
0+002c <[^>]*> or a0,a0,a1
|
||||
0+0030 <[^>]*> dmacc a0,a1,a2
|
||||
0+0034 <[^>]*> nop
|
||||
0+0038 <[^>]*> divu zero,a3,t0
|
||||
0+003c <[^>]*> or a0,a0,a1
|
||||
0+0040 <[^>]*> macc a0,a1,a2
|
||||
0+0044 <[^>]*> nop
|
||||
0+0048 <[^>]*> ddiv zero,a3,t0
|
||||
0+004c <[^>]*> or a0,a0,a1
|
||||
0+0050 <[^>]*> dmacc a0,a1,a2
|
||||
0+0054 <[^>]*> nop
|
||||
0+0058 <[^>]*> ddiv zero,a3,t0
|
||||
0+005c <[^>]*> or a0,a0,a1
|
||||
0+0060 <[^>]*> macc a0,a1,a2
|
||||
0+0064 <[^>]*> nop
|
||||
0+0068 <[^>]*> ddivu zero,a3,t0
|
||||
0+006c <[^>]*> or a0,a0,a1
|
||||
0+0070 <[^>]*> dmacc a0,a1,a2
|
||||
0+0074 <[^>]*> nop
|
||||
0+0078 <[^>]*> ddivu zero,a3,t0
|
||||
0+007c <[^>]*> or a0,a0,a1
|
||||
0+0080 <[^>]*> dmult a0,a1
|
||||
0+0084 <[^>]*> nop
|
||||
0+0088 <[^>]*> dmult a2,a3
|
||||
0+008c <[^>]*> or a0,a0,a1
|
||||
0+0090 <[^>]*> dmultu a0,a1
|
||||
0+0094 <[^>]*> nop
|
||||
0+0098 <[^>]*> dmultu a2,a3
|
||||
0+009c <[^>]*> or a0,a0,a1
|
||||
0+00a0 <[^>]*> dmacc a0,a1,a2
|
||||
0+00a4 <[^>]*> nop
|
||||
0+00a8 <[^>]*> dmacc a2,a3,t0
|
||||
0+00ac <[^>]*> or a0,a0,a1
|
||||
0+00b0 <[^>]*> dmult a0,a1
|
||||
0+00b4 <[^>]*> nop
|
||||
0+00b8 <[^>]*> dmacc a2,a3,t0
|
||||
0+00bc <[^>]*> or a0,a0,a1
|
||||
0+00c0 <[^>]*> macc a0,a1,a2
|
||||
0+00c4 <[^>]*> nop
|
||||
0+00c8 <[^>]*> mtlo a3
|
||||
0+00cc <[^>]*> dmacc a0,a1,a2
|
||||
0+00d0 <[^>]*> nop
|
||||
0+00d4 <[^>]*> mtlo a3
|
||||
0+00d8 <[^>]*> macc a0,a1,a2
|
||||
0+00dc <[^>]*> nop
|
||||
0+00e0 <[^>]*> mthi a3
|
||||
0+00e4 <[^>]*> dmacc a0,a1,a2
|
||||
0+00e8 <[^>]*> nop
|
||||
0+00ec <[^>]*> mthi a3
|
||||
#...
|
||||
65
gas/testsuite/gas/mips/vr4122.s
Normal file
65
gas/testsuite/gas/mips/vr4122.s
Normal file
@ -0,0 +1,65 @@
|
||||
# Test that certain vr4122 hardware bugs are worked around.
|
||||
# Note that we only work around bugs gcc may generate.
|
||||
|
||||
r21:
|
||||
macc $4,$5,$6
|
||||
div $0,$7,$8
|
||||
or $4,$5
|
||||
|
||||
dmacc $4,$5,$6
|
||||
div $0,$7,$8
|
||||
or $4,$5
|
||||
|
||||
macc $4,$5,$6
|
||||
divu $0,$7,$8
|
||||
or $4,$5
|
||||
|
||||
dmacc $4,$5,$6
|
||||
divu $0,$7,$8
|
||||
or $4,$5
|
||||
|
||||
macc $4,$5,$6
|
||||
ddiv $0,$7,$8
|
||||
or $4,$5
|
||||
|
||||
dmacc $4,$5,$6
|
||||
ddiv $0,$7,$8
|
||||
or $4,$5
|
||||
|
||||
macc $4,$5,$6
|
||||
ddivu $0,$7,$8
|
||||
or $4,$5
|
||||
|
||||
dmacc $4,$5,$6
|
||||
ddivu $0,$7,$8
|
||||
or $4,$5
|
||||
|
||||
r23:
|
||||
dmult $4,$5
|
||||
dmult $6,$7
|
||||
or $4,$5
|
||||
|
||||
dmultu $4,$5
|
||||
dmultu $6,$7
|
||||
or $4,$5
|
||||
|
||||
dmacc $4,$5,$6
|
||||
dmacc $6,$7,$8
|
||||
or $4,$5
|
||||
|
||||
dmult $4,$5
|
||||
dmacc $6,$7,$8
|
||||
or $4,$5
|
||||
|
||||
r24:
|
||||
macc $4,$5,$6
|
||||
mtlo $7
|
||||
|
||||
dmacc $4,$5,$6
|
||||
mtlo $7
|
||||
|
||||
macc $4,$5,$6
|
||||
mthi $7
|
||||
|
||||
dmacc $4,$5,$6
|
||||
mthi $7
|
||||
130
gas/testsuite/gas/mips/vr5400.d
Normal file
130
gas/testsuite/gas/mips/vr5400.d
Normal file
@ -0,0 +1,130 @@
|
||||
#objdump: -dr --prefix-addresses
|
||||
#name: MIPS VR5400
|
||||
#as: -march=vr5400
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section \.text:
|
||||
0+0000 <stuff> mul a0,a1,a2
|
||||
0+0004 <stuff\+0x4> mulu a0,a1,a2
|
||||
0+0008 <stuff\+0x8> mulhi a0,a1,a2
|
||||
0+000c <stuff\+0xc> mulhiu a0,a1,a2
|
||||
0+0010 <stuff\+0x10> muls a0,a1,a2
|
||||
0+0014 <stuff\+0x14> mulsu a0,a1,a2
|
||||
0+0018 <stuff\+0x18> mulshi a0,a1,a2
|
||||
0+001c <stuff\+0x1c> mulshiu a0,a1,a2
|
||||
0+0020 <stuff\+0x20> macc a0,a1,a2
|
||||
0+0024 <stuff\+0x24> maccu a0,a1,a2
|
||||
0+0028 <stuff\+0x28> macchi a0,a1,a2
|
||||
0+002c <stuff\+0x2c> macchiu a0,a1,a2
|
||||
0+0030 <stuff\+0x30> msac a0,a1,a2
|
||||
0+0034 <stuff\+0x34> msacu a0,a1,a2
|
||||
0+0038 <stuff\+0x38> msachi a0,a1,a2
|
||||
0+003c <stuff\+0x3c> msachiu a0,a1,a2
|
||||
0+0040 <stuff\+0x40> ror a0,a1,0x19
|
||||
0+0044 <stuff\+0x44> rorv a0,a1,a2
|
||||
0+0048 <stuff\+0x48> dror a0,a1,0x19
|
||||
0+004c <stuff\+0x4c> dror32 a0,a1,0x19
|
||||
0+0050 <stuff\+0x50> dror32 a0,a1,0x19
|
||||
0+0054 <stuff\+0x54> drorv a0,a1,a2
|
||||
0+0058 <stuff\+0x58> dbreak
|
||||
0+005c <stuff\+0x5c> dret
|
||||
0+0060 <stuff\+0x60> mfdr v1,\$3
|
||||
0+0064 <stuff\+0x64> mtdr v1,\$3
|
||||
0+0068 <stuff\+0x68> mfpc a0,1
|
||||
0+006c <stuff\+0x6c> mfps a0,1
|
||||
0+0070 <stuff\+0x70> mtpc a0,1
|
||||
0+0074 <stuff\+0x74> mtps a0,1
|
||||
0+0078 <stuff\+0x78> add\.ob \$f0,\$f1,\$f2
|
||||
0+007c <stuff\+0x7c> add\.ob \$f3,\$f4,\$f6\[2\]
|
||||
0+0080 <stuff\+0x80> add\.ob \$f6,\$f5,0xf
|
||||
0+0084 <stuff\+0x84> add\.ob \$f3,\$f7,0x1f
|
||||
0+0088 <stuff\+0x88> and\.ob \$f0,\$f1,\$f2
|
||||
0+008c <stuff\+0x8c> and\.ob \$f3,\$f4,\$f6\[2\]
|
||||
0+0090 <stuff\+0x90> and\.ob \$f6,\$f5,0xf
|
||||
0+0094 <stuff\+0x94> and\.ob \$f3,\$f7,0x1f
|
||||
0+0098 <stuff\+0x98> c\.eq\.ob \$f0,\$f2
|
||||
0+009c <stuff\+0x9c> c\.eq\.ob \$f3,\$f6\[2\]
|
||||
0+00a0 <stuff\+0xa0> c\.eq\.ob \$f6,0xf
|
||||
0+00a4 <stuff\+0xa4> c\.eq\.ob \$f3,0x1f
|
||||
0+00a8 <stuff\+0xa8> c\.le\.ob \$f0,\$f2
|
||||
0+00ac <stuff\+0xac> c\.le\.ob \$f3,\$f6\[2\]
|
||||
0+00b0 <stuff\+0xb0> c\.le\.ob \$f6,0xf
|
||||
0+00b4 <stuff\+0xb4> c\.le\.ob \$f3,0x1f
|
||||
0+00b8 <stuff\+0xb8> c\.lt\.ob \$f0,\$f2
|
||||
0+00bc <stuff\+0xbc> c\.lt\.ob \$f3,\$f6\[2\]
|
||||
0+00c0 <stuff\+0xc0> c\.lt\.ob \$f6,0xf
|
||||
0+00c4 <stuff\+0xc4> c\.lt\.ob \$f3,0x1f
|
||||
0+00c8 <stuff\+0xc8> max\.ob \$f0,\$f1,\$f2
|
||||
0+00cc <stuff\+0xcc> max\.ob \$f3,\$f4,\$f6\[2\]
|
||||
0+00d0 <stuff\+0xd0> max\.ob \$f6,\$f5,0xf
|
||||
0+00d4 <stuff\+0xd4> max\.ob \$f3,\$f7,0x1f
|
||||
0+00d8 <stuff\+0xd8> min\.ob \$f0,\$f1,\$f2
|
||||
0+00dc <stuff\+0xdc> min\.ob \$f3,\$f4,\$f6\[2\]
|
||||
0+00e0 <stuff\+0xe0> min\.ob \$f6,\$f5,0xf
|
||||
0+00e4 <stuff\+0xe4> min\.ob \$f3,\$f7,0x1f
|
||||
0+00e8 <stuff\+0xe8> mul\.ob \$f0,\$f1,\$f2
|
||||
0+00ec <stuff\+0xec> mul\.ob \$f3,\$f4,\$f6\[2\]
|
||||
0+00f0 <stuff\+0xf0> mul\.ob \$f6,\$f5,0xf
|
||||
0+00f4 <stuff\+0xf4> mul\.ob \$f3,\$f7,0x1f
|
||||
0+00f8 <stuff\+0xf8> mula\.ob \$f0,\$f2
|
||||
0+00fc <stuff\+0xfc> mula\.ob \$f3,\$f6\[2\]
|
||||
0+0100 <stuff\+0x100> mula\.ob \$f6,0xf
|
||||
0+0104 <stuff\+0x104> mula\.ob \$f3,0x1f
|
||||
0+0108 <stuff\+0x108> mull\.ob \$f0,\$f2
|
||||
0+010c <stuff\+0x10c> mull\.ob \$f3,\$f6\[2\]
|
||||
0+0110 <stuff\+0x110> mull\.ob \$f6,0xf
|
||||
0+0114 <stuff\+0x114> mull\.ob \$f3,0x1f
|
||||
0+0118 <stuff\+0x118> muls\.ob \$f0,\$f2
|
||||
0+011c <stuff\+0x11c> muls\.ob \$f3,\$f6\[2\]
|
||||
0+0120 <stuff\+0x120> muls\.ob \$f6,0xf
|
||||
0+0124 <stuff\+0x124> muls\.ob \$f3,0x1f
|
||||
0+0128 <stuff\+0x128> mulsl\.ob \$f0,\$f2
|
||||
0+012c <stuff\+0x12c> mulsl\.ob \$f3,\$f6\[2\]
|
||||
0+0130 <stuff\+0x130> mulsl\.ob \$f6,0xf
|
||||
0+0134 <stuff\+0x134> mulsl\.ob \$f3,0x1f
|
||||
0+0138 <stuff\+0x138> nor\.ob \$f0,\$f1,\$f2
|
||||
0+013c <stuff\+0x13c> nor\.ob \$f3,\$f4,\$f6\[2\]
|
||||
0+0140 <stuff\+0x140> nor\.ob \$f6,\$f5,0xf
|
||||
0+0144 <stuff\+0x144> nor\.ob \$f3,\$f7,0x1f
|
||||
0+0148 <stuff\+0x148> or\.ob \$f0,\$f1,\$f2
|
||||
0+014c <stuff\+0x14c> or\.ob \$f3,\$f4,\$f6\[2\]
|
||||
0+0150 <stuff\+0x150> or\.ob \$f6,\$f5,0xf
|
||||
0+0154 <stuff\+0x154> or\.ob \$f3,\$f7,0x1f
|
||||
0+0158 <stuff\+0x158> pickf\.ob \$f0,\$f1,\$f2
|
||||
0+015c <stuff\+0x15c> pickf\.ob \$f3,\$f4,\$f6\[2\]
|
||||
0+0160 <stuff\+0x160> pickf\.ob \$f6,\$f5,0xf
|
||||
0+0164 <stuff\+0x164> pickf\.ob \$f3,\$f7,0x1f
|
||||
0+0168 <stuff\+0x168> pickt\.ob \$f0,\$f1,\$f2
|
||||
0+016c <stuff\+0x16c> pickt\.ob \$f3,\$f4,\$f6\[2\]
|
||||
0+0170 <stuff\+0x170> pickt\.ob \$f6,\$f5,0xf
|
||||
0+0174 <stuff\+0x174> pickt\.ob \$f3,\$f7,0x1f
|
||||
0+0178 <stuff\+0x178> sub\.ob \$f0,\$f1,\$f2
|
||||
0+017c <stuff\+0x17c> sub\.ob \$f3,\$f4,\$f6\[2\]
|
||||
0+0180 <stuff\+0x180> sub\.ob \$f6,\$f5,0xf
|
||||
0+0184 <stuff\+0x184> sub\.ob \$f3,\$f7,0x1f
|
||||
0+0188 <stuff\+0x188> xor\.ob \$f0,\$f1,\$f2
|
||||
0+018c <stuff\+0x18c> xor\.ob \$f3,\$f4,\$f6\[2\]
|
||||
0+0190 <stuff\+0x190> xor\.ob \$f6,\$f5,0xf
|
||||
0+0194 <stuff\+0x194> xor\.ob \$f3,\$f7,0x1f
|
||||
0+0198 <stuff\+0x198> alni\.ob \$f1,\$f2,\$f3,5
|
||||
0+019c <stuff\+0x19c> shfl\.mixh\.ob \$f1,\$f2,\$f3
|
||||
0+01a0 <stuff\+0x1a0> shfl\.mixl\.ob \$f1,\$f2,\$f3
|
||||
0+01a4 <stuff\+0x1a4> bc2tl 0+4324 <stuff\+0x4324>
|
||||
0+01a8 <stuff\+0x1a8> shfl\.pacl\.ob \$f1,\$f2,\$f3
|
||||
0+01ac <stuff\+0x1ac> sll\.ob \$f2,\$f4,\$f5\[3\]
|
||||
0+01b0 <stuff\+0x1b0> sll\.ob \$f3,\$f6,0xe
|
||||
0+01b4 <stuff\+0x1b4> srl\.ob \$f2,\$f4,\$f5\[3\]
|
||||
0+01b8 <stuff\+0x1b8> srl\.ob \$f3,\$f6,0xe
|
||||
0+01bc <stuff\+0x1bc> rzu\.ob \$f2,0xd
|
||||
0+01c0 <stuff\+0x1c0> rach\.ob \$f2
|
||||
0+01c4 <stuff\+0x1c4> racl\.ob \$f2
|
||||
0+01c8 <stuff\+0x1c8> bc2f 0+04c8 <stuff\+0x4c8>
|
||||
0+01cc <stuff\+0x1cc> wach\.ob \$f2
|
||||
0+01d0 <stuff\+0x1d0> wacl\.ob \$f2,\$f3
|
||||
0+01d4 <stuff\+0x1d4> rorv a0,a1,a2
|
||||
0+01d8 <stuff\+0x1d8> ror a0,a1,0x11
|
||||
0+01dc <stuff\+0x1dc> drorv a0,a1,a2
|
||||
0+01e0 <stuff\+0x1e0> dror32 a0,a1,0x1
|
||||
0+01e4 <stuff\+0x1e4> dror a0,a1,0x2
|
||||
\.\.\.
|
||||
125
gas/testsuite/gas/mips/vr5400.s
Normal file
125
gas/testsuite/gas/mips/vr5400.s
Normal file
@ -0,0 +1,125 @@
|
||||
.text
|
||||
|
||||
stuff:
|
||||
.ent stuff
|
||||
/* Integer instructions. */
|
||||
|
||||
mul $4,$5,$6
|
||||
mulu $4,$5,$6
|
||||
mulhi $4,$5,$6
|
||||
mulhiu $4,$5,$6
|
||||
muls $4,$5,$6
|
||||
mulsu $4,$5,$6
|
||||
mulshi $4,$5,$6
|
||||
mulshiu $4,$5,$6
|
||||
macc $4,$5,$6
|
||||
maccu $4,$5,$6
|
||||
macchi $4,$5,$6
|
||||
macchiu $4,$5,$6
|
||||
msac $4,$5,$6
|
||||
msacu $4,$5,$6
|
||||
msachi $4,$5,$6
|
||||
msachiu $4,$5,$6
|
||||
|
||||
ror $4,$5,25
|
||||
rorv $4,$5,$6
|
||||
dror $4,$5,25
|
||||
dror $4,$5,57 /* Should expand to dror32 $4,$5,25. */
|
||||
dror32 $4,$5,25
|
||||
drorv $4,$5,$6
|
||||
|
||||
/* Debug instructions. */
|
||||
|
||||
dbreak
|
||||
dret
|
||||
mfdr $3,$3
|
||||
mtdr $3,$3
|
||||
|
||||
/* Coprocessor 0 instructions, minus standard ISA 3 ones.
|
||||
That leaves just the performance monitoring registers. */
|
||||
|
||||
mfpc $4,1
|
||||
mfps $4,1
|
||||
mtpc $4,1
|
||||
mtps $4,1
|
||||
|
||||
/* Multimedia instructions. */
|
||||
|
||||
.macro nsel2 op
|
||||
/* Test each form of each vector opcode. */
|
||||
\op $f0,$f2
|
||||
\op $f3,$f6[2]
|
||||
\op $f6,15
|
||||
.if 0 /* Which is right?? */
|
||||
/* Test negative numbers in immediate-value slot. */
|
||||
\op $f4,-3
|
||||
.else
|
||||
/* Test that it's recognized as an unsigned field. */
|
||||
\op $f3,31
|
||||
.endif
|
||||
.endm
|
||||
|
||||
.macro nsel3 op
|
||||
/* Test each form of each vector opcode. */
|
||||
\op $f0,$f1,$f2
|
||||
\op $f3,$f4,$f6[2]
|
||||
\op $f6,$f5,15
|
||||
.if 0 /* Which is right?? */
|
||||
/* Test negative numbers in immediate-value slot. */
|
||||
\op $f4,$f6,-3
|
||||
.else
|
||||
/* Test that it's recognized as an unsigned field. */
|
||||
\op $f3,$f7,31
|
||||
.endif
|
||||
.endm
|
||||
|
||||
nsel3 add.ob
|
||||
nsel3 and.ob
|
||||
nsel2 c.eq.ob
|
||||
nsel2 c.le.ob
|
||||
nsel2 c.lt.ob
|
||||
nsel3 max.ob
|
||||
nsel3 min.ob
|
||||
nsel3 mul.ob
|
||||
nsel2 mula.ob
|
||||
nsel2 mull.ob
|
||||
nsel2 muls.ob
|
||||
nsel2 mulsl.ob
|
||||
nsel3 nor.ob
|
||||
nsel3 or.ob
|
||||
nsel3 pickf.ob
|
||||
nsel3 pickt.ob
|
||||
nsel3 sub.ob
|
||||
nsel3 xor.ob
|
||||
|
||||
/* ALNI, SHFL: Vector only. */
|
||||
alni.ob $f1,$f2,$f3,5
|
||||
shfl.mixh.ob $f1,$f2,$f3
|
||||
shfl.mixl.ob $f1,$f2,$f3
|
||||
shfl.pach.ob $f1,$f2,$f3
|
||||
shfl.pacl.ob $f1,$f2,$f3
|
||||
|
||||
/* SLL,SRL: Scalar or immediate. */
|
||||
sll.ob $f2,$f4,$f5[3]
|
||||
sll.ob $f3,$f6,14
|
||||
srl.ob $f2,$f4,$f5[3]
|
||||
srl.ob $f3,$f6,14
|
||||
|
||||
/* RZU: Immediate, must be 0, 8, or 16. */
|
||||
rzu.ob $f2,13
|
||||
|
||||
/* No selector. */
|
||||
rach.ob $f2
|
||||
racl.ob $f2
|
||||
racm.ob $f2
|
||||
wach.ob $f2
|
||||
wacl.ob $f2,$f3
|
||||
|
||||
ror $4,$5,$6
|
||||
rol $4,$5,15
|
||||
dror $4,$5,$6
|
||||
drol $4,$5,31
|
||||
drol $4,$5,62
|
||||
|
||||
.space 8
|
||||
.end stuff
|
||||
51
gas/testsuite/gas/mips/vr5500.d
Normal file
51
gas/testsuite/gas/mips/vr5500.d
Normal file
@ -0,0 +1,51 @@
|
||||
#objdump: -dr --prefix-addresses
|
||||
#name: MIPS VR5500
|
||||
#as: -march=vr5500
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <stuff> mul a0,a1,a2
|
||||
0+0004 <stuff\+0x4> mulu a0,a1,a2
|
||||
0+00008 <stuff\+0x8> mulhi a0,a1,a2
|
||||
0+0000c <stuff\+0xc> mulhiu a0,a1,a2
|
||||
0+00010 <stuff\+0x10> muls a0,a1,a2
|
||||
0+00014 <stuff\+0x14> mulsu a0,a1,a2
|
||||
0+00018 <stuff\+0x18> mulshi a0,a1,a2
|
||||
0+0001c <stuff\+0x1c> mulshiu a0,a1,a2
|
||||
0+00020 <stuff\+0x20> macc a0,a1,a2
|
||||
0+00024 <stuff\+0x24> maccu a0,a1,a2
|
||||
0+00028 <stuff\+0x28> macchi a0,a1,a2
|
||||
0+0002c <stuff\+0x2c> macchiu a0,a1,a2
|
||||
0+00030 <stuff\+0x30> msac a0,a1,a2
|
||||
0+00034 <stuff\+0x34> msacu a0,a1,a2
|
||||
0+00038 <stuff\+0x38> msachi a0,a1,a2
|
||||
0+0003c <stuff\+0x3c> msachiu a0,a1,a2
|
||||
0+00040 <stuff\+0x40> ror a0,a1,0x19
|
||||
0+00044 <stuff\+0x44> rorv a0,a1,a2
|
||||
0+00048 <stuff\+0x48> dror a0,a1,0x19
|
||||
0+0004c <stuff\+0x4c> dror32 a0,a1,0x19
|
||||
0+00050 <stuff\+0x50> dror32 a0,a1,0x19
|
||||
0+00054 <stuff\+0x54> drorv a0,a1,a2
|
||||
0+00058 <stuff\+0x58> prefx 0x4,a0\(a1\)
|
||||
0+0005c <stuff\+0x5c> dbreak
|
||||
0+00060 <stuff\+0x60> dret
|
||||
0+00064 <stuff\+0x64> mfdr v1,\$3
|
||||
0+00068 <stuff\+0x68> mtdr v1,\$3
|
||||
0+0006c <stuff\+0x6c> mfpc a0,1
|
||||
0+00070 <stuff\+0x70> mfps a0,1
|
||||
0+00074 <stuff\+0x74> mtpc a0,1
|
||||
0+00078 <stuff\+0x78> mtps a0,1
|
||||
0+0007c <stuff\+0x7c> wait
|
||||
0+00080 <stuff\+0x80> wait
|
||||
0+00084 <stuff\+0x84> wait 0x56789
|
||||
0+00088 <stuff\+0x88> ssnop
|
||||
0+0008c <stuff\+0x8c> clo v1,a0
|
||||
0+00090 <stuff\+0x90> dclo v1,a0
|
||||
0+00094 <stuff\+0x94> clz v1,a0
|
||||
0+00098 <stuff\+0x98> dclz v1,a0
|
||||
0+0009c <stuff\+0x9c> luxc1 \$f1,a0\(v0\)
|
||||
0+000a0 <stuff\+0xa0> suxc1 \$f1,a0\(v0\)
|
||||
0+000a4 <stuff\+0xa4> tlbp
|
||||
0+000a8 <stuff\+0xa8> tlbr
|
||||
\.\.\.
|
||||
80
gas/testsuite/gas/mips/vr5500.s
Normal file
80
gas/testsuite/gas/mips/vr5500.s
Normal file
@ -0,0 +1,80 @@
|
||||
.text
|
||||
|
||||
stuff:
|
||||
.ent stuff
|
||||
/* Integer instructions. */
|
||||
|
||||
mul $4,$5,$6
|
||||
mulu $4,$5,$6
|
||||
mulhi $4,$5,$6
|
||||
mulhiu $4,$5,$6
|
||||
muls $4,$5,$6
|
||||
mulsu $4,$5,$6
|
||||
mulshi $4,$5,$6
|
||||
mulshiu $4,$5,$6
|
||||
macc $4,$5,$6
|
||||
maccu $4,$5,$6
|
||||
macchi $4,$5,$6
|
||||
macchiu $4,$5,$6
|
||||
msac $4,$5,$6
|
||||
msacu $4,$5,$6
|
||||
msachi $4,$5,$6
|
||||
msachiu $4,$5,$6
|
||||
|
||||
ror $4,$5,25
|
||||
rorv $4,$5,$6
|
||||
dror $4,$5,25
|
||||
dror $4,$5,57 /* Should expand to dror32 $4,$5,25. */
|
||||
dror32 $4,$5,25
|
||||
drorv $4,$5,$6
|
||||
|
||||
|
||||
/* Prefetch instructions. */
|
||||
# We don't test pref because currently the disassembler will
|
||||
# disassemble it as lwc3. lwc3 is correct for mips1 to mips3,
|
||||
# while pref is correct for mips4. Unfortunately, the
|
||||
# disassembler does not know which architecture it is
|
||||
# disassembling for.
|
||||
# pref 4,0($4)
|
||||
|
||||
prefx 4,$4($5)
|
||||
|
||||
/* Debug instructions. */
|
||||
|
||||
dbreak
|
||||
dret
|
||||
mfdr $3,$3
|
||||
mtdr $3,$3
|
||||
|
||||
/* Coprocessor 0 instructions, minus standard ISA 3 ones.
|
||||
That leaves just the performance monitoring registers. */
|
||||
|
||||
mfpc $4,1
|
||||
mfps $4,1
|
||||
mtpc $4,1
|
||||
mtps $4,1
|
||||
|
||||
/* Miscellaneous instructions. */
|
||||
|
||||
wait
|
||||
wait 0 # disassembles without code
|
||||
wait 0x56789
|
||||
|
||||
ssnop
|
||||
|
||||
clo $3,$4
|
||||
dclo $3,$4
|
||||
clz $3,$4
|
||||
dclz $3,$4
|
||||
|
||||
luxc1 $f1,$4($2)
|
||||
suxc1 $f1,$4($2)
|
||||
|
||||
tlbp
|
||||
tlbr
|
||||
|
||||
/* Align to 16-byte boundary. */
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
.end stuff
|
||||
Loading…
x
Reference in New Issue
Block a user