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https://github.com/darlinghq/darling-gdb.git
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sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition that unconditionally allows fmt_ps. (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU) (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt) (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change filter from 64,f to 32,f. (PREFX): Change filter from 64 to 32. (LDXC1, LUXC1): Provide separate mips32r2 implementations that use do_load_double instead of do_load. Make both LUXC1 versions unpredictable if SizeFGR () != 64. (SDXC1, SUXC1): Extend to mips32r2, using do_store_double instead of do_store. Remove unused variable. Make both SUXC1 versions unpredictable if SizeFGR () != 64.
This commit is contained in:
Richard Sandiford
parent
92fddf8e3d
commit
60dc88db8b
@ -1,3 +1,19 @@
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2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
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* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
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that unconditionally allows fmt_ps.
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(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
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(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
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(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
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filter from 64,f to 32,f.
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(PREFX): Change filter from 64 to 32.
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(LDXC1, LUXC1): Provide separate mips32r2 implementations
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that use do_load_double instead of do_load. Make both LUXC1
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versions unpredictable if SizeFGR () != 64.
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(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
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instead of do_store. Remove unused variable. Make both SUXC1
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versions unpredictable if SizeFGR () != 64.
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2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
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* mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
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@ -4144,7 +4144,6 @@
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*mipsIII:
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*mipsIV:
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*mips32:
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*mips32r2:
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*vr4100:
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*vr5000:
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*r3900:
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@ -4155,6 +4154,13 @@
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SignalException (ReservedInstruction, insn);
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}
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:function:::void:check_fmt_p:int fmt, instruction_word insn
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*mips32r2:
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{
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if ((fmt != fmt_single) && (fmt != fmt_double) && (fmt != fmt_ps))
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SignalException (ReservedInstruction, insn);
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}
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:function:::void:check_fmt_p:int fmt, instruction_word insn
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*mipsV:
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*mips64:
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@ -4309,7 +4315,7 @@
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}
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010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
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010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:32,f::ALNV.PS
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"alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
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*mipsV:
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*mips32r2:
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@ -4427,7 +4433,7 @@
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}
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:32,f::CEIL.L.fmt
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"ceil.l.%s<FMT> f<FD>, f<FS>"
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*mipsIII:
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*mipsIV:
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@ -4587,7 +4593,7 @@
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}
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:32,f::CVT.L.fmt
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"cvt.l.%s<FMT> f<FD>, f<FS>"
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*mipsIII:
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*mipsIV:
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@ -4608,7 +4614,7 @@
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}
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010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
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010001,10,000,5.FT,5.FS,5.FD,100110:COP1:32,f::CVT.PS.S
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"cvt.ps.s f<FD>, f<FS>, f<FT>"
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*mipsV:
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*mips32r2:
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@ -4649,7 +4655,7 @@
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}
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010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
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010001,10,110,00000,5.FS,5.FD,101000:COP1:32,f::CVT.S.PL
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"cvt.s.pl f<FD>, f<FS>"
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*mipsV:
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*mips32r2:
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@ -4662,7 +4668,7 @@
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}
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010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
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010001,10,110,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.PU
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"cvt.s.pu f<FD>, f<FS>"
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*mipsV:
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*mips32r2:
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@ -4799,7 +4805,7 @@
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}
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:32,f::FLOOR.L.fmt
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"floor.l.%s<FMT> f<FD>, f<FS>"
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*mipsIII:
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*mipsIV:
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@ -4866,11 +4872,19 @@
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}
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010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:32,f::LDXC1
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"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
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*mips32r2:
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{
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check_fpu (SD_);
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COP_LD (1, FD, do_load_double (SD_, GPR[BASE], GPR[INDEX]));
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}
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010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
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"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
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*mipsIV:
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*mipsV:
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*mips32r2:
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*mips64:
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*mips64r2:
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*vr5000:
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@ -4881,10 +4895,26 @@
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}
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010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:32,f::LUXC1
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"luxc1 f<FD>, r<INDEX>(r<BASE>)"
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*mips32r2:
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{
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address_word base = GPR[BASE];
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address_word index = GPR[INDEX];
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address_word vaddr = base + index;
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check_fpu (SD_);
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if (SizeFGR () != 64)
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Unpredictable ();
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/* Arrange for the bottom 3 bits of (base + index) to be 0. */
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if ((vaddr & 0x7) != 0)
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index -= (vaddr & 0x7);
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COP_LD (1, FD, do_load_double (SD_, base, index));
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}
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010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
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"luxc1 f<FD>, r<INDEX>(r<BASE>)"
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*mipsV:
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*mips32r2:
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*mips64:
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*mips64r2:
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{
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@ -4893,6 +4923,8 @@
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address_word vaddr = base + index;
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check_fpu (SD_);
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check_u64 (SD_, instruction_0);
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if (SizeFGR () != 64)
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Unpredictable ();
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/* Arrange for the bottom 3 bits of (base + index) to be 0. */
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if ((vaddr & 0x7) != 0)
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index -= (vaddr & 0x7);
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@ -4920,7 +4952,7 @@
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}
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010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
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010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32,f::LWXC1
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"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
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*mipsIV:
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*mipsV:
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@ -4936,7 +4968,7 @@
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010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:64,f::MADD.fmt
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010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:32,f::MADD.fmt
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"madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
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*mipsIV:
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*mipsV:
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@ -5101,7 +5133,7 @@
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}
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010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:64,f::MSUB.fmt
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010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:32,f::MSUB.fmt
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"msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
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*mipsIV:
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*mipsV:
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@ -5194,7 +5226,7 @@
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}
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010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:64,f::NMADD.fmt
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010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:32,f::NMADD.fmt
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"nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
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*mipsIV:
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*mipsV:
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@ -5212,7 +5244,7 @@
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}
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010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:64,f::NMSUB.fmt
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010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:32,f::NMSUB.fmt
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"nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
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*mipsIV:
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*mipsV:
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@ -5230,7 +5262,7 @@
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}
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010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
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010001,10,110,5.FT,5.FS,5.FD,101100:COP1:32,f::PLL.PS
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"pll.ps f<FD>, f<FS>, f<FT>"
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*mipsV:
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*mips32r2:
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@ -5244,7 +5276,7 @@
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}
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010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
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010001,10,110,5.FT,5.FS,5.FD,101101:COP1:32,f::PLU.PS
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"plu.ps f<FD>, f<FS>, f<FT>"
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*mipsV:
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*mips32r2:
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@ -5258,7 +5290,7 @@
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}
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010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
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010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:32::PREFX
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"prefx <HINT>, r<INDEX>(r<BASE>)"
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*mipsIV:
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*mipsV:
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@ -5279,7 +5311,7 @@
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}
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010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
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010001,10,110,5.FT,5.FS,5.FD,101110:COP1:32,f::PUL.PS
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"pul.ps f<FD>, f<FS>, f<FT>"
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*mipsV:
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*mips32r2:
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@ -5293,7 +5325,7 @@
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}
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010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
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010001,10,110,5.FT,5.FS,5.FD,101111:COP1:32,f::PUU.PS
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"puu.ps f<FD>, f<FS>, f<FT>"
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*mipsV:
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*mips32r2:
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@ -5322,7 +5354,7 @@
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}
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:32,f::ROUND.L.fmt
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"round.l.%s<FMT> f<FD>, f<FS>"
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*mipsIII:
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*mipsIV:
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@ -5404,6 +5436,15 @@
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}
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010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:32,f::SDXC1
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"sdxc1 f<FS>, r<INDEX>(r<BASE>)"
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*mips32r2
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{
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check_fpu (SD_);
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do_store_double (SD_, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
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}
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010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
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"sdxc1 f<FS>, r<INDEX>(r<BASE>)"
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*mipsIV:
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@ -5418,18 +5459,36 @@
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}
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010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:32,f::SUXC1
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"suxc1 f<FS>, r<INDEX>(r<BASE>)"
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*mips32r2:
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{
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address_word base = GPR[BASE];
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address_word index = GPR[INDEX];
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address_word vaddr = base + index;
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check_fpu (SD_);
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if (SizeFGR () != 64)
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Unpredictable ();
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/* Arrange for the bottom 3 bits of (base + index) to be 0. */
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if ((vaddr & 0x7) != 0)
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index -= (vaddr & 0x7);
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do_store_double (SD_, base, index, COP_SD (1, FS));
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}
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010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
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"suxc1 f<FS>, r<INDEX>(r<BASE>)"
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*mipsV:
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*mips64:
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*mips64r2:
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{
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unsigned64 v;
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address_word base = GPR[BASE];
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address_word index = GPR[INDEX];
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address_word vaddr = base + index;
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check_fpu (SD_);
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check_u64 (SD_, instruction_0);
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if (SizeFGR () != 64)
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Unpredictable ();
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/* Arrange for the bottom 3 bits of (base + index) to be 0. */
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if ((vaddr & 0x7) != 0)
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index -= (vaddr & 0x7);
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@ -5570,7 +5629,7 @@
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}
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
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010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:32,f::TRUNC.L.fmt
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"trunc.l.%s<FMT> f<FD>, f<FS>"
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*mipsIII:
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*mipsIV:
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