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[ARM] Add feature check for ARMv8.1 AdvSIMD instructions.
gas/ 2016-03-04 Matthew Wahab <matthew.wahab@arm.com> * config/gas/tc-arm.c (fpu_neon_ext_v8_1): Restrict to the ARMv8.1 RDMA feature. (record_feature_use): New. (mark_feature_used): Use record_feature_use. (do_neon_qrdmlah): New. (insns): Use do_neon_qrdmlah for vqrdmlah and vqrdmlsh and variants. (arm_extensions): Put into alphabetical order. Re-indent "simd" and "rdma" entries. Fix the incorrect merge value for "+rdma". * testsuite/gas/arm/armv8-a+rdma-warning.d: New. * testsuite/gas/arm/armv8-a+rdma.d: Add assembler command line options. Make source file explicit. * testsuite/gas/arm/armv8-a+rdma.l: New. * testsuite/gas/arm/armv8-a+rdma.s: Remove .arch and .arch_extension directives. Fix white-space. * testsuite/gas/arm/armv8_1-a+simd.d: New. include/opcode 2016-03-04 Matthew Wahab <matthew.wahab@arm.com> * arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA. (ARM_CPU_HAS_FEATURE): Add comment. Change-Id: Ie19250e8fa50aed44e44ab40ff30b04b38bc1a3d
This commit is contained in:
Matthew Wahab
parent
dc1c8a16a3
commit
643afb90da
@ -1,3 +1,22 @@
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2016-03-04 Matthew Wahab <matthew.wahab@arm.com>
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* config/gas/tc-arm.c (fpu_neon_ext_v8_1): Restrict to the ARMv8.1 RDMA
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feature.
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(record_feature_use): New.
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(mark_feature_used): Use record_feature_use.
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(do_neon_qrdmlah): New.
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(insns): Use do_neon_qrdmlah for vqrdmlah and vqrdmlsh and
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variants.
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(arm_extensions): Put into alphabetical order. Re-indent "simd"
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and "rdma" entries. Fix the incorrect merge value for "+rdma".
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* testsuite/gas/arm/armv8-a+rdma-warning.d: New.
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* testsuite/gas/arm/armv8-a+rdma.d: Add assembler command line options.
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Make source file explicit.
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* testsuite/gas/arm/armv8-a+rdma.l: New.
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* testsuite/gas/arm/armv8-a+rdma.s: Remove .arch and .arch_extension
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directives. Fix white-space.
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* testsuite/gas/arm/armv8_1-a+simd.d: New.
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2016-03-02 H.J. Lu <hongjiu.lu@intel.com>
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* testsuite/gas/i386/x86_64-intel.d: Adjusted for COFF.
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@ -271,7 +271,7 @@ static const arm_feature_set fpu_crypto_ext_armv8 =
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static const arm_feature_set crc_ext_armv8 =
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ARM_FEATURE_COPROC (CRC_EXT_ARMV8);
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static const arm_feature_set fpu_neon_ext_v8_1 =
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ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA);
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ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA);
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static int mfloat_abi_opt = -1;
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/* Record user cpu selection for object attributes. */
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@ -6085,6 +6085,16 @@ parse_cond (char **str)
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return c->value;
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}
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/* Record a use of the given feature. */
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static void
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record_feature_use (const arm_feature_set *feature)
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{
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if (thumb_mode)
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ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
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else
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ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
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}
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/* If the given feature available in the selected CPU, mark it as used.
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Returns TRUE iff feature is available. */
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static bfd_boolean
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@ -6096,10 +6106,7 @@ mark_feature_used (const arm_feature_set *feature)
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/* Add the appropriate architecture feature for the barrier option used.
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*/
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if (thumb_mode)
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ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
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else
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ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
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record_feature_use (feature);
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return TRUE;
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}
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@ -15022,6 +15029,38 @@ do_neon_qdmulh (void)
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}
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}
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static void
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do_neon_qrdmlah (void)
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{
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/* Check we're on the correct architecture. */
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if (!mark_feature_used (&fpu_neon_ext_armv8))
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inst.error =
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_("instruction form not available on this architecture.");
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else if (!mark_feature_used (&fpu_neon_ext_v8_1))
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{
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as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
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record_feature_use (&fpu_neon_ext_v8_1);
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}
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if (inst.operands[2].isscalar)
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{
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enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
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struct neon_type_el et = neon_check_type (3, rs,
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N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
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NEON_ENCODE (SCALAR, inst);
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neon_mul_mac (et, neon_quad (rs));
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}
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else
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{
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enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
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struct neon_type_el et = neon_check_type (3, rs,
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N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
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NEON_ENCODE (INTEGER, inst);
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/* The U bit (rounding) comes from bit mask. */
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neon_three_same (neon_quad (rs), 0, et.size);
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}
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}
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static void
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do_neon_fcmp_absolute (void)
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{
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@ -20311,10 +20350,10 @@ static const struct asm_opcode insns[] =
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NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
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NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
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/* ARM v8.1 extension. */
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nUF(vqrdmlah, _vqrdmlah, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
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nUF(vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
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nUF(vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
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nUF(vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
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nUF (vqrdmlah, _vqrdmlah, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
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nUF (vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
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nUF (vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
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nUF (vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
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/* Two address, int/float. Types S8 S16 S32 F32. */
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NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
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@ -25350,25 +25389,25 @@ static const struct arm_option_extension_value_table arm_extensions[] =
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ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
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ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
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ARM_FEATURE_CORE_LOW (ARM_EXT_V7A | ARM_EXT_V7R)),
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ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
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ARM_FEATURE_COPROC (FPU_NEON_ARMV8),
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ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
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ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
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ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
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ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)),
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ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
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ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0),
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ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
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ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1,
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ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
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ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
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ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
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ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
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ARM_FEATURE_CORE_LOW (ARM_EXT_V6K | ARM_EXT_V7A)),
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ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
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ARM_FEATURE_COPROC (FPU_NEON_ARMV8),
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ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
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ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV
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| ARM_EXT_DIV),
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ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
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ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
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ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8,
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ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
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ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
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ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
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ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ANY),
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{ NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE }
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6
gas/testsuite/gas/arm/armv8-a+rdma-warning.d
Normal file
6
gas/testsuite/gas/arm/armv8-a+rdma-warning.d
Normal file
@ -0,0 +1,6 @@
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#name: Accepted v8-a with ARMv8.1 AdvSIMD.
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#as: -march=armv8-a+simd
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#objdump: -dr
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#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
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#source: armv8-a+rdma.s
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#error-output: armv8-a+rdma.l
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@ -1,6 +1,8 @@
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#name: Valid v8-a+rdma
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#as: -march=armv8-a+rdma
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#objdump: -dr
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#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
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#source: armv8-a+rdma.s
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.*: +file format .*arm.*
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65
gas/testsuite/gas/arm/armv8-a+rdma.l
Normal file
65
gas/testsuite/gas/arm/armv8-a+rdma.l
Normal file
@ -0,0 +1,65 @@
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[^:]+: Assembler messages:
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
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@ -1,60 +1,58 @@
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.syntax unified
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.text
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.arch armv8-a
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.arch_extension rdma
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.macro vect_inst I T R
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\I\().\T \R\()0, \R\()1, \R\()2
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.endm
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.macro vect_inst I T R
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\I\().\T \R\()0, \R\()1, \R\()2
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.endm
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.macro scalar_inst I T R N
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\I\().\T \R\()0, \R\()1, d\()2[\N\()]
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.endm
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\I\().\T \R\()0, \R\()1, d\()2[\N\()]
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.endm
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.text
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.arm
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.arm
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A1:
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.irp inst, vqrdmlah, vqrdmlsh
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.irp type, s16, s32
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.irp inst, vqrdmlah, vqrdmlsh
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.irp type, s16, s32
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.irp reg, d, q
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vect_inst \inst \type \reg
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.endr
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.endr
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vect_inst \inst \type \reg
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.endr
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.endr
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.endr
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.irp inst, vqrdmlah, vqrdmlsh
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.irp inst, vqrdmlah, vqrdmlsh
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.irp reg, d, q
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.irp idx, 0, 1, 2, 3
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scalar_inst \inst s16 \reg \idx
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.endr
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.irp idx, 0, 1, 2, 3
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scalar_inst \inst s16 \reg \idx
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.endr
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.endr
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.irp reg, d, q
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.irp idx, 0, 1
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scalar_inst \inst s32 \reg \idx
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.endr
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.irp idx, 0, 1
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scalar_inst \inst s32 \reg \idx
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.endr
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.endr
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.endr
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.text
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.thumb
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.thumb
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T1:
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.irp inst, vqrdmlah, vqrdmlsh
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.irp type, s16, s32
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.irp inst, vqrdmlah, vqrdmlsh
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.irp type, s16, s32
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.irp reg, d, q
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vect_inst \inst \type \reg
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.endr
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.endr
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vect_inst \inst \type \reg
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.endr
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.endr
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.endr
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.irp inst, vqrdmlah, vqrdmlsh
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.irp inst, vqrdmlah, vqrdmlsh
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.irp reg, d, q
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.irp idx, 0, 1, 2, 3
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scalar_inst \inst s16 \reg \idx
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.endr
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.irp idx, 0, 1, 2, 3
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scalar_inst \inst s16 \reg \idx
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.endr
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.endr
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.irp reg, d, q
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.irp idx, 0, 1
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scalar_inst \inst s32 \reg \idx
|
||||
.endr
|
||||
.irp idx, 0, 1
|
||||
scalar_inst \inst s32 \reg \idx
|
||||
.endr
|
||||
.endr
|
||||
.endr
|
||||
|
||||
78
gas/testsuite/gas/arm/armv8_1-a+simd.d
Normal file
78
gas/testsuite/gas/arm/armv8_1-a+simd.d
Normal file
@ -0,0 +1,78 @@
|
||||
#name: Valid ARMv8.1-A with +simd
|
||||
#as: -march=armv8.1-a+simd
|
||||
#objdump: -dr
|
||||
#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
|
||||
#source: armv8-a+rdma.s
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
00000000 <.*>:
|
||||
0: f3110b12 vqrdmlah.s16 d0, d1, d2
|
||||
4: f3120b54 vqrdmlah.s16 q0, q1, q2
|
||||
8: f3210b12 vqrdmlah.s32 d0, d1, d2
|
||||
c: f3220b54 vqrdmlah.s32 q0, q1, q2
|
||||
10: f3110c12 vqrdmlsh.s16 d0, d1, d2
|
||||
14: f3120c54 vqrdmlsh.s16 q0, q1, q2
|
||||
18: f3210c12 vqrdmlsh.s32 d0, d1, d2
|
||||
1c: f3220c54 vqrdmlsh.s32 q0, q1, q2
|
||||
20: f2910e42 vqrdmlah.s16 d0, d1, d2\[0\]
|
||||
24: f2910e4a vqrdmlah.s16 d0, d1, d2\[1\]
|
||||
28: f2910e62 vqrdmlah.s16 d0, d1, d2\[2\]
|
||||
2c: f2910e6a vqrdmlah.s16 d0, d1, d2\[3\]
|
||||
30: f3920e42 vqrdmlah.s16 q0, q1, d2\[0\]
|
||||
34: f3920e4a vqrdmlah.s16 q0, q1, d2\[1\]
|
||||
38: f3920e62 vqrdmlah.s16 q0, q1, d2\[2\]
|
||||
3c: f3920e6a vqrdmlah.s16 q0, q1, d2\[3\]
|
||||
40: f2a10e42 vqrdmlah.s32 d0, d1, d2\[0\]
|
||||
44: f2a10e62 vqrdmlah.s32 d0, d1, d2\[1\]
|
||||
48: f3a20e42 vqrdmlah.s32 q0, q1, d2\[0\]
|
||||
4c: f3a20e62 vqrdmlah.s32 q0, q1, d2\[1\]
|
||||
50: f2910f42 vqrdmlsh.s16 d0, d1, d2\[0\]
|
||||
54: f2910f4a vqrdmlsh.s16 d0, d1, d2\[1\]
|
||||
58: f2910f62 vqrdmlsh.s16 d0, d1, d2\[2\]
|
||||
5c: f2910f6a vqrdmlsh.s16 d0, d1, d2\[3\]
|
||||
60: f3920f42 vqrdmlsh.s16 q0, q1, d2\[0\]
|
||||
64: f3920f4a vqrdmlsh.s16 q0, q1, d2\[1\]
|
||||
68: f3920f62 vqrdmlsh.s16 q0, q1, d2\[2\]
|
||||
6c: f3920f6a vqrdmlsh.s16 q0, q1, d2\[3\]
|
||||
70: f2a10f42 vqrdmlsh.s32 d0, d1, d2\[0\]
|
||||
74: f2a10f62 vqrdmlsh.s32 d0, d1, d2\[1\]
|
||||
78: f3a20f42 vqrdmlsh.s32 q0, q1, d2\[0\]
|
||||
7c: f3a20f62 vqrdmlsh.s32 q0, q1, d2\[1\]
|
||||
|
||||
00000080 <.*>:
|
||||
80: ff11 0b12 vqrdmlah.s16 d0, d1, d2
|
||||
84: ff12 0b54 vqrdmlah.s16 q0, q1, q2
|
||||
88: ff21 0b12 vqrdmlah.s32 d0, d1, d2
|
||||
8c: ff22 0b54 vqrdmlah.s32 q0, q1, q2
|
||||
90: ff11 0c12 vqrdmlsh.s16 d0, d1, d2
|
||||
94: ff12 0c54 vqrdmlsh.s16 q0, q1, q2
|
||||
98: ff21 0c12 vqrdmlsh.s32 d0, d1, d2
|
||||
9c: ff22 0c54 vqrdmlsh.s32 q0, q1, q2
|
||||
a0: ef91 0e42 vqrdmlah.s16 d0, d1, d2\[0\]
|
||||
a4: ef91 0e4a vqrdmlah.s16 d0, d1, d2\[1\]
|
||||
a8: ef91 0e62 vqrdmlah.s16 d0, d1, d2\[2\]
|
||||
ac: ef91 0e6a vqrdmlah.s16 d0, d1, d2\[3\]
|
||||
b0: ff92 0e42 vqrdmlah.s16 q0, q1, d2\[0\]
|
||||
b4: ff92 0e4a vqrdmlah.s16 q0, q1, d2\[1\]
|
||||
b8: ff92 0e62 vqrdmlah.s16 q0, q1, d2\[2\]
|
||||
bc: ff92 0e6a vqrdmlah.s16 q0, q1, d2\[3\]
|
||||
c0: efa1 0e42 vqrdmlah.s32 d0, d1, d2\[0\]
|
||||
c4: efa1 0e62 vqrdmlah.s32 d0, d1, d2\[1\]
|
||||
c8: ffa2 0e42 vqrdmlah.s32 q0, q1, d2\[0\]
|
||||
cc: ffa2 0e62 vqrdmlah.s32 q0, q1, d2\[1\]
|
||||
d0: ef91 0f42 vqrdmlsh.s16 d0, d1, d2\[0\]
|
||||
d4: ef91 0f4a vqrdmlsh.s16 d0, d1, d2\[1\]
|
||||
d8: ef91 0f62 vqrdmlsh.s16 d0, d1, d2\[2\]
|
||||
dc: ef91 0f6a vqrdmlsh.s16 d0, d1, d2\[3\]
|
||||
e0: ff92 0f42 vqrdmlsh.s16 q0, q1, d2\[0\]
|
||||
e4: ff92 0f4a vqrdmlsh.s16 q0, q1, d2\[1\]
|
||||
e8: ff92 0f62 vqrdmlsh.s16 q0, q1, d2\[2\]
|
||||
ec: ff92 0f6a vqrdmlsh.s16 q0, q1, d2\[3\]
|
||||
f0: efa1 0f42 vqrdmlsh.s32 d0, d1, d2\[0\]
|
||||
f4: efa1 0f62 vqrdmlsh.s32 d0, d1, d2\[1\]
|
||||
f8: ffa2 0f42 vqrdmlsh.s32 q0, q1, d2\[0\]
|
||||
fc: ffa2 0f62 vqrdmlsh.s32 q0, q1, d2\[1\]
|
||||
@ -1,3 +1,8 @@
|
||||
2016-03-04 Matthew Wahab <matthew.wahab@arm.com>
|
||||
|
||||
* arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA.
|
||||
(ARM_CPU_HAS_FEATURE): Add comment.
|
||||
|
||||
2015-03-03 Evgenii Stepanov <eugenis@google.com>
|
||||
|
||||
* plugin-api.h (enum ld_plugin_tag): Add LDPT_GET_SYMBOLS_V3.
|
||||
|
||||
@ -261,7 +261,7 @@
|
||||
#define ARM_ARCH_V7EM ARM_FEATURE_CORE (ARM_AEXT_V7EM, ARM_EXT2_V6T2_V8M)
|
||||
#define ARM_ARCH_V8A ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_AEXT2_V8A)
|
||||
#define ARM_ARCH_V8_1A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A, \
|
||||
CRC_EXT_ARMV8)
|
||||
CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA)
|
||||
#define ARM_ARCH_V8_2A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_2A, \
|
||||
CRC_EXT_ARMV8)
|
||||
#define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE, ARM_AEXT2_V8M)
|
||||
@ -321,6 +321,7 @@ typedef struct
|
||||
unsigned long coproc;
|
||||
} arm_feature_set;
|
||||
|
||||
/* Test whether CPU and FEAT have any features in common. */
|
||||
#define ARM_CPU_HAS_FEATURE(CPU,FEAT) \
|
||||
(((CPU).core[0] & (FEAT).core[0]) != 0 \
|
||||
|| ((CPU).core[1] & (FEAT).core[1]) != 0 \
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user