darlinghq/darling-gdb
1
0
Fork 0
mirror of https://github.com/darlinghq/darling-gdb.git synced 2025-01-24 10:24:55 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

* config/atof-ieee.c, config/obj-coff.c, config/obj-elf.c,

Browse Source 
config/obj-ieee.c, config/obj-som.c, config/obj-vms.c,
	config/tc-a29k.c, config/tc-alpha.c, config/tc-arc.c,
	config/tc-arm.c, config/tc-d30v.c, config/tc-dlx.c,
	config/tc-fr30.c, config/tc-h8300.c, config/tc-h8500.c,
	config/tc-i370.c, config/tc-i386.c, config/tc-i960.c,
	config/tc-ia64.c, config/tc-m32r.c, config/tc-m32r.h,
	config/tc-m68hc11.c, config/tc-m68hc11.h, config/tc-mips.c,
	config/tc-mn10200.c, config/tc-msp430.c, config/tc-ns32k.c,
	config/tc-openrisc.c, config/tc-or32.c, config/tc-pdp11.c,
	config/tc-pj.c, config/tc-sparc.h, config/tc-tic54x.c,
	config/tc-tic80.c, config/tc-v850.c, config/tc-w65.c,
	config/tc-xtensa.c, config/tc-z8k.c, config/xtensa-relax.c: Remove
	#if 0'd code throughout.
This commit is contained in:
Ben Elliston 2005-01-31 23:18:35 +00:00
parent 0e71e4955c
commit 65ec77d245
40 changed files with 23 additions and 1453 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
gas/ChangeLog
View File

@ -1,3 +1,20 @@
2005-02-01 Ben Elliston <bje@au.ibm.com>
* config/atof-ieee.c, config/obj-coff.c, config/obj-elf.c,
config/obj-ieee.c, config/obj-som.c, config/obj-vms.c,
config/tc-a29k.c, config/tc-alpha.c, config/tc-arc.c,
config/tc-arm.c, config/tc-d30v.c, config/tc-dlx.c,
config/tc-fr30.c, config/tc-h8300.c, config/tc-h8500.c,
config/tc-i370.c, config/tc-i386.c, config/tc-i960.c,
config/tc-ia64.c, config/tc-m32r.c, config/tc-m32r.h,
config/tc-m68hc11.c, config/tc-m68hc11.h, config/tc-mips.c,
config/tc-mn10200.c, config/tc-msp430.c, config/tc-ns32k.c,
config/tc-openrisc.c, config/tc-or32.c, config/tc-pdp11.c,
config/tc-pj.c, config/tc-sparc.h, config/tc-tic54x.c,
config/tc-tic80.c, config/tc-v850.c, config/tc-w65.c,
config/tc-xtensa.c, config/tc-z8k.c, config/xtensa-relax.c: Remove
#if 0'd code throughout.
2005-01-31 Nick Clifton <nickc@redhat.com>
* as.c (parse_args): Bump copyright date reported by --version to

24
gas/config/atof-ieee.c
View File

@ -673,35 +673,11 @@ gen_to_words (words, precision, exponent_bits)
but return a floating exception because we can't encode
the number. */
*words &= ~(1 << (LITTLENUM_NUMBER_OF_BITS - 1));
#if 0
make_invalid_floating_point_number (words);
return return_value;
#endif
}
}
return return_value;
}
#if 0
/* Unused. */
/* This routine is a real kludge. Someone really should do it better,
but I'm too lazy, and I don't understand this stuff all too well
anyway. (JF) */
static void
int_to_gen (x)
long x;
{
char buf[20];
char *bufp;
sprintf (buf, "%ld", x);
bufp = &buf[0];
if (atof_generic (&bufp, ".", EXP_CHARS, &generic_floating_point_number))
as_bad (_("Error converting number to floating point (Exponent overflow?)"));
}
#endif
#ifdef TEST
char *
print_gen (gen)

98
gas/config/obj-coff.c
View File

@ -112,17 +112,6 @@ stack_init (chunk_size, element_size)
return st;
}
#if 0
/* Not currently used. */
static void
stack_delete (st)
stack *st;
{
free (st->data);
free (st);
}
#endif
static char *
stack_push (st, element)
stack *st;
@ -2854,9 +2843,6 @@ obj_coff_line (ignore)
start of the containing function. */
if (!strcmp (".bf", name))
{
#if 0 /* XXX Can we ever have line numbers going backwards? */
if (this_base > line_base)
#endif
line_base = this_base;
#ifndef NO_LISTING
@ -3174,13 +3160,6 @@ yank_symbols ()
if (S_GET_NUMBER_AUXILIARY (symbolP) < 1)
S_SET_NUMBER_AUXILIARY (symbolP, 1);
/* Clobber possible stale .dim information. */
#if 0
/* Iffed out by steve - this fries the lnnoptr info too. */
bzero (symbolP->sy_symbol.ost_auxent[0].x_sym.x_fcnary.x_ary.x_dimen,
sizeof (symbolP->sy_symbol.ost_auxent[0].x_sym.x_fcnary.x_ary.x_dimen));
#endif
}
if (S_GET_STORAGE_CLASS (symbolP) == C_FCN)
{
@ -3773,19 +3752,10 @@ write_object_file ()
}
coff_header_append (abfd, &headers);
#if 0
/* Recent changes to write need this, but where it should
go is up to Ken.. */
if (!bfd_close_all_done (abfd))
as_fatal (_("Can't close %s: %s"), out_file_name,
bfd_errmsg (bfd_get_error ()));
#else
{
extern bfd *stdoutput;
stdoutput = abfd;
}
#endif
}
/* Add a new segment. This is called from subseg_new via the
@ -4180,68 +4150,8 @@ static void
obj_coff_lcomm (ignore)
int ignore ATTRIBUTE_UNUSED;
{
s_lcomm(0);
s_lcomm (0);
return;
#if 0
char *name;
char c;
int temp;
char *p;
symbolS *symbolP;
name = input_line_pointer;
c = get_symbol_end ();
p = input_line_pointer;
*p = c;
SKIP_WHITESPACE ();
if (*input_line_pointer != ',')
{
as_bad (_("Expected comma after name"));
ignore_rest_of_line ();
return;
}
if (*input_line_pointer == '\n')
{
as_bad (_("Missing size expression"));
return;
}
input_line_pointer++;
if ((temp = get_absolute_expression ()) < 0)
{
as_warn (_("lcomm length (%d.) <0! Ignored."), temp);
ignore_rest_of_line ();
return;
}
*p = 0;
symbolP = symbol_find_or_make (name);
if (S_GET_SEGMENT (symbolP) == SEG_UNKNOWN &&
S_GET_VALUE (symbolP) == 0)
{
if (! need_pass_2)
{
char *p;
segT current_seg = now_seg; /* Save current seg. */
subsegT current_subseg = now_subseg;
subseg_set (SEG_E2, 1);
symbolP->sy_frag = frag_now;
p = frag_var(rs_org, 1, 1, (relax_substateT)0, symbolP,
(offsetT) temp, (char *) 0);
*p = 0;
subseg_set (current_seg, current_subseg); /* Restore current seg. */
S_SET_SEGMENT (symbolP, SEG_E2);
S_SET_STORAGE_CLASS (symbolP, C_STAT);
}
}
else
as_bad (_("Symbol %s already defined"), name);
demand_empty_rest_of_line ();
#endif
}
static void
@ -4457,11 +4367,7 @@ fixup_segment (segP, this_segment_type)
add_number -= S_GET_VALUE (sub_symbolP);
#ifdef DIFF_EXPR_OK
else if (S_GET_SEGMENT (sub_symbolP) == this_segment_type
#if 0 /* Okay for 68k, at least... */
&& !pcrel
#endif
)
else if (S_GET_SEGMENT (sub_symbolP) == this_segment_type)
{
/* Make it pc-relative. */
add_number += (md_pcrel_from (fixP)

11
gas/config/obj-elf.c
View File

@ -1815,17 +1815,6 @@ elf_frob_symbol (symbolS *symp, int *puntp)
&& (symbol_get_bfdsym (symp)->flags & BSF_FUNCTION) == 0)
symbol_get_bfdsym (symp)->flags |= BSF_OBJECT;
#endif
#if 0 /* TC_PPC */
/* If TC_PPC is defined, we used to force the type of a symbol to be
BSF_OBJECT if it was otherwise unset. This was required by some
version of VxWorks. Thomas de Lellis <tdel@windriver.com> says
that this is no longer needed, so it is now commented out. */
if ((symbol_get_bfdsym (symp)->flags
& (BSF_FUNCTION | BSF_FILE | BSF_SECTION_SYM)) == 0
&& S_IS_DEFINED (symp))
symbol_get_bfdsym (symp)->flags |= BSF_OBJECT;
#endif
}
struct group_list

20
gas/config/obj-ieee.c
View File

@ -209,12 +209,6 @@ do_relocs_for (idx)
reloc_ptr_vector[i] = to;
to->howto = (reloc_howto_type *) (from->fx_r_type);
#if 0
/* We can't represent complicated things in a reloc yet. */
if (from->fx_addsy == 0 || from->fx_subsy != 0)
abort ();
#endif
s = &(from->fx_addsy->sy_symbol.sy);
to->address = ((char *) (from->fx_frag->fr_address +
from->fx_where))
@ -561,21 +555,7 @@ write_object_file ()
fragS **prev_frag_ptr_ptr;
struct frchain *next_frchain_ptr;
#if 0
struct frag **head_ptr = segment_info[i].frag_root;
#endif
segment_info[i].frag_root = segment_info[i].frchainP->frch_root;
#if 0
/* I'm not sure what this is for. */
for (frchain_ptr = segment_info[i].frchainP->frch_root;
frchain_ptr != (struct frchain *) NULL;
frchain_ptr = frchain_ptr->frch_next)
{
*head_ptr = frchain_ptr;
head_ptr = &frchain_ptr->next;
}
#endif
}
for (i = SEG_E0; i < SEG_UNKNOWN; i++)

3
gas/config/obj-som.c
View File

@ -332,9 +332,6 @@ obj_som_weak (ignore)
*input_line_pointer = c;
SKIP_WHITESPACE ();
S_SET_WEAK (symbolP);
#if 0
symbol_get_obj (symbolP)->local = 1;
#endif
if (c == ',')
{
input_line_pointer++;

87
gas/config/obj-vms.c
View File

@ -403,16 +403,6 @@ vms_check_for_special_label (symbolS *symbolP)
if (!strcmp (sym_name, "__vax_g_doubles"))
vax_g_doubles = 1;
#if 0 /* not necessary */
else if (!strcmp (sym_name, "__vax_d_doubles"))
vax_g_doubles = 0;
#endif
#if 0 /* These are potential alternatives to tc-vax.c's md_parse_options(). */
else if (!strcmp (sym_name, "gcc_compiled."))
flag_one = 1;
else if (!strcmp (sym_name, "__gnu_language_cplusplus"))
flag_hash_long_names = 1;
#endif
}
}
@ -839,15 +829,6 @@ VMS_TBT_Routine_End (int Max_Size, symbolS *sp)
Size = sym_value;
/* Dummy labels like "gcc_compiled." should no longer reach here. */
#if 0
else
/* Check if gcc_compiled. has size of zero. */
if (sym_value == sp_value &&
sp != symbolP &&
(!strcmp (S_GET_NAME (sp), "gcc_compiled.") ||
!strcmp (S_GET_NAME (sp), "gcc2_compiled.")))
Size = sym_value;
#endif
}
}
if (Size == 0x7fffffff)
@ -1339,41 +1320,6 @@ find_symbol (int dbx_type)
return find_symbol (spnt->type2);
}
#if 0 /* obsolete */
/* This routine puts info into either Local or Asuffix, depending on the sign
of size. The reason is that it is easier to build the variable descriptor
backwards, while the array descriptor is best built forwards. In the end
they get put together, if there is not a struct/union/enum along the way. */
static void
push (int value, int size1)
{
if (size1 < 0)
{
size1 = -size1;
if (Lpnt < size1)
{
overflow = 1;
Lpnt = 1;
return;
}
Lpnt -= size1;
md_number_to_chars (&Local[Lpnt + 1], value, size1);
}
else
{
if (Apoint + size1 >= MAX_DEBUG_RECORD)
{
overflow = 1;
Apoint = MAX_DEBUG_RECORD - 1;
return;
}
md_number_to_chars (&Asuffix[Apoint], value, size1);
Apoint += size1;
}
}
#endif
static void
fpush (int value, int size)
{
@ -3019,11 +2965,6 @@ VMS_Case_Hack_Symbol (const char *In, char *Out)
new_name = Out; /* Save this for later. */
#if 0
if ((In[0] == '_') && (In[1] == '$') && (In[2] == '_'))
destructor = 1;
#endif
/* We may need to truncate the symbol, save the hash for later. */
result = (strlen (In) > 23) ? hash_string (In) : 0;
/* Is there a Psect Attribute to skip? */
@ -3043,10 +2984,6 @@ VMS_Case_Hack_Symbol (const char *In, char *Out)
}
old_name = In;
#if 0
if (strlen (In) > 31 && flag_hash_long_names)
as_tsktsk ("Symbol name truncated: %s\n", In);
#endif
/* Do the case conversion. */
/* Maximum of 23 chars */
i = 23;
@ -4288,26 +4225,6 @@ global_symbol_directory (unsigned text_siz, unsigned data_siz)
struct VMS_Symbol *vsp;
int Globalref, define_as_global_symbol;
#if 0
/* The g++ compiler does not write out external references to
vtables correctly. Check for this and holler if we see it
happening. If that compiler bug is ever fixed we can remove
this.
(Jun'95: gcc 2.7.0's cc1plus still exhibits this behavior.)
This was reportedly fixed as of June 2, 1998. */
for (sp = symbol_rootP; sp; sp = symbol_next (sp))
if (S_GET_RAW_TYPE (sp) == N_UNDF && IS_GXX_VTABLE (sp))
{
S_SET_TYPE (sp, N_UNDF | N_EXT);
S_SET_OTHER (sp, 1);
as_warn (_("g++ wrote an extern reference to `%s' as a routine.\nI will fix it, but I hope that it was note really a routine."),
S_GET_NAME (sp));
}
#endif
/* Now scan the symbols and emit the appropriate GSD records. */
for (sp = symbol_rootP; sp; sp = symbol_next (sp))
{
@ -4550,10 +4467,6 @@ local_symbols_DST (symbolS *s0P, symbolS *Current_Routine)
for (s1P = Current_Routine; s1P; s1P = symbol_next (s1P))
{
#if 0 /* redundant; RAW_TYPE != N_FUN suffices */
if (!S_IS_DEBUG (s1P))
continue;
#endif
if (S_GET_RAW_TYPE (s1P) != N_FUN)
continue;
pnt0 = s0P_name;

57
gas/config/tc-a29k.c
View File

@ -945,63 +945,6 @@ md_estimate_size_before_relax (fragP, segtype)
return 0;
}
#if 0
/* for debugging only */
static void
print_insn (insn)
struct machine_it *insn;
{
char *Reloc[] =
{
"RELOC_8",
"RELOC_16",
"RELOC_32",
"RELOC_DISP8",
"RELOC_DISP16",
"RELOC_DISP32",
"RELOC_WDISP30",
"RELOC_WDISP22",
"RELOC_HI22",
"RELOC_22",
"RELOC_13",
"RELOC_LO10",
"RELOC_SFA_BASE",
"RELOC_SFA_OFF13",
"RELOC_BASE10",
"RELOC_BASE13",
"RELOC_BASE22",
"RELOC_PC10",
"RELOC_PC22",
"RELOC_JMP_TBL",
"RELOC_SEGOFF16",
"RELOC_GLOB_DAT",
"RELOC_JMP_SLOT",
"RELOC_RELATIVE",
"NO_RELOC"
};
if (insn->error)
{
fprintf (stderr, "ERROR: %s\n");
}
fprintf (stderr, "opcode=0x%08x\n", insn->opcode);
fprintf (stderr, "reloc = %s\n", Reloc[insn->reloc]);
fprintf (stderr, "exp = {\n");
fprintf (stderr, "\t\tX_add_symbol = %s\n",
insn->exp.X_add_symbol ?
(S_GET_NAME (insn->exp.X_add_symbol) ?
S_GET_NAME (insn->exp.X_add_symbol) : "???") : "0");
fprintf (stderr, "\t\tX_op_symbol = %s\n",
insn->exp.X_op_symbol ?
(S_GET_NAME (insn->exp.X_op_symbol) ?
S_GET_NAME (insn->exp.X_op_symbol) : "???") : "0");
fprintf (stderr, "\t\tX_add_number = %d\n",
insn->exp.X_add_number);
fprintf (stderr, "}\n");
}
#endif
/* Translate internal representation of relocation info to target format.
On sparc/29k: first 4 bytes are normal unsigned long address, next three

39
gas/config/tc-alpha.c
View File

@ -308,12 +308,8 @@ const char EXP_CHARS[] = "eE";
/* Characters which mean that a number is a floating point constant,
as in 0d1.0. */
#if 0
const char FLT_CHARS[] = "dD";
#else
/* XXX: Do all of these really get used on the alpha?? */
char FLT_CHARS[] = "rRsSfFdDxXpP";
#endif
#ifdef OBJ_EVAX
const char *md_shortopts = "Fm:g+1h:HG:";
@ -657,18 +653,6 @@ static const struct alpha_macro alpha_macros[] =
{ MACRO_IR, MACRO_EXP, MACRO_EOA } },
{ "ldiq", emit_lda, NULL,
{ MACRO_IR, MACRO_EXP, MACRO_EOA } },
#if 0
{ "ldif" emit_ldiq, NULL,
{ MACRO_FPR, MACRO_EXP, MACRO_EOA } },
{ "ldid" emit_ldiq, NULL,
{ MACRO_FPR, MACRO_EXP, MACRO_EOA } },
{ "ldig" emit_ldiq, NULL,
{ MACRO_FPR, MACRO_EXP, MACRO_EOA } },
{ "ldis" emit_ldiq, NULL,
{ MACRO_FPR, MACRO_EXP, MACRO_EOA } },
{ "ldit" emit_ldiq, NULL,
{ MACRO_FPR, MACRO_EXP, MACRO_EOA } },
#endif
{ "stl", emit_loadstore, "stl",
{ MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
@ -701,14 +685,6 @@ static const struct alpha_macro alpha_macros[] =
{ MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
/* Arithmetic macros */
#if 0
{ "absl" emit_absl, 1, { IR } },
{ "absl" emit_absl, 2, { IR, IR } },
{ "absl" emit_absl, 2, { EXP, IR } },
{ "absq" emit_absq, 1, { IR } },
{ "absq" emit_absq, 2, { IR, IR } },
{ "absq" emit_absq, 2, { EXP, IR } },
#endif
{ "sextb", emit_sextX, (PTR) 0,
{ MACRO_IR, MACRO_IR, MACRO_EOA,
@ -5466,15 +5442,6 @@ static void
s_alpha_base (ignore)
int ignore ATTRIBUTE_UNUSED;
{
#if 0
if (first_32bit_quadrant)
{
/* not fatal, but it might not work in the end */
as_warn (_("File overrides no-base-register option."));
first_32bit_quadrant = 0;
}
#endif
SKIP_WHITESPACE ();
if (*input_line_pointer == '$')
{ /* $rNN form */
@ -5811,12 +5778,6 @@ select_gp_value ()
/* Select the smallest VMA of these existing sections. */
maybe_set_gp (alpha_lita_section);
#if 0
/* These were disabled before -- should we use them? */
maybe_set_gp (sdata);
maybe_set_gp (lit8_sec);
maybe_set_gp (lit4_sec);
#endif
/* @@ Will a simple 0x8000 work here? If not, why not? */
#define GP_ADJUSTMENT (0x8000 - 0x10)

9
gas/config/tc-arc.c
View File

@ -1845,9 +1845,6 @@ md_apply_fix3 (fixP, valP, seg)
valueT * valP;
segT seg;
{
#if 0
char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
#endif
valueT value = * valP;
if (fixP->fx_addsy == (symbolS *) NULL)
@ -1946,12 +1943,6 @@ md_apply_fix3 (fixP, valP, seg)
md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
value, 4);
break;
#if 0
case BFD_RELOC_64:
md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
value, 8);
break;
#endif
case BFD_RELOC_ARC_B26:
/* If !fixP->fx_done then `value' is an implicit addend.
We must shift it right by 2 in this case as well because the

130
gas/config/tc-arm.c
View File

@ -2683,18 +2683,6 @@ do_msr (char * str)
return;
}
#if 0 /* The first edition of the ARM architecture manual stated that
writing anything other than the flags with an immediate operation
had UNPREDICTABLE effects. This constraint was removed in the
second edition of the specification. */
if ((cpu_variant & ARM_EXT_V5) != ARM_EXT_V5
&& inst.instruction & ((PSR_c | PSR_x | PSR_s) << PSR_SHIFT))
{
inst.error = _("immediate value cannot be used to set this field");
return;
}
#endif
inst.instruction |= INST_IMMEDIATE;
if (inst.reloc.exp.X_add_symbol)
@ -10882,55 +10870,6 @@ build_arm_ops_hsh (void)
}
}
#if 0 /* Suppressed - for now. */
#if defined OBJ_ELF || defined OBJ_COFF
#ifdef OBJ_ELF
#define arm_Note Elf_External_Note
#else
typedef struct
{
unsigned char namesz[4]; /* Size of entry's owner string. */
unsigned char descsz[4]; /* Size of the note descriptor. */
unsigned char type[4]; /* Interpretation of the descriptor. */
char name[1]; /* Start of the name+desc data. */
} arm_Note;
#endif
/* The description is kept to a fix sized in order to make updating
it and merging it easier. */
#define ARM_NOTE_DESCRIPTION_LENGTH 8
static void
arm_add_note (const char * name,
const char * description,
unsigned int type)
{
arm_Note note ATTRIBUTE_UNUSED;
char * p;
unsigned int name_len;
name_len = (strlen (name) + 1 + 3) & ~3;
p = frag_more (sizeof (note.namesz));
md_number_to_chars (p, (valueT) name_len, sizeof (note.namesz));
p = frag_more (sizeof (note.descsz));
md_number_to_chars (p, (valueT) ARM_NOTE_DESCRIPTION_LENGTH, sizeof (note.descsz));
p = frag_more (sizeof (note.type));
md_number_to_chars (p, (valueT) type, sizeof (note.type));
p = frag_more (name_len);
strcpy (p, name);
p = frag_more (ARM_NOTE_DESCRIPTION_LENGTH);
strncpy (p, description, ARM_NOTE_DESCRIPTION_LENGTH);
frag_align (2, 0, 0);
}
#endif
#endif
static const struct thumb_opcode tinsns[] =
{
@ -11208,62 +11147,6 @@ md_begin (void)
else if (cpu_variant & ARM_EXT_V3M)
mach = bfd_mach_arm_3M;
#if 0 /* Suppressed - for now. */
#if defined (OBJ_ELF) || defined (OBJ_COFF)
/* Create a .note section to fully identify this arm binary. */
#define NOTE_ARCH_STRING "arch: "
#if defined OBJ_COFF && ! defined NT_VERSION
#define NT_VERSION 1
#define NT_ARCH 2
#endif
{
segT current_seg = now_seg;
subsegT current_subseg = now_subseg;
asection * arm_arch;
const char * arch_string;
arm_arch = bfd_make_section_old_way (stdoutput, ARM_NOTE_SECTION);
#ifdef OBJ_COFF
bfd_set_section_flags (stdoutput, arm_arch,
SEC_DATA | SEC_ALLOC | SEC_LOAD | SEC_LINK_ONCE \
| SEC_HAS_CONTENTS);
#else
bfd_set_section_flags (stdoutput, arm_arch,
SEC_READONLY | SEC_HAS_CONTENTS);
#endif
arm_arch->output_section = arm_arch;
subseg_set (arm_arch, 0);
switch (mach)
{
default:
case bfd_mach_arm_unknown: arch_string = "unknown"; break;
case bfd_mach_arm_2: arch_string = "armv2"; break;
case bfd_mach_arm_2a: arch_string = "armv2a"; break;
case bfd_mach_arm_3: arch_string = "armv3"; break;
case bfd_mach_arm_3M: arch_string = "armv3M"; break;
case bfd_mach_arm_4: arch_string = "armv4"; break;
case bfd_mach_arm_4T: arch_string = "armv4t"; break;
case bfd_mach_arm_5: arch_string = "armv5"; break;
case bfd_mach_arm_5T: arch_string = "armv5t"; break;
case bfd_mach_arm_5TE: arch_string = "armv5te"; break;
case bfd_mach_arm_XScale: arch_string = "XScale"; break;
case bfd_mach_arm_ep9312: arch_string = "ep9312"; break;
case bfd_mach_arm_iWMMXt: arch_string = "iWMMXt"; break;
}
arm_add_note (NOTE_ARCH_STRING, arch_string, NT_ARCH);
subseg_set (current_seg, current_subseg);
}
#endif
#endif /* Suppressed code. */
bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
}
@ -11481,14 +11364,7 @@ md_apply_fix3 (fixS * fixP,
assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
/* Note whether this will delete the relocation. */
#if 0
/* Patch from REarnshaw to JDavis (disabled for the moment, since it
doesn't work fully.) */
if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy))
&& !fixP->fx_pcrel)
#else
if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
#endif
fixP->fx_done = 1;
/* If this symbol is in a different section then we need to leave it for
@ -12434,12 +12310,6 @@ md_assemble (char * str)
char *p;
char *start;
/* Align the instruction.
This may not be the right thing to do but ... */
#if 0
arm_align (2, 0);
#endif
/* Align the previous label if needed. */
if (last_label_seen != NULL)
{

16
gas/config/tc-d30v.c
View File

@ -926,9 +926,6 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
as_fatal (_("unknown execution type passed to write_2_short()"));
}
#if 0
printf ("writing out %llx\n", insn);
#endif
f = frag_more (8);
d30v_number_to_chars (f, insn, 8);
@ -1477,9 +1474,6 @@ do_assemble (str, opcode, shortp, is_parallel)
as_bad (_("unknown condition code: %s"), tmp);
return -1;
}
#if 0
printf ("condition code=%d\n", i);
#endif
opcode->ecc = i;
op_end += 3;
}
@ -1521,10 +1515,6 @@ do_assemble (str, opcode, shortp, is_parallel)
else
cmp_hack = 0;
#if 0
printf ("cmp_hack=%d\n", cmp_hack);
#endif
/* Need to look for .s or .l. */
if (name[nlen - 2] == '.')
{
@ -1758,9 +1748,6 @@ find_format (opcode, myops, fsize, cmp_hack)
match = 0;
}
}
#if 0
printf ("through the loop: match=%d\n", match);
#endif
/* We're only done if the operands matched so far AND there
are no more to check. */
if (match && myops[j].X_op == 0)
@ -1779,9 +1766,6 @@ find_format (opcode, myops, fsize, cmp_hack)
}
fm = (struct d30v_format *) &d30v_format_table[++k];
}
#if 0
printf ("trying another format: i=%d\n", i);
#endif
}
return NULL;
}

89
gas/config/tc-dlx.c
View File

@ -24,9 +24,6 @@
#include "as.h"
#include "tc-dlx.h"
#include "opcode/dlx.h"
#if 0
#include "elf/dlx.h"
#endif
/* Make it easier to clone this machine desc into another one. */
#define machine_opcode dlx_opcode
@ -140,41 +137,6 @@ insert_sreg (regname, regnum)
static void
define_some_regs ()
{
#if 0
/* Hardware representation. */
insert_sreg ("r0", 0);
insert_sreg ("r1", 1);
insert_sreg ("r2", 2);
insert_sreg ("r3", 3);
insert_sreg ("r4", 4);
insert_sreg ("r5", 5);
insert_sreg ("r6", 6);
insert_sreg ("r7", 7);
insert_sreg ("r8", 8);
insert_sreg ("r9", 9);
insert_sreg ("r10", 10);
insert_sreg ("r11", 11);
insert_sreg ("r12", 12);
insert_sreg ("r13", 13);
insert_sreg ("r14", 14);
insert_sreg ("r15", 15);
insert_sreg ("r16", 16);
insert_sreg ("r17", 17);
insert_sreg ("r18", 18);
insert_sreg ("r19", 19);
insert_sreg ("r20", 20);
insert_sreg ("r21", 21);
insert_sreg ("r22", 22);
insert_sreg ("r23", 23);
insert_sreg ("r24", 24);
insert_sreg ("r25", 25);
insert_sreg ("r26", 26);
insert_sreg ("r27", 27);
insert_sreg ("r28", 28);
insert_sreg ("r29", 29);
insert_sreg ("r30", 30);
insert_sreg ("r31", 31);
#endif
/* Software representation. */
insert_sreg ("zero", 0);
insert_sreg ("at", 1);
@ -1337,33 +1299,6 @@ md_operand (expressionP)
}
return;
#if 0
else if (input_line_pointer[0] == '$'
&& ISDIGIT ((unsigned char) input_line_pointer[1]))
{
long lab;
char *name;
symbolS *sym;
/* This is a local label. */
++input_line_pointer;
lab = (long) get_absolute_expression ();
if (dollar_label_defined (lab))
{
name = dollar_label_name (lab, 0);
sym = symbol_find (name);
}
else
{
name = dollar_label_name (lab, 1);
sym = symbol_find_or_make (name);
}
expressionP->X_op = O_symbol;
expressionP->X_add_symbol = sym;
expressionP->X_add_number = 0;
}
#endif
}
/* Round up a section size to the appropriate boundary. */
@ -1388,30 +1323,6 @@ md_pcrel_from (fixP)
return 4 + fixP->fx_where + fixP->fx_frag->fr_address;
}
/* From cgen.c: */
#if 0
static short
tc_bfd_fix2rtype (fixP)
fixS* fixP;
{
#if 0
if (fixP->fx_bsr)
abort ();
#endif
if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
return BFD_RELOC_32;
if (fixP->fx_pcrel != 0 && fixP->fx_size == 4)
return BFD_RELOC_26_PCREL;
abort ();
return 0;
}
#endif
/* Translate internal representation of relocation info to BFD target
format.
FIXME: To what extent can we get all relevant targets to use this?

146
gas/config/tc-fr30.c
View File

@ -203,50 +203,6 @@ const relax_typeS md_relax_table[] =
{0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
};
#if 0
long
fr30_relax_frag (segment, fragP, stretch)
segT segment;
fragS * fragP;
long stretch;
{
/* Address of branch insn. */
long address = fragP->fr_address + fragP->fr_fix - 2;
long growth = 0;
/* Keep 32 bit insns aligned on 32 bit boundaries. */
if (fragP->fr_subtype == 2)
{
if ((address & 3) != 0)
{
fragP->fr_subtype = 3;
growth = 2;
}
}
else if (fragP->fr_subtype == 3)
{
if ((address & 3) == 0)
{
fragP->fr_subtype = 2;
growth = -2;
}
}
else
{
growth = relax_frag (segment, fragP, stretch);
/* Long jump on odd halfword boundary? */
if (fragP->fr_subtype == 2 && (address & 3) != 0)
{
fragP->fr_subtype = 3;
growth += 2;
}
}
return growth;
}
#endif
/* Return an initial guess of the length by which a fragment must grow to
hold a branch to reach its destination.
Also updates fr_type/fr_subtype as necessary.
@ -271,34 +227,11 @@ md_estimate_size_before_relax (fragP, segment)
if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
{
#if 0
int old_fr_fix = fragP->fr_fix;
#endif
/* The symbol is undefined in this segment.
Change the relaxation subtype to the max allowable and leave
all further handling to md_convert_frag. */
fragP->fr_subtype = 2;
#if 0 /* Can't use this, but leave in for illustration. */
/* Change 16 bit insn to 32 bit insn. */
fragP->fr_opcode[0] |= 0x80;
/* Increase known (fixed) size of fragment. */
fragP->fr_fix += 2;
/* Create a relocation for it. */
fix_new (fragP, old_fr_fix, 4,
fragP->fr_symbol,
fragP->fr_offset, 1 /* pcrel */,
/* FIXME: Can't use a real BFD reloc here.
gas_cgen_md_apply_fix3 can't handle it. */
BFD_RELOC_FR30_26_PCREL);
/* Mark this fragment as finished. */
frag_wane (fragP);
return fragP->fr_fix - old_fr_fix;
#else
{
const CGEN_INSN * insn;
int i;
@ -321,7 +254,6 @@ md_estimate_size_before_relax (fragP, segment)
fragP->fr_cgen.insn = insn;
return 2;
}
#endif
}
/* Return the size of the variable part of the frag. */
@ -341,84 +273,6 @@ md_convert_frag (abfd, sec, fragP)
segT sec ATTRIBUTE_UNUSED;
fragS *fragP ATTRIBUTE_UNUSED;
{
#if 0
char * opcode;
char * displacement;
int target_address;
int opcode_address;
int extension;
int addend;
opcode = fragP->fr_opcode;
/* Address opcode resides at in file space. */
opcode_address = fragP->fr_address + fragP->fr_fix - 2;
switch (fragP->fr_subtype)
{
case 1 :
extension = 0;
displacement = & opcode[1];
break;
case 2 :
opcode[0] |= 0x80;
extension = 2;
displacement = & opcode[1];
break;
case 3 :
opcode[2] = opcode[0] | 0x80;
md_number_to_chars (opcode, PAR_NOP_INSN, 2);
opcode_address += 2;
extension = 4;
displacement = & opcode[3];
break;
default :
abort ();
}
if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
{
/* symbol must be resolved by linker */
if (fragP->fr_offset & 3)
as_warn (_("Addend to unresolved symbol not on word boundary."));
addend = fragP->fr_offset >> 2;
}
else
{
/* Address we want to reach in file space. */
target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
addend = (target_address - (opcode_address & -4)) >> 2;
}
/* Create a relocation for symbols that must be resolved by the linker.
Otherwise output the completed insn. */
if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
{
assert (fragP->fr_subtype != 1);
assert (fragP->fr_cgen.insn != 0);
gas_cgen_record_fixup (fragP,
/* Offset of branch insn in frag. */
fragP->fr_fix + extension - 4,
fragP->fr_cgen.insn,
4 /*length*/,
/* FIXME: quick hack */
#if 0
CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
#else
CGEN_OPERAND_ENTRY (FR30_OPERAND_DISP24),
#endif
fragP->fr_cgen.opinfo,
fragP->fr_symbol, fragP->fr_offset);
}
#define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
md_number_to_chars (displacement, (valueT) addend,
SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
fragP->fr_fix += extension;
#endif
}
/* Functions concerning relocs. */

9
gas/config/tc-h8300.c
View File

@ -1193,15 +1193,6 @@ get_specific (const struct h8_instruction *instruction,
x |= x_size = L_32;
}
#if 0 /* ??? */
/* Promote an L8 to L_16 if it makes us match. */
if ((op_mode == ABS || op_mode == DISP) && x_size == L_8)
{
if (op_size == L_16)
x_size = L_16;
}
#endif
if (((x_size == L_16 && op_size == L_16U)
|| (x_size == L_8 && op_size == L_8U)
|| (x_size == L_3 && op_size == L_3NZ))

4
gas/config/tc-h8500.c
View File

@ -1576,10 +1576,6 @@ tc_reloc_mangle (fix_ptr, intr, base)
dot = segment_info[S_GET_SEGMENT (symbol_ptr)].dot;
if (dot)
{
#if 0
intr->r_offset -=
segment_info[S_GET_SEGMENT (symbol_ptr)].scnhdr.s_paddr;
#endif
intr->r_offset += S_GET_VALUE (symbol_ptr);
intr->r_symndx = dot->sy_number;
}

66
gas/config/tc-i370.c
View File

@ -687,11 +687,6 @@ i370_elf_suffix (str_p, exp_p)
static struct map_bfd mapping[] =
{
#if 0
MAP ("l", BFD_RELOC_LO16),
MAP ("h", BFD_RELOC_HI16),
MAP ("ha", BFD_RELOC_HI16_S),
#endif
/* warnings with -mrelocatable. */
MAP ("fixup", BFD_RELOC_CTOR),
{ (char *)0, 0, BFD_RELOC_UNUSED }
@ -2453,60 +2448,6 @@ i370_macro (str, macro)
/* Assemble the constructed instruction. */
md_assemble (complete);
}
#if 0
/* For ELF, add support for SHF_EXCLUDE and SHT_ORDERED */
int
i370_section_letter (letter, ptr_msg)
int letter;
char **ptr_msg;
{
if (letter == 'e')
return SHF_EXCLUDE;
*ptr_msg = "Bad .section directive: want a,e,w,x,M,S in string";
return 0;
}
int
i370_section_word (str, len)
char *str;
size_t len;
{
if (len == 7 && strncmp (str, "exclude", 7) == 0)
return SHF_EXCLUDE;
return -1;
}
int
i370_section_type (str, len)
char *str;
size_t len;
{
if (len == 7 && strncmp (str, "ordered", 7) == 0)
return SHT_ORDERED;
return -1;
}
int
i370_section_flags (flags, attr, type)
int flags;
int attr;
int type;
{
if (type == SHT_ORDERED)
flags |= SEC_ALLOC | SEC_LOAD | SEC_SORT_ENTRIES;
if (attr & SHF_EXCLUDE)
flags |= SEC_EXCLUDE;
return flags;
}
#endif /* OBJ_ELF */
/* Pseudo-op handling. */
@ -2787,13 +2728,6 @@ md_apply_fix3 (fixP, valP, seg)
Why? Because we are not expecting the compiler to generate
any operands that need relocation. Due to the 12-bit naturew of
i370 addressing, this would be unusual. */
#if 0
if ((operand->flags & I370_OPERAND_RELATIVE) != 0
&& operand->bits == 12
&& operand->shift == 0)
fixP->fx_r_type = BFD_RELOC_I370_D12;
else
#endif
{
char *sfile;
unsigned int sline;

9
gas/config/tc-i386.c
View File

@ -2489,14 +2489,7 @@ check_byte_reg (void)
|| i.tm.base_opcode == 0xfbf))
continue;
if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
#if 0
/* Check that the template allows eight bit regs. This
kills insns such as `orb $1,%edx', which maybe should be
allowed. */
&& (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
#endif
)
if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
{
/* Prohibit these changes in the 64bit mode, since the
lowering is more complicated. */

9
gas/config/tc-i960.c
View File

@ -3162,10 +3162,6 @@ tc_coff_symbol_emit_hook (symbolP)
{
symbolS *balP = tc_get_bal_of_call (symbolP);
#if 0
/* second aux entry contains the bal entry point */
S_SET_NUMBER_AUXILIARY (symbolP, 2);
#endif
symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP);
if (S_GET_STORAGE_CLASS (symbolP) == C_EXT)
S_SET_STORAGE_CLASS (symbolP, C_LEAFEXT);
@ -3238,11 +3234,6 @@ static short
tc_bfd_fix2rtype (fixP)
fixS *fixP;
{
#if 0
if (fixP->fx_bsr)
abort ();
#endif
if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
return BFD_RELOC_32;

25
gas/config/tc-ia64.c
View File

@ -5190,9 +5190,6 @@ const pseudo_typeS md_pseudo_table[] =
{ "copy_state", dot_copy_state, 0 },
{ "unwabi", dot_unwabi, 0 },
{ "personality", dot_personality, 0 },
#if 0
{ "estate", dot_estate, 0 },
#endif
{ "mii", dot_template, 0x0 },
{ "mli", dot_template, 0x2 }, /* old format, for compatibility */
{ "mlx", dot_template, 0x2 },
@ -5204,10 +5201,6 @@ const pseudo_typeS md_pseudo_table[] =
{ "bbb", dot_template, 0xb },
{ "mmb", dot_template, 0xc },
{ "mfb", dot_template, 0xe },
#if 0
{ "lb", dot_scope, 0 },
{ "le", dot_scope, 1 },
#endif
{ "align", dot_align, 0 },
{ "regstk", dot_regstk, 0 },
{ "rotr", dot_rot, DYNREG_GR },
@ -6603,11 +6596,6 @@ emit_one_bundle ()
|| idesc->operands[1] != opnd2))
idesc = get_next_opcode (idesc);
}
#if 0
else
/* no other resolved dynamic ops have collisions */
know (!get_next_opcode (idesc));
#endif
md.slot[curr].idesc = idesc;
}
else
@ -9644,10 +9632,6 @@ resources_match (rs, idesc, note, qp_regno, path)
else if (specs[count].index == rs->index)
return 1;
}
#if 0
if (md.debug_dv)
fprintf (stderr, " No %s conflicts\n", rs->dependency->name);
#endif
return 0;
}
@ -10048,12 +10032,6 @@ mark_resources (idesc)
count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
#if 0
if (md.debug_dv && !count)
fprintf (stderr, " No %s %s usage found (path %d)\n",
dv_mode[dep->mode], dep->name, md.path);
#endif
while (count-- > 0)
{
mark_resource (idesc, dep, &specs[count],
@ -10270,9 +10248,6 @@ md_assemble (str)
mnemonic = "adds";
ia64_free_opcode (idesc);
idesc = ia64_find_opcode (mnemonic);
#if 0
know (!idesc->next);
#endif
}
else if (strcmp (idesc->name, "mov") == 0)
{

99
gas/config/tc-m32r.c
View File

@ -79,13 +79,6 @@ int pic_code;
This flag does not apply to them. */
static int m32r_relax;
#if 0
/* Not supported yet. */
/* If non-NULL, pointer to cpu description file to read.
This allows runtime additions to the assembler. */
static const char *m32r_cpu_desc;
#endif
/* Non-zero if warn when a high/shigh reloc has no matching low reloc.
Each high/shigh reloc must be paired with it's low cousin in order to
properly calculate the addend in a relocatable link (since there is a
@ -246,14 +239,6 @@ struct option md_longopts[] =
{"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED},
{"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
{"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
#if 0
/* Not supported yet. */
#define OPTION_RELAX (OPTION_NO_WARN_UNMATCHED + 1)
#define OPTION_CPU_DESC (OPTION_RELAX + 1)
{"relax", no_argument, NULL, OPTION_RELAX},
{"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
#endif
{NULL, no_argument, NULL, 0}
};
@ -378,16 +363,6 @@ md_parse_option (c, arg)
pic_code = 1;
break;
#if 0
/* Not supported yet. */
case OPTION_RELAX:
m32r_relax = 1;
break;
case OPTION_CPU_DESC:
m32r_cpu_desc = arg;
break;
#endif
default:
return 0;
}
@ -456,13 +431,6 @@ md_show_usage (stream)
fprintf (stream, _("\
-KPIC generate PIC\n"));
#if 0
fprintf (stream, _("\
-relax create linker relaxable code\n"));
fprintf (stream, _("\
-cpu-desc provide runtime cpu description file\n"));
#endif
}
static void fill_insn PARAMS ((int));
@ -770,19 +738,6 @@ md_begin ()
/* This is a callback from cgen to gas to parse operands. */
cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
#if 0
/* Not supported yet. */
/* If a runtime cpu description file was provided, parse it. */
if (m32r_cpu_desc != NULL)
{
const char *errmsg;
errmsg = cgen_read_cpu_file (gas_cgen_cpu_desc, m32r_cpu_desc);
if (errmsg != NULL)
as_bad ("%s: %s", m32r_cpu_desc, errmsg);
}
#endif
/* Save the current subseg so we can restore it [it's the default one and
we don't want the initial section to be .sbss]. */
seg = now_seg;
@ -795,11 +750,6 @@ md_begin ()
applicable = bfd_applicable_section_flags (stdoutput);
bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
#if 0
/* What does this do? [see perform_an_assembly_pass] */
seg_info (bss_section)->bss = 1;
#endif
subseg_set (seg, subseg);
/* We must construct a fake section similar to bfd_com_section
@ -914,28 +864,9 @@ static int
writes_to_pc (a)
m32r_insn *a;
{
#if 0
/* Once PC operands are working.... */
const CGEN_OPINST *a_operands == CGEN_INSN_OPERANDS (gas_cgen_cpu_desc,
a->insn);
if (a_operands == NULL)
return 0;
while (a_operands->type != CGEN_OPINST_END)
{
if (a_operands->operand != NULL
&& CGEN_OPERAND_INDEX (gas_cgen_cpu_desc,
a_operands->operand) == M32R_OPERAND_PC)
return 1;
a_operands++;
}
#else
if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI)
|| CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI))
return 1;
#endif
return 0;
}
@ -1820,35 +1751,11 @@ md_estimate_size_before_relax (fragP, segment)
|| S_IS_EXTERNAL (fragP->fr_symbol)
|| S_IS_WEAK (fragP->fr_symbol))
{
#if 0
int old_fr_fix = fragP->fr_fix;
#endif
/* The symbol is undefined in this segment.
Change the relaxation subtype to the max allowable and leave
all further handling to md_convert_frag. */
fragP->fr_subtype = 2;
#if 0
/* Can't use this, but leave in for illustration. */
/* Change 16 bit insn to 32 bit insn. */
fragP->fr_opcode[0] |= 0x80;
/* Increase known (fixed) size of fragment. */
fragP->fr_fix += 2;
/* Create a relocation for it. */
fix_new (fragP, old_fr_fix, 4,
fragP->fr_symbol,
fragP->fr_offset, 1 /* pcrel */,
/* FIXME: Can't use a real BFD reloc here.
gas_cgen_md_apply_fix3 can't handle it. */
BFD_RELOC_M32R_26_PCREL);
/* Mark this fragment as finished. */
frag_wane (fragP);
return fragP->fr_fix - old_fr_fix;
#else
{
const CGEN_INSN *insn;
int i;
@ -1871,7 +1778,6 @@ md_estimate_size_before_relax (fragP, segment)
fragP->fr_cgen.insn = insn;
return 2;
}
#endif
}
return md_relax_table[fragP->fr_subtype].rlx_length;
@ -1962,13 +1868,8 @@ md_convert_frag (abfd, sec, fragP)
fragP->fr_cgen.insn,
4 /* Length. */,
/* FIXME: quick hack. */
#if 0
cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
fragP->fr_cgen.opindex),
#else
cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
M32R_OPERAND_DISP24),
#endif
fragP->fr_cgen.opinfo,
fragP->fr_symbol, fragP->fr_offset);
if (fragP->fr_cgen.opinfo)

6
gas/config/tc-m32r.h
View File

@ -57,15 +57,9 @@ long md_pcrel_from_section PARAMS ((struct fix *, segT));
/* For 8 vs 16 vs 32 bit branch selection. */
extern const struct relax_type md_relax_table[];
#define TC_GENERIC_RELAX_TABLE md_relax_table
#if 0
extern void m32r_prepare_relax_scan ();
#define md_prepare_relax_scan(fragP, address, aim, this_state, this_type) \
m32r_prepare_relax_scan (fragP, address, aim, this_state, this_type)
#else
extern long m32r_relax_frag PARAMS ((segT, fragS *, long));
#define md_relax_frag(segment, fragP, stretch) \
m32r_relax_frag (segment, fragP, stretch)
#endif
/* Account for nop if 32 bit insn falls on odd halfword boundary. */
#define TC_CGEN_MAX_RELAX(insn, len) (6)

6
gas/config/tc-m68hc11.c
View File

@ -3281,16 +3281,10 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
case BFD_RELOC_M68HC11_LO8:
case BFD_RELOC_8:
case BFD_RELOC_M68HC11_PAGE:
#if 0
bfd_putb8 ((bfd_vma) value, (unsigned char *) where);
#endif
((bfd_byte *) where)[0] = (bfd_byte) value;
break;
case BFD_RELOC_8_PCREL:
#if 0
bfd_putb8 ((bfd_vma) value, (unsigned char *) where);
#endif
((bfd_byte *) where)[0] = (bfd_byte) value;
if (value < -128 || value > 127)

6
gas/config/tc-m68hc11.h
View File

@ -33,12 +33,6 @@ struct fix;
/* Motorola assembler specs does not require '.' before pseudo-ops. */
#define NO_PSEUDO_DOT 1
#if 0
/* Treat the single quote as a string delimiter.
??? This does not work at all. */
#define SINGLE_QUOTE_STRINGS 1
#endif
#ifndef BFD_ASSEMBLER
#error M68HC11 support requires BFD_ASSEMBLER
#endif

110
gas/config/tc-mips.c
View File

@ -11142,93 +11142,6 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
fixP->fx_addnumber = *valP;
}
#if 0
void
printInsn (unsigned long oc)
{
const struct mips_opcode *p;
int treg, sreg, dreg, shamt;
short imm;
const char *args;
int i;
for (i = 0; i < NUMOPCODES; ++i)
{
p = &mips_opcodes[i];
if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
{
printf ("%08lx %s\t", oc, p->name);
treg = (oc >> 16) & 0x1f;
sreg = (oc >> 21) & 0x1f;
dreg = (oc >> 11) & 0x1f;
shamt = (oc >> 6) & 0x1f;
imm = oc;
for (args = p->args;; ++args)
{
switch (*args)
{
case '\0':
printf ("\n");
break;
case ',':
case '(':
case ')':
printf ("%c", *args);
continue;
case 'r':
assert (treg == sreg);
printf ("$%d,$%d", treg, sreg);
continue;
case 'd':
case 'G':
printf ("$%d", dreg);
continue;
case 't':
case 'E':
printf ("$%d", treg);
continue;
case 'k':
printf ("0x%x", treg);
continue;
case 'b':
case 's':
printf ("$%d", sreg);
continue;
case 'a':
printf ("0x%08lx", oc & 0x1ffffff);
continue;
case 'i':
case 'j':
case 'o':
case 'u':
printf ("%d", imm);
continue;
case '<':
case '>':
printf ("$%d", shamt);
continue;
default:
internalError ();
}
break;
}
return;
}
}
printf (_("%08lx UNDEFINED\n"), oc);
}
#endif
static symbolS *
get_symbol (void)
{
@ -13811,29 +13724,6 @@ s_mips_mask (int reg_type)
s_ignore (reg_type);
}
/* The .loc directive. */
#if 0
static void
s_loc (int x)
{
symbolS *symbolP;
int lineno;
int addroff;
assert (now_seg == text_section);
lineno = get_number ();
addroff = frag_now_fix ();
symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
S_SET_TYPE (symbolP, N_SLINE);
S_SET_OTHER (symbolP, 0);
S_SET_DESC (symbolP, lineno);
symbolP->sy_segment = now_seg;
}
#endif
/* A table describing all the processors gas knows about. Names are
matched in the order listed.

8
gas/config/tc-mn10200.c
View File

@ -1288,14 +1288,6 @@ md_pcrel_from (fixp)
fixS *fixp;
{
return fixp->fx_frag->fr_address;
#if 0
if (fixp->fx_addsy != (symbolS *) NULL && !S_IS_DEFINED (fixp->fx_addsy))
{
/* The symbol is undefined. Let the linker figure it out. */
return 0;
}
return fixp->fx_frag->fr_address + fixp->fx_where;
#endif
}
void

16
gas/config/tc-msp430.c
View File

@ -1295,22 +1295,6 @@ msp430_srcoperand (struct msp430_operand_s * op,
/* Symbolic mode 'mov a, b' == 'mov x(pc), y(pc)'. */
do
{
#if 0 /* Allow expression in operand like 'a+123*(1|2)'. */
char *t = l;
__tl = l;
while (*t)
{
/* alpha/number underline dot for labels. */
if (! ISALNUM (*t) && *t != '_' && *t != '.')
{
as_bad (_("unknown operand %s"), l);
return 1;
}
t++;
}
#endif
op->mode = OP_EXP;
op->reg = 0; /* PC relative... be careful. */
op->am = 1;

3
gas/config/tc-ns32k.c
View File

@ -2098,9 +2098,6 @@ md_estimate_size_before_relax (fragP, segment)
frag_opcode_frag (fragP),
frag_opcode_offset (fragP));
fragP->fr_fix += 4;
#if 0
fragP->fr_opcode[1] = 0xff;
#endif
frag_wane (fragP);
return 4;
}

8
gas/config/tc-openrisc.c
View File

@ -145,14 +145,6 @@ md_assemble (str)
gas_cgen_finish_insn (insn.insn, insn.buffer,
CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
#if 0 /* Currently disabled */
/* Warn about invalid insns in delay slots. */
if (last_insn_had_delay_slot
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_NOT_IN_DELAY_SLOT))
as_warn (_("Instruction %s not allowed in a delay slot."),
CGEN_INSN_NAME (insn.insn));
#endif
last_insn_had_delay_slot
= CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT);
}

33
gas/config/tc-or32.c
View File

@ -581,10 +581,6 @@ machine_ip (str)
if (*s == '(')
{
operand->X_op = O_constant;
#if 0
operand->X_add_number = 0; /* ??? if enabled load/store offsets
are zero. */
#endif
}
else if (*s == ')')
s += 1;
@ -796,10 +792,6 @@ machine_ip (str)
if (*s == '(')
{
operand->X_op = O_constant;
#if 0
operand->X_add_number = 0; /* ??? if enabled load/store offsets
are zero. */
#endif
}
else if (*s == ')')
s += 1;
@ -1002,20 +994,7 @@ md_apply_fix3 (fixP, val, seg)
case BFD_RELOC_32_GOT_PCREL: /* 0000XXXX pattern in a word. */
if (!fixP->fx_done)
{
/* The linker tries to support both AMD and old GNU style
R_IREL relocs. That means that if the addend is exactly
the negative of the address within the section, the
linker will not handle it correctly. */
#if 0
if (fixP->fx_pcrel
&& t_val != 0
&& t_val == - (fixP->fx_frag->fr_address + fixP->fx_where))
as_bad_where
(fixP->fx_file, fixP->fx_line,
_("the linker will not handle this relocation correctly (1)"));
#endif
}
;
else if (fixP->fx_pcrel)
{
long v = t_val >> 28;
@ -1124,23 +1103,13 @@ md_apply_fix3 (fixP, valP, seg)
R_IREL relocs. That means that if the addend is exactly
the negative of the address within the section, the
linker will not handle it correctly. */
#if 0
if (fixP->fx_pcrel
&& val != 0
&& val == - (fixP->fx_frag->fr_address + fixP->fx_where))
as_bad_where
(fixP->fx_file, fixP->fx_line,
_("the linker will not handle this relocation correctly (1)"));
#endif
}
else if (fixP->fx_pcrel)
{
long v = val >> 28;
#if 1
if (v != 0 && v != -1)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("call/jmp target out of range (2)"));
#endif
}
else
/* This case was supposed to be handled in machine_ip. */

48
gas/config/tc-pdp11.c
View File

@ -366,30 +366,6 @@ parse_expression (char *str, struct pdp11_code *operand)
operand->reloc.pc_rel = 0;
#if 0
/* FIXME: what follows is broken badly. You can't deal with differences
in radix conventions this way, because of symbolic constants, constant
expressions made up of pieces of differing radix, etc. The only
choices are to change ../expr.c to know about pdp11 conventions, or
to accept the fact that gas will use consistent conventions that differ
from those of traditional pdp11 assemblers. For now, I've
chosen the latter. paul koning, 12/23/2001
*/
if (operand->reloc.exp.X_op == O_constant)
{
if (*str == '.')
str++;
else
{
/* FIXME: buffer overflow! */
char buf[100];
char *end;
sprintf (buf, "%ld", operand->reloc.exp.X_add_number);
operand->reloc.exp.X_add_number = strtol (buf, &end, 8);
}
}
#endif
return str;
}
@ -641,31 +617,7 @@ md_assemble (instruction_string)
*p = c;
if (op == 0)
{
#if 0
op1.error = NULL;
op1.additional = FALSE;
op1.reloc.type = BFD_RELOC_NONE;
op1.code = 0;
op1.word = 0;
str = parse_expression (str, &op1);
if (op1.error)
{
as_bad (op1.error);
return;
}
{
char *to = frag_more (2);
md_number_to_chars (to, op1.code, 2);
if (insn.reloc.type != BFD_RELOC_NONE)
fix_new_exp (frag_now, to - frag_now->fr_literal, 2,
&insn.reloc.exp, insn.reloc.pc_rel, insn.reloc.type);
}
#else
as_bad (_("Unknown instruction '%s'"), str);
#endif
return;
}

3
gas/config/tc-pj.c
View File

@ -256,9 +256,6 @@ md_assemble (str)
unsigned char *op_start;
unsigned char *op_end;
#if 0
pj_operan_info operand[3];
#endif
pj_opc_info_t *opcode;
char *output;
int idx = 0;

7
gas/config/tc-sparc.h
View File

@ -39,13 +39,6 @@ extern const char *sparc_target_format PARAMS ((void));
#define RELOC_EXPANSION_POSSIBLE
#define MAX_RELOC_EXPANSION 2
#if 0
#ifdef TE_SPARCAOUT
/* Bi-endian support may eventually be unconditional, but until things are
working well it's only provided for targets that need it. */
#define SPARC_BIENDIAN
#endif
#endif
/* Make it unconditional and check if -EL is valid after option parsing */
#define SPARC_BIENDIAN

68
gas/config/tc-tic54x.c
View File

@ -153,9 +153,6 @@ struct option md_longopts[] =
{ "mfar-mode", no_argument, NULL, OPTION_ADDRESS_MODE },
{ "mf", no_argument, NULL, OPTION_ADDRESS_MODE },
{ "mcpu", required_argument, NULL, OPTION_CPU_VERSION },
#if 0
{ "mcoff-version", required_argument, NULL, OPTION_COFF_VERSION },
#endif
{ "merrors-to-file", required_argument, NULL, OPTION_STDERR_TO_FILE },
{ "me", required_argument, NULL, OPTION_STDERR_TO_FILE },
{ NULL, no_argument, NULL, 0},
@ -349,9 +346,6 @@ md_show_usage (stream)
fprintf (stream, _("C54x-specific command line options:\n"));
fprintf (stream, _("-mfar-mode | -mf Use extended addressing\n"));
fprintf (stream, _("-mcpu=<CPU version> Specify the CPU version\n"));
#if 0
fprintf (stream, _("-mcoff-version={0|1|2} Select COFF version\n"));
#endif
fprintf (stream, _("-merrors-to-file <filename>\n"));
fprintf (stream, _("-me <filename> Redirect errors to a file\n"));
}
@ -2583,9 +2577,6 @@ const pseudo_typeS md_pseudo_table[] =
{ "emsg" , tic54x_message , 'e' },
{ "mmsg" , tic54x_message , 'm' },
{ "wmsg" , tic54x_message , 'w' },
#if 0
{ "end" , s_end , 0 },
#endif
{ "far_mode" , tic54x_address_mode , far_mode },
{ "fclist" , tic54x_fclist , 1 },
{ "fcnolist" , tic54x_fclist , 0 },
@ -2611,10 +2602,6 @@ const pseudo_typeS md_pseudo_table[] =
address. */
{ "length" , s_ignore , 0 },
{ "width" , s_ignore , 0 },
#if 0
{ "list" , listing_list , 1 },
{ "nolist" , listing_list , 0 },
#endif
{ "long" , tic54x_cons , 'l' },
{ "ulong" , tic54x_cons , 'L' },
{ "xlong" , tic54x_cons , 'x' },
@ -2628,9 +2615,6 @@ const pseudo_typeS md_pseudo_table[] =
{ "newblock" , tic54x_clear_local_labels, 0 },
{ "option" , s_ignore , 0 },
{ "p2align" , tic54x_p2align , 0 },
#if 0
{ "page" , listing_eject , 0 },
#endif
{ "sblock" , tic54x_sblock , 0 },
{ "sect" , tic54x_sect , '*' },
{ "set" , tic54x_set , 0 },
@ -2646,9 +2630,6 @@ const pseudo_typeS md_pseudo_table[] =
{ "endstruct", tic54x_endstruct , 0 },
{ "tab" , s_ignore , 0 },
{ "text" , tic54x_sect , 't' },
#if 0
{ "title" , listing_title , 0 },
#endif
{ "union" , tic54x_struct , 1 },
{ "endunion" , tic54x_endstruct , 1 },
{ "usect" , tic54x_usect , 0 },
@ -2657,21 +2638,6 @@ const pseudo_typeS md_pseudo_table[] =
{0 , 0 , 0 }
};
#if 0
/* For debugging, strings for each operand type. */
static const char *optypes[] =
{
"none", "Xmem", "Ymem", "pmad", "dmad", "Smem", "Lmem", "MMR", "PA",
"Sind", "xpmad", "xpmad+", "MMRX", "MMRY",
"SRC1", "SRC", "RND", "DST",
"ARX",
"SHIFT", "SHFT",
"B", "A", "lk", "TS", "k8", "16", "BITC", "CC", "CC2", "CC3", "123", "031",
"k5", "k8u", "ASM", "T", "DP", "ARP", "k3", "lku", "N", "SBIT", "12",
"k9", "TRN",
};
#endif
int
md_parse_option (c, arg)
int c;
@ -5080,24 +5046,6 @@ subsym_substitute (line, forced)
break;
}
++tail;
#if 0
/* Try to replace required whitespace
eliminated by the preprocessor; technically, a forced
substitution could come anywhere, even mid-symbol,
e.g. if x is "0", 'sym:x:end' should result in 'sym0end',
but 'sym:x: end' should result in 'sym0 end'.
FIXME -- this should really be fixed in the preprocessor,
but would require several new states;
KEEP_WHITE_AROUND_COLON does part of the job, but isn't
complete. */
if ((is_part_of_name (tail[1])
&& tail[1] != '.'
&& tail[1] != '$')
|| tail[1] == '\0' || tail[1] == ',' || tail[1] == '"')
++tail;
else
*tail = ' ';
#endif
}
else
/* Restore the character after the symbol end. */
@ -5402,11 +5350,6 @@ void
tic54x_define_label (sym)
symbolS *sym;
{
#if 0
static int local_label_count = 0;
const char *name = S_GET_NAME (sym);
#endif
/* Just in case we need this later; note that this is not necessarily the
same thing as line_label...
When aligning or assigning labels to fields, sometimes the label is
@ -5456,17 +5399,6 @@ tic54x_parse_name (name, exp)
char *name ATTRIBUTE_UNUSED;
expressionS *exp ATTRIBUTE_UNUSED;
{
#if 0
symbol *sym = (symbol *) hash_find (mmreg_hash, name);
/* If it's a MMREG, replace it with its constant value. */
if (sym)
{
exp->X_op = O_constant;
exp->X_add_number = sym->value;
return 1;
}
#endif
return 0;
}

90
gas/config/tc-tic80.c
View File

@ -397,11 +397,7 @@ find_opcode (opcode, myops)
is given, we never use the short forms.
FIXME: Should be able to choose "best-fit". */
}
else if ((bits == 32)
#if 0
&& (flags & TIC80_OPERAND_BASEREL)
#endif
)
else if ((bits == 32))
{
/* The default is to prefer the long form of base
relative relocations. This is the only form that
@ -470,90 +466,6 @@ find_opcode (opcode, myops)
return (match ? opc : NULL);
#if 0
/* Now search the opcode table table for one with operands that
matches what we've got. */
while (!match)
{
match = 1;
for (i = 0; opcode->operands[i]; i++)
{
int flags = tic80_operands[opcode->operands[i]].flags;
int X_op = myops[i].X_op;
int num = myops[i].X_add_number;
if (X_op == 0)
{
match = 0;
break;
}
if (flags
& (TIC80_OPERAND_GPR | TIC80_OPERAND_FPA | TIC80_OPERAND_CR))
{
if ((X_op != O_register) ||
((flags & TIC80_OPERAND_GPR) != (num & TIC80_OPERAND_GPR)) ||
((flags & TIC80_OPERAND_FPA) != (num & TIC80_OPERAND_FPA)) ||
((flags & TIC80_OPERAND_CR) != (num & TIC80_OPERAND_CR)))
{
match = 0;
break;
}
}
if (((flags & TIC80_OPERAND_MINUS) && ((X_op != O_absent) || (num != TIC80_OPERAND_MINUS))) ||
((flags & TIC80_OPERAND_PLUS) && ((X_op != O_absent) || (num != TIC80_OPERAND_PLUS))) ||
((flags & TIC80_OPERAND_ATMINUS) && ((X_op != O_absent) || (num != TIC80_OPERAND_ATMINUS))) ||
((flags & TIC80_OPERAND_ATPAR) && ((X_op != O_absent) || (num != TIC80_OPERAND_ATPAR))) ||
((flags & TIC80_OPERAND_ATSIGN) && ((X_op != O_absent) || (num != TIC80_OPERAND_ATSIGN))))
{
match = 0;
break;
}
}
/* We're only done if the operands matched so far AND there
are no more to check. */
if (match && myops[i].X_op == 0)
break;
else
match = 0;
next_opcode = opcode + 1;
if (next_opcode->opcode == 0)
break;
if (strcmp (next_opcode->name, opcode->name))
break;
opcode = next_opcode;
}
if (!match)
{
as_bad (_("bad opcode or operands"));
return (0);
}
/* Check that all registers that are required to be even are.
Also, if any operands were marked as registers, but were really
symbols, fix that here. */
for (i = 0; opcode->operands[i]; i++)
{
if ((tic80_operands[opcode->operands[i]].flags & TIC80_OPERAND_EVEN)
&& (myops[i].X_add_number & 1))
as_fatal (_("Register number must be EVEN"));
if (myops[i].X_op == O_register)
{
if (!(tic80_operands[opcode->operands[i]].flags & TIC80_OPERAND_REG))
{
myops[i].X_op = O_symbol;
myops[i].X_add_symbol =
symbol_find_or_make ((char *) myops[i].X_op_symbol);
myops[i].X_add_number = 0;
myops[i].X_op_symbol = NULL;
}
}
}
#endif
}
/* build_insn takes a pointer to the opcode entry in the opcode table

11
gas/config/tc-v850.c
View File

@ -2025,13 +2025,6 @@ md_assemble (str)
if (errmsg)
goto error;
#if 0
fprintf (stderr,
" insn: %x, operand %d, op: %d, add_number: %d\n",
insn, opindex_ptr - opcode->operands,
ex.X_op, ex.X_add_number);
#endif
switch (ex.X_op)
{
case O_illegal:
@ -2411,10 +2404,6 @@ md_apply_fix3 (fixP, valueP, seg)
fixP->fx_r_type = BFD_RELOC_V850_9_PCREL;
else
{
#if 0
fprintf (stderr, "bits: %d, insn: %x\n", operand->bits, insn);
#endif
as_bad_where (fixP->fx_file, fixP->fx_line,
_("unresolved expression that must be resolved"));
fixP->fx_done = 1;

4
gas/config/tc-w65.c
View File

@ -64,10 +64,6 @@ const pseudo_typeS md_pseudo_table[] = {
{0, 0, 0}
};
#if 0
int md_reloc_size;
#endif
const char EXP_CHARS[] = "eE";
/* Chars that mean this number is a floating point constant. */

51
gas/config/tc-xtensa.c
View File

@ -5590,17 +5590,7 @@ xtensa_fix_adjustable (fixS *fixP)
&& (S_IS_EXTERNAL (fixP->fx_addsy) || S_IS_WEAK (fixP->fx_addsy)))
return 0;
#if 0
/* We may someday want to enable this code to preserve relocations for
non-PC-relative fixes, possibly under control of a PIC flag. */
return (fixP->fx_pcrel
|| (fixP->fx_subsy != NULL
&& (S_GET_SEGMENT (fixP->fx_subsy)
== S_GET_SEGMENT (fixP->fx_addsy)))
|| S_IS_LOCAL (fixP->fx_addsy));
#else
return 1;
#endif
}
@ -9573,34 +9563,6 @@ convert_frag_immed (segT segP,
xg_emit_insn_to_buf (tinsn, single_format, immed_instr,
fragP,
immed_instr - fragP->fr_literal, TRUE);
#if 0
/* Code to recognize branch-around expansion
so the fragment is properly marked as ending in a
jump. */
if ((((i == istack.ninsn - 2)
&& (istack.insn[istack.ninsn-1].insn_type
== ITYPE_LABEL))
|| i == istack.ninsn -1)
&& xtensa_opcode_is_jump (xtensa_default_isa,
tinsn->opcode) == 1
&& fragP->fr_next != NULL
&& ! fragP->fr_next->tc_frag_data.is_unreachable)
{
/* Create a new unreachable frag of zero size. */
size_t frag_size = sizeof (fragS);
fragS *new_fragP = (fragS *) xmalloc (frag_size);
memset (new_fragP, 0, frag_size);
new_fragP->fr_address = fragP->fr_next->fr_address;
new_fragP->fr_next = fragP->fr_next;
new_fragP->fr_fix = 0;
new_fragP->fr_var = 0;
new_fragP->fr_type = rs_fill;
new_fragP->tc_frag_data.is_unreachable = TRUE;
/* The rest are zeros.... */
/* Link it in to the chain. */
fragP->fr_next = new_fragP;
}
#endif
}
immed_instr += size;
total_size += size;
@ -10676,18 +10638,7 @@ retrieve_segment_info (segT seg)
seginfo->bfd_section = seg;
seginfo->sym = 0;
/* We will not be dealing with these, only our special ones. */
#if 0
if (seg == bfd_abs_section_ptr)
abs_seg_info = seginfo;
else if (seg == bfd_und_section_ptr)
und_seg_info = seginfo;
else
#endif
bfd_set_section_userdata (stdoutput, seg, (void *) seginfo);
#if 0
seg_fix_rootP = &segment_info[seg].fix_root;
seg_fix_tailP = &segment_info[seg].fix_tail;
#endif
bfd_set_section_userdata (stdoutput, seg, (void *) seginfo);
frchainP = (frchainS *) xmalloc (sizeof (frchainS));
frchainP->frch_root = NULL;

12
gas/config/tc-z8k.c
View File

@ -655,9 +655,6 @@ get_operand (char **ptr, struct z8k_op *mode, unsigned int dst ATTRIBUTE_UNUSED)
src++;
regaddr (mode->mode, "ra(rb) ra");
#if 0
regword (mode->mode, "ra(rb) rb");
#endif
mode->mode = CLASS_BX;
mode->reg = regn;
mode->x_reg = nr;
@ -1514,15 +1511,6 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED)
fixP->fx_no_overflow = 1;
break;
#if 0
case R_DA | R_SEG:
*buf++ = (val >> 16);
*buf++ = 0x00;
*buf++ = (val >> 8);
*buf++ = val;
break;
#endif
case 0:
md_number_to_chars (buf, val, fixP->fx_size);
break;

19
gas/config/xtensa-relax.c
View File

@ -299,15 +299,6 @@ static string_pattern_pair widen_spec_list[] =
{"l32i %at,%as,%imm | %at!=%as ? IsaUseConst16",
"const16 %at,HI16U(%imm); const16 %at,LOW16U(%imm); add %at,%at,%as; l32i %at,%at,0"},
#if 0 /* Xtensa Synchronization Option not yet available */
{"l32ai %at,%as,%imm ? IsaUseL32R",
"LITERAL0 %imm; l32r %at,%LITERAL0; add.n %at,%at,%as; l32ai %at,%at,0"},
#endif
#if 0 /* Xtensa Speculation Option not yet available */
{"l32is %at,%as,%imm ? IsaUseL32R",
"LITERAL0 %imm; l32r %at,%LITERAL0; add.n %at,%at,%as; l32is %at,%at,0"},
#endif
/* This is only PART of the loop instruction. In addition,
hardcoded into its use is a modification of the final operand in
the instruction in bytes 9 and 12. */
@ -1545,10 +1536,6 @@ build_transition (insn_pattern *initial_insn,
if (opcode == XTENSA_UNDEFINED)
{
/* It is OK to not be able to translate some of these opcodes. */
#if 0
as_warn (_("invalid opcode '%s' in transition rule '%s'"),
initial_insn->t.opcode_name, from_string);
#endif
return NULL;
}
@ -1559,12 +1546,6 @@ build_transition (insn_pattern *initial_insn,
/* This is also OK because there are opcodes that
have different numbers of operands on different
architecture variations. */
#if 0
as_fatal (_("opcode %s mismatched operand count %d != expected %d"),
xtensa_opcode_name (isa, opcode),
xtensa_num_operands (isa, opcode),
insn_templ_operand_count (&initial_insn->t));
#endif
return NULL;
}