mirror of
https://github.com/darlinghq/darling-gdb.git
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1999-05-28 Torbjorn Granlund <tege@matematik.su.se>
* config/tc-m68k.c (m68k_ip): Check for disallowed index register width for Coldfire. (arch_coldfire_p): New #define. (m68k_ip, m68k_init_after_args): Use arch_coldfire_p. 1999-05-28 Linus Nordberg <linus.nordberg@canit.se> * config/tc-m68k.c (install_operand): Add places `n', `o'. * config/tc-m68k.c (m68k_ip): Add formats `E', `G', `H'. (install_operand): Add place `N'. (init_table): Add registers ACC, MACSR, MASK. * config/m68k-parse.h (m68k_register): Add ACC, MACSR, MASK. * config/tc-m68k.c: Change mcf5200 --> mcf. (archs): Add mcf5206e, mcf5307. (m68k_ip): Add format `u'. (install_operand): Add place `m', `M', `h'. (init_table): Add upper/lower registers. * config/m68k-parse.h (m68k_register): Add upper/lower registers.
This commit is contained in:
Ian Lance Taylor
parent
461d5ddde0
commit
6da466c730
@ -1,3 +1,28 @@
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1999-05-28 Torbjorn Granlund <tege@matematik.su.se>
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* config/tc-m68k.c (m68k_ip): Check for disallowed index register
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width for Coldfire.
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(arch_coldfire_p): New #define.
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(m68k_ip, m68k_init_after_args): Use arch_coldfire_p.
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1999-05-28 Linus Nordberg <linus.nordberg@canit.se>
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* config/tc-m68k.c (install_operand): Add places `n', `o'.
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* config/tc-m68k.c (m68k_ip): Add formats `E', `G', `H'.
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(install_operand): Add place `N'.
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(init_table): Add registers ACC, MACSR, MASK.
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* config/m68k-parse.h (m68k_register): Add ACC, MACSR, MASK.
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* config/tc-m68k.c: Change mcf5200 --> mcf.
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(archs): Add mcf5206e, mcf5307.
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(m68k_ip): Add format `u'.
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(install_operand): Add place `m', `M', `h'.
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(init_table): Add upper/lower registers.
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* config/m68k-parse.h (m68k_register): Add upper/lower registers.
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1999-05-28 Martin Dorey <mdorey@madge.com>
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* config/tc-i960.c: Several minor changes to add ELF and
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@ -1,5 +1,6 @@
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/* m68k-parse.h -- header file for m68k assembler
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Copyright (C) 1987, 91, 92, 93, 94, 1995 Free Software Foundation, Inc.
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Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 1999
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Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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@ -83,6 +84,9 @@ enum m68k_register
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ZPC, /* Hack for Program space, but 0 addressing */
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SR, /* Status Reg */
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CCR, /* Condition code Reg */
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ACC, /* Accumulator Reg */
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MACSR, /* MAC Status Reg */
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MASK, /* Modulus Reg */
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/* These have to be grouped together for the movec instruction to work. */
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USP, /* User Stack Pointer */
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@ -165,6 +169,44 @@ enum m68k_register
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ZADDR5,
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ZADDR6,
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ZADDR7,
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/* Upper and lower half of data and address registers. Order *must*
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be DATAxL, ADDRxL, DATAxU, ADDRxU. */
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DATA0L, /* lower half of data registers */
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DATA1L,
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DATA2L,
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DATA3L,
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DATA4L,
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DATA5L,
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DATA6L,
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DATA7L,
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ADDR0L, /* lower half of address registers */
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ADDR1L,
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ADDR2L,
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ADDR3L,
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ADDR4L,
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ADDR5L,
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ADDR6L,
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ADDR7L,
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DATA0U, /* upper half of data registers */
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DATA1U,
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DATA2U,
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DATA3U,
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DATA4U,
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DATA5U,
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DATA6U,
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DATA7U,
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ADDR0U, /* upper half of address registers */
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ADDR1U,
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ADDR2U,
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ADDR3U,
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ADDR4U,
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ADDR5U,
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ADDR6U,
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ADDR7U,
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};
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/* Size information. */
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@ -1,5 +1,5 @@
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/* tc-m68k.c -- Assemble for the m68k family
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Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 97, 1998
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Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 97, 98, 1999
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Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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@ -193,7 +193,7 @@ static const enum m68k_register m68060_control_regs[] = {
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USP, VBR, URP, SRP, PCR,
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0
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};
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static const enum m68k_register mcf5200_control_regs[] = {
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static const enum m68k_register mcf_control_regs[] = {
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CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
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RAMBAR0, RAMBAR1, MBAR,
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0
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@ -251,9 +251,10 @@ struct m68k_it
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reloc[5]; /* Five is enough??? */
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};
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#define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
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#define cpu_of_arch(x) ((x) & (m68000up|mcf))
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#define float_of_arch(x) ((x) & mfloat)
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#define mmu_of_arch(x) ((x) & mmmu)
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#define arch_coldfire_p(x) (((x) & mcf) != 0)
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/* Macros for determining if cpu supports a specific addressing mode */
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#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
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@ -395,6 +396,8 @@ static const struct m68k_cpu archs[] = {
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{ m68881, "68881", 0 },
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{ m68851, "68851", 0 },
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{ mcf5200, "5200", 0 },
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{ mcf5206e, "5206e", 0 },
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{ mcf5307, "5307", 0},
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/* Aliases (effectively, so far as gas is concerned) for the above
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cpus. */
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{ m68020, "68k", 1 },
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@ -422,6 +425,9 @@ static const struct m68k_cpu archs[] = {
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{ cpu32, "68349", 1 },
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{ cpu32, "68360", 1 },
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{ m68881, "68882", 1 },
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{ mcf5200, "5202", 1 },
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{ mcf5200, "5204", 1 },
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{ mcf5200, "5206", 1 },
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};
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static const int n_archs = sizeof (archs) / sizeof (archs[0]);
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@ -1475,11 +1481,26 @@ m68k_ip (instring)
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losing++;
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break;
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case 'E':
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if (opP->reg != ACC)
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losing++;
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break;
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case 'F':
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if (opP->mode != FPREG)
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losing++;
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break;
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case 'G':
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if (opP->reg != MACSR)
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losing++;
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break;
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case 'H':
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if (opP->reg != MASK)
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losing++;
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break;
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case 'I':
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if (opP->mode != CONTROL
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|| opP->reg < COP0
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@ -1741,6 +1762,19 @@ m68k_ip (instring)
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++losing;
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break;
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case 'u':
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if (opP->reg < DATA0L || opP->reg > ADDR7U)
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losing++;
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/* FIXME: kludge instead of fixing parser:
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upper/lower registers are *not* CONTROL
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registers, but ordinary ones. */
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if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
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|| (opP->reg >= DATA0U && opP->reg <= DATA7U))
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opP->mode = DREG;
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else
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opP->mode = AREG;
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break;
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default:
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abort ();
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} /* switch on type of operand */
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@ -1998,11 +2032,11 @@ m68k_ip (instring)
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&& ((opP->disp.size == SIZE_UNSPEC
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&& flag_short_refs == 0
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&& cpu_of_arch (current_architecture) >= m68020
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&& cpu_of_arch (current_architecture) != mcf5200)
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&& ! arch_coldfire_p (current_architecture))
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|| opP->disp.size == SIZE_LONG)))
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{
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if (cpu_of_arch (current_architecture) < m68020
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|| cpu_of_arch (current_architecture) == mcf5200)
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|| arch_coldfire_p (current_architecture))
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opP->error =
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_("displacement too large for this architecture; needs 68020 or higher");
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if (opP->reg == PC)
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@ -2111,12 +2145,16 @@ m68k_ip (instring)
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if ((opP->index.scale != 1
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&& cpu_of_arch (current_architecture) < m68020)
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|| (opP->index.scale == 8
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&& current_architecture == mcf5200))
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&& arch_coldfire_p (current_architecture)))
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{
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opP->error =
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_("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
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}
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if (arch_coldfire_p (current_architecture)
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&& opP->index.size == SIZE_WORD)
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opP->error = _("invalid index size for coldfire");
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switch (opP->index.scale)
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{
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case 1:
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@ -2148,7 +2186,7 @@ m68k_ip (instring)
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{
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if (siz1 == SIZE_BYTE
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|| cpu_of_arch (current_architecture) < m68020
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|| cpu_of_arch (current_architecture) == mcf5200
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|| arch_coldfire_p (current_architecture)
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|| (siz1 == SIZE_UNSPEC
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&& ! isvar (&opP->disp)
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&& issbyte (baseo)))
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@ -2215,7 +2253,7 @@ m68k_ip (instring)
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/* It isn't simple. */
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if (cpu_of_arch (current_architecture) < m68020
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|| cpu_of_arch (current_architecture) == mcf5200)
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|| arch_coldfire_p (current_architecture))
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opP->error =
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_("invalid operand mode for this architecture; needs 68020 or higher");
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@ -2574,10 +2612,17 @@ m68k_ip (instring)
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install_operand (s[1], opP->reg - DATA);
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break;
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case 'E': /* Ignore it */
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break;
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case 'F':
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install_operand (s[1], opP->reg - FP0);
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break;
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case 'G': /* Ignore it */
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case 'H':
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break;
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case 'I':
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tmpreg = opP->reg - COP0;
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install_operand (s[1], tmpreg);
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@ -2905,6 +2950,11 @@ m68k_ip (instring)
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addword (tmpreg >> 16);
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addword (tmpreg & 0xFFFF);
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break;
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case 'u':
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install_operand (s[1], opP->reg - DATA0L);
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opP->reg -= (DATA0L);
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opP->reg &= 0x0F; /* remove upper/lower bit */
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break;
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default:
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abort ();
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}
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@ -3044,6 +3094,30 @@ install_operand (mode, val)
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the_ins.opcode[1] = (val >> 16);
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the_ins.opcode[2] = val & 0xffff;
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break;
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case 'm':
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the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
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the_ins.opcode[0] |= ((val & 0x7) << 9);
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the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
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break;
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case 'n':
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the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
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the_ins.opcode[0] |= ((val & 0x7) << 9);
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break;
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case 'o':
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the_ins.opcode[1] |= val << 12;
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the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
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break;
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case 'M':
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the_ins.opcode[0] |= (val & 0xF);
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the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
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break;
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case 'N':
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the_ins.opcode[1] |= (val & 0xF);
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the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
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break;
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case 'h':
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the_ins.opcode[1] |= ((val != 1) << 10);
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break;
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case 'c':
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default:
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as_fatal (_("failed sanity check."));
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@ -3245,6 +3319,10 @@ static const struct init_entry init_table[] =
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{ "ccr", CCR },
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{ "cc", CCR },
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{ "acc", ACC },
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{ "macsr", MACSR },
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{ "mask", MASK },
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/* control registers */
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{ "sfc", SFC }, /* Source Function Code */
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{ "sfcr", SFC },
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@ -3349,6 +3427,43 @@ static const struct init_entry init_table[] =
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{ "za6", ZADDR6 },
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{ "za7", ZADDR7 },
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/* Upper and lower data and address registers, used by macw and msacw. */
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{ "d0l", DATA0L },
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{ "d1l", DATA1L },
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{ "d2l", DATA2L },
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{ "d3l", DATA3L },
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{ "d4l", DATA4L },
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{ "d5l", DATA5L },
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{ "d6l", DATA6L },
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{ "d7l", DATA7L },
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{ "a0l", ADDR0L },
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{ "a1l", ADDR1L },
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{ "a2l", ADDR2L },
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{ "a3l", ADDR3L },
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{ "a4l", ADDR4L },
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{ "a5l", ADDR5L },
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{ "a6l", ADDR6L },
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{ "a7l", ADDR7L },
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{ "d0u", DATA0U },
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{ "d1u", DATA1U },
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{ "d2u", DATA2U },
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{ "d3u", DATA3U },
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{ "d4u", DATA4U },
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{ "d5u", DATA5U },
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{ "d6u", DATA6U },
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{ "d7u", DATA7U },
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{ "a0u", ADDR0U },
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{ "a1u", ADDR1U },
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{ "a2u", ADDR2U },
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{ "a3u", ADDR3U },
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{ "a4u", ADDR4U },
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{ "a5u", ADDR5U },
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{ "a6u", ADDR6U },
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{ "a7u", ADDR7U },
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{ 0, 0 }
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};
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@ -3783,7 +3898,9 @@ select_control_regs ()
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control_regs = cpu32_control_regs;
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break;
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case mcf5200:
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control_regs = mcf5200_control_regs;
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case mcf5206e:
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case mcf5307:
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control_regs = mcf_control_regs;
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break;
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default:
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abort ();
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@ -3857,7 +3974,7 @@ m68k_init_after_args ()
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select_control_regs ();
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if (cpu_of_arch (current_architecture) < m68020
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|| cpu_of_arch (current_architecture) == mcf5200)
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|| arch_coldfire_p (current_architecture))
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md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
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}
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