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gdbarch software_single_step frame_info to regcache: mips
gdb: 2016-11-22 Yao Qi <yao.qi@linaro.org> * mips-tdep.c (mips32_bc1_pc): Replace parameter frame with regcache. Call regcache_raw_get_unsigned instead of get_frame_register_unsigned. (mips32_next_pc): Likewise. (micromips_bc1_pc): Likewise. (micromips_next_pc): Likewise. (extended_mips16_next_pc): Likewise. (mips16_next_pc): Likewise. (mips_next_pc): Likewise. (mips_software_single_step): Call get_regcache_arch instead of get_frame_arch.
This commit is contained in:
Yao Qi
parent
5b6e2eee08
commit
7113a196ba
@ -1,3 +1,17 @@
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2016-11-22 Yao Qi <yao.qi@linaro.org>
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* mips-tdep.c (mips32_bc1_pc): Replace parameter frame with
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regcache. Call regcache_raw_get_unsigned instead of
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get_frame_register_unsigned.
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(mips32_next_pc): Likewise.
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(micromips_bc1_pc): Likewise.
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(micromips_next_pc): Likewise.
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(extended_mips16_next_pc): Likewise.
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(mips16_next_pc): Likewise.
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(mips_next_pc): Likewise.
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(mips_software_single_step): Call get_regcache_arch instead
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of get_frame_arch.
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2016-11-22 Yao Qi <yao.qi@linaro.org>
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* cris-tdep.c (find_step_target): Replace parameter frame
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140
gdb/mips-tdep.c
140
gdb/mips-tdep.c
@ -1544,7 +1544,7 @@ mips32_relative_offset (ULONGEST inst)
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number of the floating condition bits tested by the branch. */
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static CORE_ADDR
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mips32_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame,
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mips32_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache,
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ULONGEST inst, CORE_ADDR pc, int count)
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{
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int fcsr = mips_regnum (gdbarch)->fp_control_status;
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@ -1558,7 +1558,7 @@ mips32_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame,
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/* No way to handle; it'll most likely trap anyway. */
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return pc;
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fcs = get_frame_register_unsigned (frame, fcsr);
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fcs = regcache_raw_get_unsigned (regcache, fcsr);
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cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01);
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if (((cond >> cnum) & mask) != mask * !tf)
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@ -1602,9 +1602,9 @@ is_octeon_bbit_op (int op, struct gdbarch *gdbarch)
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branch prediction. */
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static CORE_ADDR
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mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
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mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
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{
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struct gdbarch *gdbarch = get_frame_arch (frame);
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struct gdbarch *gdbarch = get_regcache_arch (regcache);
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unsigned long inst;
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int op;
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inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
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@ -1631,15 +1631,15 @@ mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
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}
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else if (op == 17 && itype_rs (inst) == 8)
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/* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
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pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 1);
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pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1);
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else if (op == 17 && itype_rs (inst) == 9
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&& (itype_rt (inst) & 2) == 0)
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/* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
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pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 2);
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pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2);
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else if (op == 17 && itype_rs (inst) == 10
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&& (itype_rt (inst) & 2) == 0)
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/* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
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pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 4);
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pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4);
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else if (op == 29)
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/* JALX: 011101 */
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/* The new PC will be alternate mode. */
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@ -1661,8 +1661,8 @@ mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
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if (op == 54 || op == 62)
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bit += 32;
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if (((get_frame_register_signed (frame,
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itype_rs (inst)) >> bit) & 1)
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if (((regcache_raw_get_signed (regcache,
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itype_rs (inst)) >> bit) & 1)
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== branch_if)
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pc += mips32_relative_offset (inst) + 4;
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else
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@ -1685,15 +1685,15 @@ mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
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case 8: /* JR */
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case 9: /* JALR */
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/* Set PC to that address. */
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pc = get_frame_register_signed (frame, rtype_rs (inst));
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pc = regcache_raw_get_signed (regcache, rtype_rs (inst));
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break;
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case 12: /* SYSCALL */
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{
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struct gdbarch_tdep *tdep;
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tdep = gdbarch_tdep (get_frame_arch (frame));
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tdep = gdbarch_tdep (gdbarch);
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if (tdep->syscall_next_pc != NULL)
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pc = tdep->syscall_next_pc (frame);
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pc = tdep->syscall_next_pc (get_current_frame ());
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else
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pc += 4;
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}
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@ -1713,7 +1713,7 @@ mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
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case 16: /* BLTZAL */
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case 18: /* BLTZALL */
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less_branch:
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if (get_frame_register_signed (frame, itype_rs (inst)) < 0)
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if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0)
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pc += mips32_relative_offset (inst) + 4;
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else
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pc += 8; /* after the delay slot */
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@ -1722,7 +1722,7 @@ mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
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case 3: /* BGEZL */
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case 17: /* BGEZAL */
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case 19: /* BGEZALL */
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if (get_frame_register_signed (frame, itype_rs (inst)) >= 0)
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if (regcache_raw_get_signed (regcache, itype_rs (inst)) >= 0)
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pc += mips32_relative_offset (inst) + 4;
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else
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pc += 8; /* after the delay slot */
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@ -1739,8 +1739,8 @@ mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
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/* No way to handle; it'll most likely trap anyway. */
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break;
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if ((get_frame_register_unsigned (frame,
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dspctl) & 0x7f) >= pos)
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if ((regcache_raw_get_unsigned (regcache,
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dspctl) & 0x7f) >= pos)
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pc += mips32_relative_offset (inst);
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else
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pc += 4;
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@ -1763,22 +1763,22 @@ mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
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break;
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case 4: /* BEQ, BEQL */
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equal_branch:
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if (get_frame_register_signed (frame, itype_rs (inst)) ==
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get_frame_register_signed (frame, itype_rt (inst)))
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if (regcache_raw_get_signed (regcache, itype_rs (inst)) ==
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regcache_raw_get_signed (regcache, itype_rt (inst)))
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pc += mips32_relative_offset (inst) + 4;
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else
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pc += 8;
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break;
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case 5: /* BNE, BNEL */
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neq_branch:
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if (get_frame_register_signed (frame, itype_rs (inst)) !=
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get_frame_register_signed (frame, itype_rt (inst)))
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if (regcache_raw_get_signed (regcache, itype_rs (inst)) !=
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regcache_raw_get_signed (regcache, itype_rt (inst)))
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pc += mips32_relative_offset (inst) + 4;
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else
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pc += 8;
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break;
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case 6: /* BLEZ, BLEZL */
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if (get_frame_register_signed (frame, itype_rs (inst)) <= 0)
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if (regcache_raw_get_signed (regcache, itype_rs (inst)) <= 0)
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pc += mips32_relative_offset (inst) + 4;
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else
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pc += 8;
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@ -1786,7 +1786,7 @@ mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
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case 7:
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default:
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greater_branch: /* BGTZ, BGTZL */
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if (get_frame_register_signed (frame, itype_rs (inst)) > 0)
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if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0)
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pc += mips32_relative_offset (inst) + 4;
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else
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pc += 8;
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@ -1840,7 +1840,7 @@ micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc)
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examined by the branch. */
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static CORE_ADDR
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micromips_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame,
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micromips_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache,
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ULONGEST insn, CORE_ADDR pc, int count)
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{
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int fcsr = mips_regnum (gdbarch)->fp_control_status;
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@ -1854,7 +1854,7 @@ micromips_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame,
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/* No way to handle; it'll most likely trap anyway. */
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return pc;
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fcs = get_frame_register_unsigned (frame, fcsr);
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fcs = regcache_raw_get_unsigned (regcache, fcsr);
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cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01);
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if (((cond >> cnum) & mask) != mask * !tf)
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@ -1869,9 +1869,9 @@ micromips_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame,
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after the instruction at the address PC. */
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static CORE_ADDR
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micromips_next_pc (struct frame_info *frame, CORE_ADDR pc)
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micromips_next_pc (struct regcache *regcache, CORE_ADDR pc)
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{
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struct gdbarch *gdbarch = get_frame_arch (frame);
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struct gdbarch *gdbarch = get_regcache_arch (regcache);
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ULONGEST insn;
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insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
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@ -1891,7 +1891,7 @@ micromips_next_pc (struct frame_info *frame, CORE_ADDR pc)
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&& (b6s10_ext (insn) & 0x2bf) == 0x3c)
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/* JALR, JALR.HB: 000000 000x111100 111100 */
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/* JALRS, JALRS.HB: 000000 010x111100 111100 */
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pc = get_frame_register_signed (frame, b0s5_reg (insn >> 16));
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pc = regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16));
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break;
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case 0x10: /* POOL32I: bits 010000 */
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@ -1900,8 +1900,8 @@ micromips_next_pc (struct frame_info *frame, CORE_ADDR pc)
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case 0x00: /* BLTZ: bits 010000 00000 */
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case 0x01: /* BLTZAL: bits 010000 00001 */
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case 0x11: /* BLTZALS: bits 010000 10001 */
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if (get_frame_register_signed (frame,
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b0s5_reg (insn >> 16)) < 0)
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if (regcache_raw_get_signed (regcache,
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b0s5_reg (insn >> 16)) < 0)
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pc += micromips_relative_offset16 (insn);
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else
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pc += micromips_pc_insn_size (gdbarch, pc);
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@ -1910,38 +1910,38 @@ micromips_next_pc (struct frame_info *frame, CORE_ADDR pc)
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case 0x02: /* BGEZ: bits 010000 00010 */
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case 0x03: /* BGEZAL: bits 010000 00011 */
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case 0x13: /* BGEZALS: bits 010000 10011 */
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if (get_frame_register_signed (frame,
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b0s5_reg (insn >> 16)) >= 0)
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if (regcache_raw_get_signed (regcache,
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b0s5_reg (insn >> 16)) >= 0)
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pc += micromips_relative_offset16 (insn);
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else
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pc += micromips_pc_insn_size (gdbarch, pc);
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break;
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case 0x04: /* BLEZ: bits 010000 00100 */
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if (get_frame_register_signed (frame,
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b0s5_reg (insn >> 16)) <= 0)
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if (regcache_raw_get_signed (regcache,
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b0s5_reg (insn >> 16)) <= 0)
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pc += micromips_relative_offset16 (insn);
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else
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pc += micromips_pc_insn_size (gdbarch, pc);
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break;
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case 0x05: /* BNEZC: bits 010000 00101 */
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if (get_frame_register_signed (frame,
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b0s5_reg (insn >> 16)) != 0)
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if (regcache_raw_get_signed (regcache,
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b0s5_reg (insn >> 16)) != 0)
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pc += micromips_relative_offset16 (insn);
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break;
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case 0x06: /* BGTZ: bits 010000 00110 */
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if (get_frame_register_signed (frame,
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b0s5_reg (insn >> 16)) > 0)
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if (regcache_raw_get_signed (regcache,
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b0s5_reg (insn >> 16)) > 0)
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pc += micromips_relative_offset16 (insn);
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else
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pc += micromips_pc_insn_size (gdbarch, pc);
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break;
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case 0x07: /* BEQZC: bits 010000 00111 */
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if (get_frame_register_signed (frame,
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b0s5_reg (insn >> 16)) == 0)
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if (regcache_raw_get_signed (regcache,
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b0s5_reg (insn >> 16)) == 0)
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pc += micromips_relative_offset16 (insn);
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break;
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@ -1962,8 +1962,8 @@ micromips_next_pc (struct frame_info *frame, CORE_ADDR pc)
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/* No way to handle; it'll most likely trap anyway. */
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break;
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if ((get_frame_register_unsigned (frame,
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dspctl) & 0x7f) >= pos)
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if ((regcache_raw_get_unsigned (regcache,
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dspctl) & 0x7f) >= pos)
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pc += micromips_relative_offset16 (insn);
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else
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pc += micromips_pc_insn_size (gdbarch, pc);
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@ -1975,14 +1975,14 @@ micromips_next_pc (struct frame_info *frame, CORE_ADDR pc)
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case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
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/* BC1ANY2T: bits 010000 11101 xxx01 */
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if (((insn >> 16) & 0x2) == 0x0)
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pc = micromips_bc1_pc (gdbarch, frame, insn, pc,
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pc = micromips_bc1_pc (gdbarch, regcache, insn, pc,
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((insn >> 16) & 0x1) + 1);
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break;
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case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
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case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
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if (((insn >> 16) & 0x3) == 0x1)
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pc = micromips_bc1_pc (gdbarch, frame, insn, pc, 4);
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pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, 4);
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break;
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}
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break;
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@ -1994,16 +1994,16 @@ micromips_next_pc (struct frame_info *frame, CORE_ADDR pc)
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break;
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case 0x25: /* BEQ: bits 100101 */
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if (get_frame_register_signed (frame, b0s5_reg (insn >> 16))
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== get_frame_register_signed (frame, b5s5_reg (insn >> 16)))
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if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16))
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== regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16)))
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pc += micromips_relative_offset16 (insn);
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else
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pc += micromips_pc_insn_size (gdbarch, pc);
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break;
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case 0x2d: /* BNE: bits 101101 */
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if (get_frame_register_signed (frame, b0s5_reg (insn >> 16))
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!= get_frame_register_signed (frame, b5s5_reg (insn >> 16)))
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if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16))
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!= regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16)))
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pc += micromips_relative_offset16 (insn);
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else
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pc += micromips_pc_insn_size (gdbarch, pc);
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@ -2022,17 +2022,17 @@ micromips_next_pc (struct frame_info *frame, CORE_ADDR pc)
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case 0x11: /* POOL16C: bits 010001 */
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if ((b5s5_op (insn) & 0x1c) == 0xc)
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/* JR16, JRC, JALR16, JALRS16: 010001 011xx */
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pc = get_frame_register_signed (frame, b0s5_reg (insn));
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pc = regcache_raw_get_signed (regcache, b0s5_reg (insn));
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else if (b5s5_op (insn) == 0x18)
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/* JRADDIUSP: bits 010001 11000 */
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pc = get_frame_register_signed (frame, MIPS_RA_REGNUM);
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pc = regcache_raw_get_signed (regcache, MIPS_RA_REGNUM);
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break;
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case 0x23: /* BEQZ16: bits 100011 */
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{
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int rs = mips_reg3_to_reg[b7s3_reg (insn)];
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if (get_frame_register_signed (frame, rs) == 0)
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if (regcache_raw_get_signed (regcache, rs) == 0)
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pc += micromips_relative_offset7 (insn);
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else
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pc += micromips_pc_insn_size (gdbarch, pc);
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@ -2043,7 +2043,7 @@ micromips_next_pc (struct frame_info *frame, CORE_ADDR pc)
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{
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int rs = mips_reg3_to_reg[b7s3_reg (insn)];
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if (get_frame_register_signed (frame, rs) != 0)
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if (regcache_raw_get_signed (regcache, rs) != 0)
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pc += micromips_relative_offset7 (insn);
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else
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pc += micromips_pc_insn_size (gdbarch, pc);
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@ -2222,10 +2222,10 @@ add_offset_16 (CORE_ADDR pc, int offset)
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}
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static CORE_ADDR
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extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc,
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extended_mips16_next_pc (regcache *regcache, CORE_ADDR pc,
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unsigned int extension, unsigned int insn)
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{
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struct gdbarch *gdbarch = get_frame_arch (frame);
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struct gdbarch *gdbarch = get_regcache_arch (regcache);
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int op = (insn >> 11);
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switch (op)
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{
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||||
@ -2253,7 +2253,7 @@ extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc,
|
||||
struct upk_mips16 upk;
|
||||
int reg;
|
||||
unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk);
|
||||
reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]);
|
||||
reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]);
|
||||
if (reg == 0)
|
||||
pc = add_offset_16 (pc, upk.offset);
|
||||
else
|
||||
@ -2265,7 +2265,7 @@ extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc,
|
||||
struct upk_mips16 upk;
|
||||
int reg;
|
||||
unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk);
|
||||
reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]);
|
||||
reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]);
|
||||
if (reg != 0)
|
||||
pc = add_offset_16 (pc, upk.offset);
|
||||
else
|
||||
@ -2278,7 +2278,8 @@ extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc,
|
||||
int reg;
|
||||
unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk);
|
||||
/* upk.regx contains the opcode */
|
||||
reg = get_frame_register_signed (frame, 24); /* Test register is 24 */
|
||||
/* Test register is 24 */
|
||||
reg = regcache_raw_get_signed (regcache, 24);
|
||||
if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
|
||||
|| ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
|
||||
pc = add_offset_16 (pc, upk.offset);
|
||||
@ -2300,7 +2301,7 @@ extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc,
|
||||
reg = mips_reg3_to_reg[upk.regx];
|
||||
else
|
||||
reg = 31; /* Function return instruction. */
|
||||
pc = get_frame_register_signed (frame, reg);
|
||||
pc = regcache_raw_get_signed (regcache, reg);
|
||||
}
|
||||
else
|
||||
pc += 2;
|
||||
@ -2312,7 +2313,7 @@ extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc,
|
||||
that. */
|
||||
{
|
||||
pc += 2;
|
||||
pc = extended_mips16_next_pc (frame, pc, insn,
|
||||
pc = extended_mips16_next_pc (regcache, pc, insn,
|
||||
fetch_mips_16 (gdbarch, pc));
|
||||
break;
|
||||
}
|
||||
@ -2326,11 +2327,11 @@ extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc,
|
||||
}
|
||||
|
||||
static CORE_ADDR
|
||||
mips16_next_pc (struct frame_info *frame, CORE_ADDR pc)
|
||||
mips16_next_pc (struct regcache *regcache, CORE_ADDR pc)
|
||||
{
|
||||
struct gdbarch *gdbarch = get_frame_arch (frame);
|
||||
struct gdbarch *gdbarch = get_regcache_arch (regcache);
|
||||
unsigned int insn = fetch_mips_16 (gdbarch, pc);
|
||||
return extended_mips16_next_pc (frame, pc, 0, insn);
|
||||
return extended_mips16_next_pc (regcache, pc, 0, insn);
|
||||
}
|
||||
|
||||
/* The mips_next_pc function supports single_step when the remote
|
||||
@ -2339,16 +2340,16 @@ mips16_next_pc (struct frame_info *frame, CORE_ADDR pc)
|
||||
branch will go. This isn't hard because all the data is available.
|
||||
The MIPS32, MIPS16 and microMIPS variants are quite different. */
|
||||
static CORE_ADDR
|
||||
mips_next_pc (struct frame_info *frame, CORE_ADDR pc)
|
||||
mips_next_pc (struct regcache *regcache, CORE_ADDR pc)
|
||||
{
|
||||
struct gdbarch *gdbarch = get_frame_arch (frame);
|
||||
struct gdbarch *gdbarch = get_regcache_arch (regcache);
|
||||
|
||||
if (mips_pc_is_mips16 (gdbarch, pc))
|
||||
return mips16_next_pc (frame, pc);
|
||||
return mips16_next_pc (regcache, pc);
|
||||
else if (mips_pc_is_micromips (gdbarch, pc))
|
||||
return micromips_next_pc (frame, pc);
|
||||
return micromips_next_pc (regcache, pc);
|
||||
else
|
||||
return mips32_next_pc (frame, pc);
|
||||
return mips32_next_pc (regcache, pc);
|
||||
}
|
||||
|
||||
/* Return non-zero if the MIPS16 instruction INSN is a compact branch
|
||||
@ -4150,16 +4151,17 @@ deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
|
||||
VEC (CORE_ADDR) *
|
||||
mips_software_single_step (struct frame_info *frame)
|
||||
{
|
||||
struct gdbarch *gdbarch = get_frame_arch (frame);
|
||||
struct regcache *regcache = get_current_regcache ();
|
||||
struct gdbarch *gdbarch = get_regcache_arch (regcache);
|
||||
CORE_ADDR pc, next_pc;
|
||||
VEC (CORE_ADDR) *next_pcs;
|
||||
|
||||
pc = get_frame_pc (frame);
|
||||
pc = regcache_read_pc (regcache);
|
||||
next_pcs = deal_with_atomic_sequence (gdbarch, pc);
|
||||
if (next_pcs != NULL)
|
||||
return next_pcs;
|
||||
|
||||
next_pc = mips_next_pc (frame, pc);
|
||||
next_pc = mips_next_pc (regcache, pc);
|
||||
|
||||
VEC_safe_push (CORE_ADDR, next_pcs, next_pc);
|
||||
return next_pcs;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user