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[AArch64 disassembler] Add missing checks of undefine encodings on
st1/st2/st3/st4 instructions. opcodes/ * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined instructions. binutils/testsuite/ * binutils-all/aarch64/aarch64.exp: New test driver for AArch64. * binutils-all/aarch64/unallocated-encoding.s: New testcase. * binutils-all/aarch64/unallocated-encoding.d: Ditto.
This commit is contained in:
Yufeng Zhang
parent
b3fe4307a6
commit
76dfed02aa
@ -1,3 +1,9 @@
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2014-03-26 Jiong Wang <jiong.wang@arm.com>
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* binutils-all/aarch64/aarch64.exp: New test driver for AArch64.
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* binutils-all/aarch64/unallocated-encoding.s: New testcase.
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* binutils-all/aarch64/unallocated-encoding.d: Ditto.
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2014-03-17 Nick Clifton <nickc@redhat.com>
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* binutils-all/readelf.ss: Add skip of MSP430 defined symbols.
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30
binutils/testsuite/binutils-all/aarch64/aarch64.exp
Normal file
30
binutils/testsuite/binutils-all/aarch64/aarch64.exp
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@ -0,0 +1,30 @@
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# Copyright (C) 2014 Free Software Foundation, Inc.
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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if {![istarget "aarch64*-*-*"]
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|| ![is_elf_format]} then {
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return
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}
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set tempfile tmpdir/aarch64temp.o
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set copyfile tmpdir/aarch64copy
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set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
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foreach t $test_list {
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# We need to strip the ".d", but can leave the dirname.
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verbose [file rootname $t]
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run_dump_test [file rootname $t]
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}
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@ -0,0 +1,29 @@
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#PROG: objcopy
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#objdump: -dr
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#name: Disassembler detects unallocated instruction encodings.
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.*: +file format .*aarch64.*
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Disassembly of section \.text:
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0000000000000000 <.*>:
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0: 0d0047de .inst 0x0d0047de ; undefined
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4: 0d2047dd .inst 0x0d2047dd ; undefined
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8: 0d0067dc .inst 0x0d0067dc ; undefined
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c: 0d2067db .inst 0x0d2067db ; undefined
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10: 0d008bde .inst 0x0d008bde ; undefined
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14: 0d208bdd .inst 0x0d208bdd ; undefined
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18: 0d00abdc .inst 0x0d00abdc ; undefined
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1c: 0d20abdb .inst 0x0d20abdb ; undefined
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20: 0d008fde .inst 0x0d008fde ; undefined
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24: 0d208fdd .inst 0x0d208fdd ; undefined
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28: 0d00afdc .inst 0x0d00afdc ; undefined
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2c: 0d20afdb .inst 0x0d20afdb ; undefined
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30: 0d0097de .inst 0x0d0097de ; undefined
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34: 0d2097dd .inst 0x0d2097dd ; undefined
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38: 0d00b7dc .inst 0x0d00b7dc ; undefined
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3c: 0d20b7db .inst 0x0d20b7db ; undefined
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40: 0d009fde .inst 0x0d009fde ; undefined
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44: 0d209fdd .inst 0x0d209fdd ; undefined
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48: 0d00bfdc .inst 0x0d00bfdc ; undefined
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4c: 0d20bfdb .inst 0x0d20bfdb ; undefined
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@ -0,0 +1,51 @@
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.text
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func:
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//scale 1, size<0> check for H.
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#st1 {v30.h}[0], [x30]
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.inst 0x0d0043de | (1 << 10)
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#st2 {v29.h, v30.h}[0], [x30]
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.inst 0x0d2043dd | (1 << 10)
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#st3 {v28.h, v29.h, v30.h}[0], [x30]
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.inst 0x0d0063dc | (1 << 10)
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#st4 {v27.h, v28.h, v29.h, v30.h}[0], [x30]
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.inst 0x0d2063db | (1 << 10)
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//scale 2, size<1> check for S.
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#st1 {v30.s}[0], [x30]
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.inst 0x0d0083de | (1 << 11)
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#st2 {v29.s, v30.s}[0], [x30]
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.inst 0x0d2083dd | (1 << 11)
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#st3 {v28.s, v29.s, v30.s}[0], [x30]
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.inst 0x0d00a3dc | (1 << 11)
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#st4 {v27.s, v28.s, v29.s, v30.s}[0], [x30]
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.inst 0x0d20a3db | (1 << 11)
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//scale 2, size<1> check for D.
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#st1 {v30.d}[0], [x30]
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.inst 0x0d0087de | (1 << 11)
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#st2 {v29.d, v30.d}[0], [x30]
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.inst 0x0d2087dd | (1 << 11)
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#st3 {v28.d, v29.d, v30.d}[0], [x30]
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.inst 0x0d00a7dc | (1 << 11)
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#st4 {v27.d, v28.d, v29.d, v30.d}[0], [x30]
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.inst 0x0d20a7db | (1 << 11)
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//scale 2, S-bit check for D.
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#st1 {v30.d}[0], [x30]
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.inst 0x0d0087de | (2 << 11)
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#st2 {v29.d, v30.d}[0], [x30]
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.inst 0x0d2087dd | (2 << 11)
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#st3 {v28.d, v29.d, v30.d}[0], [x30]
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.inst 0x0d00a7dc | (2 << 11)
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#st4 {v27.d, v28.d, v29.d, v30.d}[0], [x30]
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.inst 0x0d20a7db | (2 << 11)
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//scale 2, size<1> & S-bit check for D.
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#st1 {v30.d}[0], [x30]
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.inst 0x0d0087de | (3 << 11)
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#st2 {v29.d, v30.d}[0], [x30]
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.inst 0x0d2087dd | (3 << 11)
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#st3 {v28.d, v29.d, v30.d}[0], [x30]
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.inst 0x0d00a7dc | (3 << 11)
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#st4 {v27.d, v28.d, v29.d, v30.d}[0], [x30]
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.inst 0x0d20a7db | (3 << 11)
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@ -1,3 +1,8 @@
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2014-03-26 Jiong Wang <jiong.wang@arm.com>
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* aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
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instructions.
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2014-03-20 Ilya Tocar <ilya.tocar@intel.com>
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* i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
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@ -422,11 +422,17 @@ aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
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info->reglist.index = QSsize;
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break;
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case 0x1:
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if (QSsize & 0x1)
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/* UND. */
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return 0;
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info->qualifier = AARCH64_OPND_QLF_S_H;
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/* Index encoded in "Q:S:size<1>". */
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info->reglist.index = QSsize >> 1;
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break;
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case 0x2:
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if ((QSsize >> 1) & 0x1)
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/* UND. */
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return 0;
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if ((QSsize & 0x1) == 0)
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{
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info->qualifier = AARCH64_OPND_QLF_S_S;
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@ -435,12 +441,12 @@ aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
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}
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else
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{
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info->qualifier = AARCH64_OPND_QLF_S_D;
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/* Index encoded in "Q". */
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info->reglist.index = QSsize >> 3;
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if (extract_field (FLD_S, code, 0))
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/* UND */
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return 0;
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info->qualifier = AARCH64_OPND_QLF_S_D;
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/* Index encoded in "Q". */
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info->reglist.index = QSsize >> 3;
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}
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break;
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default:
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