darlinghq/darling-gdb
1
0
Fork 0
mirror of https://github.com/darlinghq/darling-gdb.git synced 2025-01-22 09:04:58 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Adjust for branch target encoding change

Browse Source
This commit is contained in:
Anthony Green 2012-09-08 01:26:07 +00:00
parent 7078b4097f
commit 78ca4e81ff
2 changed files with 15 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
sim/moxie/ChangeLog
View File

@ -1,3 +1,8 @@
2012-09-07 Anthony Green <green@moxielogic.com>
* interp.c (sim_resume): Branches are now relative to the
address of the instruction following the branch.
2012-06-17 Mike Frysinger <vapier@gentoo.org>
* interp.c: Include config.h first. Also include fcntl.h directly.

20
sim/moxie/interp.c
View File

@ -290,69 +290,69 @@ sim_resume (sd, step, siggnal)
{
TRACE("beq");
if (cpu.asregs.cc & CC_EQ)
pc += INST2OFFSET(inst) - 2;
pc += INST2OFFSET(inst);
}
break;
case 0x01: /* bne */
{
TRACE("bne");
if (! (cpu.asregs.cc & CC_EQ))
pc += INST2OFFSET(inst) - 2;
pc += INST2OFFSET(inst);
}
break;
case 0x02: /* blt */
{
TRACE("blt");
if (cpu.asregs.cc & CC_LT)
pc += INST2OFFSET(inst) - 2;
pc += INST2OFFSET(inst);
} break;
case 0x03: /* bgt */
{
TRACE("bgt");
if (cpu.asregs.cc & CC_GT)
pc += INST2OFFSET(inst) - 2;
pc += INST2OFFSET(inst);
}
break;
case 0x04: /* bltu */
{
TRACE("bltu");
if (cpu.asregs.cc & CC_LTU)
pc += INST2OFFSET(inst) - 2;
pc += INST2OFFSET(inst);
}
break;
case 0x05: /* bgtu */
{
TRACE("bgtu");
if (cpu.asregs.cc & CC_GTU)
pc += INST2OFFSET(inst) - 2;
pc += INST2OFFSET(inst);
}
break;
case 0x06: /* bge */
{
TRACE("bge");
if (cpu.asregs.cc & (CC_GT | CC_EQ))
pc += INST2OFFSET(inst) - 2;
pc += INST2OFFSET(inst);
}
break;
case 0x07: /* ble */
{
TRACE("ble");
if (cpu.asregs.cc & (CC_LT | CC_EQ))
pc += INST2OFFSET(inst) - 2;
pc += INST2OFFSET(inst);
}
break;
case 0x08: /* bgeu */
{
TRACE("bgeu");
if (cpu.asregs.cc & (CC_GTU | CC_EQ))
pc += INST2OFFSET(inst) - 2;
pc += INST2OFFSET(inst);
}
break;
case 0x09: /* bleu */
{
TRACE("bleu");
if (cpu.asregs.cc & (CC_LTU | CC_EQ))
pc += INST2OFFSET(inst) - 2;
pc += INST2OFFSET(inst);
}
break;
default: