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IGEN likes to cache the current instruction address (CIA). Change the
MIPS simulator so that correctly writes the value of CIA back int PC (the global previously used) when the simulation halts. Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
This commit is contained in:
Andrew Cagney
parent
864519b9fd
commit
7ce8b9178c
@ -1,3 +1,36 @@
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Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (signal_exception, store_word, load_word,
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address_translation, load_memory, store_memory, cache_op,
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prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
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cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc): Add current
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instruction address - cia - argument.
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(sim_read, sim_write): Call address_translation directly.
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(sim_engine_run): Rename variable vaddr to cia.
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* sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
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Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
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COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
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* sim-main.h (SignalExceptionSimulatorFault): Delete definition.
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* interp.c (sim_open): Replace SignalExceptionSimulatorFault with
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SIM_ASSERT.
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* interp.c (signal_exception): Pass restart address to
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sim_engine_restart.
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* Makefile.in (semantics.o, engine.o, support.o, itable.o,
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idecode.o): Add dependency.
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* sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
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Delete definitions
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(DELAY_SLOT): Update NIA not PC with branch address.
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(NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
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* mips.igen: Use CIA not PC in branch calculations.
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(illegal): Call SignalException.
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(BEQ, ADDIU): Fix assembler.
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Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* m16.igen (JALX): Was missing.
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@ -180,6 +180,12 @@ tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
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$(srcdir)/../../move-if-change tmp-irun.c irun.c
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touch tmp-igen
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semantics.o: sim-main.h $(SIM_EXTRA_DEPS)
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engine.o: sim-main.h $(SIM_EXTRA_DEPS)
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support.o: sim-main.h $(SIM_EXTRA_DEPS)
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idecode.o: sim-main.h $(SIM_EXTRA_DEPS)
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itable.o: sim-main.h $(SIM_EXTRA_DEPS)
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SIM_M16_ALL = tmp-igen $(SIM_M16_ALL)
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@ -319,10 +319,8 @@ sim_open (kind, cb, abfd, argv)
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/* verify assumptions the simulator made about the host type system.
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This macro does not return if there is a problem */
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if (sizeof(int) != (4 * sizeof(char)))
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SignalExceptionSimulatorFault ("sizeof(int) != 4");
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if (sizeof(word64) != (8 * sizeof(char)))
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SignalExceptionSimulatorFault ("sizeof(word64) != 8");
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SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
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SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
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#if defined(HASFPU)
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/* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
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@ -507,7 +505,7 @@ sim_write (sd,addr,buffer,size)
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address_word vaddr = (address_word)addr + index;
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address_word paddr;
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int cca;
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if (!AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &cca, isTARGET, isRAW))
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if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
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break;
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if (sim_core_write_buffer (sd, NULL, sim_core_read_map, buffer + index, paddr, 1) != 1)
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break;
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@ -535,7 +533,7 @@ sim_read (sd,addr,buffer,size)
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address_word vaddr = (address_word)addr + index;
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address_word paddr;
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int cca;
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if (!AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &cca, isTARGET, isRAW))
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if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
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break;
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if (sim_core_read_buffer (sd, NULL, sim_core_read_map, buffer + index, paddr, 1) != 1)
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break;
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@ -937,8 +935,9 @@ sim_monitor(sd,reason)
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/* Store a word into memory. */
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static void
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store_word (sd, vaddr, val)
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store_word (sd, cia, vaddr, val)
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SIM_DESC sd;
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address_word cia;
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uword64 vaddr;
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t_reg val;
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{
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@ -968,8 +967,9 @@ store_word (sd, vaddr, val)
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/* Load a word from memory. */
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static t_reg
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load_word (sd, vaddr)
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load_word (sd, cia, vaddr)
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SIM_DESC sd;
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address_word cia;
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uword64 vaddr;
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{
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if ((vaddr & 3) != 0)
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@ -1219,8 +1219,9 @@ ColdReset (sd)
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function raises an exception and does not return. */
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int
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address_translation(sd,vAddr,IorD,LorS,pAddr,CCA,raw)
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address_translation(sd,cia,vAddr,IorD,LorS,pAddr,CCA,raw)
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SIM_DESC sd;
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address_word cia;
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address_word vAddr;
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int IorD;
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int LorS;
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@ -1254,8 +1255,9 @@ address_translation(sd,vAddr,IorD,LorS,pAddr,CCA,raw)
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program, or alter architecturally-visible state. */
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void
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prefetch(sd,CCA,pAddr,vAddr,DATA,hint)
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prefetch(sd,cia,CCA,pAddr,vAddr,DATA,hint)
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SIM_DESC sd;
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address_word cia;
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int CCA;
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address_word pAddr;
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address_word vAddr;
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@ -1287,8 +1289,9 @@ prefetch(sd,CCA,pAddr,vAddr,DATA,hint)
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satisfy a load reference. At a minimum, the block is the entire
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memory element. */
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void
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load_memory(sd,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD)
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load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD)
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SIM_DESC sd;
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address_word cia;
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uword64* memvalp;
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uword64* memval1p;
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int CCA;
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@ -1417,8 +1420,9 @@ load_memory(sd,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD)
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will be changed. */
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void
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store_memory(sd,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr)
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store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr)
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SIM_DESC sd;
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address_word cia;
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int CCA;
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int AccessLength;
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uword64 MemElem;
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@ -1513,7 +1517,9 @@ store_memory(sd,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr)
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unsigned32
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ifetch32 (SIM_DESC sd, address_word vaddr)
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ifetch32 (SIM_DESC sd,
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address_word cia,
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address_word vaddr)
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{
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/* Copy the action of the LW instruction */
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address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
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@ -1538,8 +1544,9 @@ ifetch32 (SIM_DESC sd, address_word vaddr)
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loads and stores indicated by stype occur in the same order for all
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processors. */
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void
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sync_operation(sd,stype)
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sync_operation(sd,cia,stype)
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SIM_DESC sd;
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address_word cia;
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int stype;
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{
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#ifdef DEBUG
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@ -1554,7 +1561,9 @@ sync_operation(sd,stype)
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will never see a return from this function call. */
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void
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signal_exception (SIM_DESC sd, int exception,...)
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signal_exception (SIM_DESC sd,
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address_word cia,
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int exception,...)
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{
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int vector;
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@ -1630,22 +1639,24 @@ signal_exception (SIM_DESC sd, int exception,...)
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space with suitable instruction values. For systems were
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actual trap instructions are used, we would not need to
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perform this magic. */
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if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION) {
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sim_monitor(sd, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
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PC = RA; /* simulate the return from the vector entry */
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/* NOTE: This assumes that a branch-and-link style
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instruction was used to enter the vector (which is the
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case with the current IDT monitor). */
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sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA);
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}
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if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
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{
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sim_monitor(sd, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
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/* NOTE: This assumes that a branch-and-link style
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instruction was used to enter the vector (which is the
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case with the current IDT monitor). */
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sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, RA);
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}
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/* Look for the mips16 entry and exit instructions, and
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simulate a handler for them. */
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else if ((IPC & 1) != 0
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&& (instruction & 0xf81f) == 0xe809
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&& (instruction & 0x0c0) != 0x0c0) {
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mips16_entry (instruction);
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sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA);
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} /* else fall through to normal exception processing */
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&& (instruction & 0x0c0) != 0x0c0)
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{
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mips16_entry (instruction);
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sim_engine_restart (sd, NULL, NULL, NULL_CIA);
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}
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/* else fall through to normal exception processing */
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sim_io_eprintf(sd,"ReservedInstruction 0x%08X at IPC = 0x%s\n",instruction,pr_addr(IPC));
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}
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@ -1663,7 +1674,7 @@ signal_exception (SIM_DESC sd, int exception,...)
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va_end(ap);
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/* Check for our special terminating BREAK: */
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if ((instruction & 0x03FFFFC0) == 0x03ff0000) {
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sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
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sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, cia,
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sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
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}
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}
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@ -1795,8 +1806,9 @@ UndefinedResult()
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#endif /* WARN_RESULT */
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void
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cache_op(sd,op,pAddr,vAddr,instruction)
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cache_op(sd,cia,op,pAddr,vAddr,instruction)
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SIM_DESC sd;
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address_word cia;
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int op;
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address_word pAddr;
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address_word vAddr;
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@ -1930,8 +1942,9 @@ cache_op(sd,op,pAddr,vAddr,instruction)
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#endif /* DEBUG */
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uword64
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value_fpr(sd,fpr,fmt)
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value_fpr(sd,cia,fpr,fmt)
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SIM_DESC sd;
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address_word cia;
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int fpr;
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FP_formats fmt;
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{
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@ -2034,8 +2047,9 @@ value_fpr(sd,fpr,fmt)
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}
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void
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store_fpr(sd,fpr,fmt,value)
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store_fpr(sd,cia,fpr,fmt,value)
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SIM_DESC sd;
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address_word cia;
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int fpr;
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FP_formats fmt;
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uword64 value;
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@ -2586,8 +2600,9 @@ SquareRoot(op,fmt)
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}
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uword64
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convert(sd,rm,op,from,to)
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convert(sd,cia,rm,op,from,to)
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SIM_DESC sd;
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address_word cia;
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int rm;
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uword64 op;
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FP_formats from;
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@ -2803,8 +2818,9 @@ CoProcPresent(coproc_number)
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}
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void
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cop_lw(sd,coproc_num,coproc_reg,memword)
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cop_lw(sd,cia,coproc_num,coproc_reg,memword)
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SIM_DESC sd;
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address_word cia;
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int coproc_num, coproc_reg;
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unsigned int memword;
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{
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@ -2830,8 +2846,9 @@ cop_lw(sd,coproc_num,coproc_reg,memword)
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}
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void
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cop_ld(sd,coproc_num,coproc_reg,memword)
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cop_ld(sd,cia,coproc_num,coproc_reg,memword)
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SIM_DESC sd;
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address_word cia;
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int coproc_num, coproc_reg;
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uword64 memword;
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{
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@ -2853,8 +2870,9 @@ cop_ld(sd,coproc_num,coproc_reg,memword)
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}
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unsigned int
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cop_sw(sd,coproc_num,coproc_reg)
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cop_sw(sd,cia,coproc_num,coproc_reg)
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SIM_DESC sd;
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address_word cia;
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int coproc_num, coproc_reg;
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{
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unsigned int value = 0;
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@ -2894,8 +2912,9 @@ cop_sw(sd,coproc_num,coproc_reg)
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}
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uword64
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cop_sd(sd,coproc_num,coproc_reg)
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cop_sd(sd,cia,coproc_num,coproc_reg)
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SIM_DESC sd;
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address_word cia;
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int coproc_num, coproc_reg;
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{
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uword64 value = 0;
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@ -2928,8 +2947,9 @@ cop_sd(sd,coproc_num,coproc_reg)
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}
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void
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decode_coproc(sd,instruction)
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decode_coproc(sd,cia,instruction)
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SIM_DESC sd;
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address_word cia;
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unsigned int instruction;
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{
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int coprocnum = ((instruction >> 26) & 3);
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@ -3113,8 +3133,10 @@ sim_engine_run (sd, next_cpu_nr, siggnal)
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/* main controlling loop */
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while (1) {
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/* Fetch the next instruction from the simulator memory: */
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address_word vaddr = (uword64)PC;
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/* vaddr is slowly being replaced with cia - current instruction
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address */
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address_word cia = (uword64)PC;
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address_word vaddr = cia;
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address_word paddr;
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int cca;
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unsigned int instruction; /* uword64? what's this used for? FIXME! */
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@ -3134,7 +3156,8 @@ sim_engine_run (sd, next_cpu_nr, siggnal)
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sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
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#endif /* DEBUG */
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if (AddressTranslation(PC,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
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/* Fetch the next instruction from the simulator memory: */
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if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
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if ((vaddr & 1) == 0) {
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/* Copy the action of the LW instruction */
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unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
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@ -50,16 +50,15 @@
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// Pseudo instructions known by IGEN
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:internal::::illegal:
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{
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sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
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(unsigned long) CIA);
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sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
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/* FIXME: This ifetch causes a double count of a fetch at CIA */
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SignalException (ReservedInstruction, IMEM (CIA));
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}
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//
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// MIPS Architecture:
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// Mips Architecture:
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//
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// CPU Instruction Set (mipsI - mipsIV)
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//
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@ -112,7 +111,7 @@
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001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
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"add r<RT>, r<RS>, IMMEDIATE"
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"add r<RT>, r<RS>, <IMMEDIATE>"
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*mipsI:
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*mipsII:
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*mipsIII:
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@ -196,7 +195,7 @@
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000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
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"beq r<RS>, r<RT>, OFFSET"
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"beq r<RS>, r<RT>, <OFFSET>"
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*mipsI:
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*mipsII:
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*mipsIII:
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@ -214,7 +213,7 @@
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{
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address_word offset = EXTEND16 (OFFSET) << 2;
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if (GPR[RS] == GPR[RT])
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DELAY_SLOT (PC + offset);
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DELAY_SLOT (CIA + offset);
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}
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@ -236,7 +235,7 @@
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{
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address_word offset = EXTEND16 (OFFSET) << 2;
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if (GPR[RS] == GPR[RT])
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DELAY_SLOT (PC + offset);
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DELAY_SLOT (CIA + offset);
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else
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NULLIFY_NEXT_INSTRUCTION ();
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}
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@ -261,7 +260,7 @@
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{
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address_word offset = EXTEND16 (OFFSET) << 2;
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if (GPR[RS] >= 0)
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DELAY_SLOT (PC + offset);
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DELAY_SLOT (CIA + offset);
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}
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@ -285,7 +284,7 @@
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address_word offset = EXTEND16 (OFFSET) << 2;
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RA = (CIA + 8);
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if (GPR[RS] >= 0)
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DELAY_SLOT (PC + offset);
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DELAY_SLOT (CIA + offset);
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}
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@ -310,7 +309,7 @@
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/* NOTE: The branch occurs AFTER the next instruction has been
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executed */
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if (GPR[RS] >= 0)
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DELAY_SLOT (PC + offset);
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DELAY_SLOT (CIA + offset);
|
||||
else
|
||||
NULLIFY_NEXT_INSTRUCTION ();
|
||||
}
|
||||
@ -334,7 +333,7 @@
|
||||
{
|
||||
address_word offset = EXTEND16 (OFFSET) << 2;
|
||||
if (GPR[RS] >= 0)
|
||||
DELAY_SLOT (PC + offset);
|
||||
DELAY_SLOT (CIA + offset);
|
||||
else
|
||||
NULLIFY_NEXT_INSTRUCTION ();
|
||||
}
|
||||
@ -359,7 +358,7 @@
|
||||
{
|
||||
address_word offset = EXTEND16 (OFFSET) << 2;
|
||||
if (GPR[RS] > 0)
|
||||
DELAY_SLOT (PC + offset);
|
||||
DELAY_SLOT (CIA + offset);
|
||||
}
|
||||
|
||||
|
||||
@ -383,7 +382,7 @@
|
||||
/* NOTE: The branch occurs AFTER the next instruction has been
|
||||
executed */
|
||||
if (GPR[RS] > 0)
|
||||
DELAY_SLOT (PC + offset);
|
||||
DELAY_SLOT (CIA + offset);
|
||||
else
|
||||
NULLIFY_NEXT_INSTRUCTION ();
|
||||
}
|
||||
@ -410,7 +409,7 @@
|
||||
/* NOTE: The branch occurs AFTER the next instruction has been
|
||||
executed */
|
||||
if (GPR[RS] <= 0)
|
||||
DELAY_SLOT (PC + offset);
|
||||
DELAY_SLOT (CIA + offset);
|
||||
}
|
||||
|
||||
|
||||
@ -432,7 +431,7 @@
|
||||
{
|
||||
address_word offset = EXTEND16 (OFFSET) << 2;
|
||||
if (GPR[RS] <= 0)
|
||||
DELAY_SLOT (PC + offset);
|
||||
DELAY_SLOT (CIA + offset);
|
||||
else
|
||||
NULLIFY_NEXT_INSTRUCTION ();
|
||||
}
|
||||
@ -457,7 +456,7 @@
|
||||
{
|
||||
address_word offset = EXTEND16 (OFFSET) << 2;
|
||||
if (GPR[RS] < 0)
|
||||
DELAY_SLOT (PC + offset);
|
||||
DELAY_SLOT (CIA + offset);
|
||||
}
|
||||
|
||||
|
||||
@ -483,7 +482,7 @@
|
||||
/* NOTE: The branch occurs AFTER the next instruction has been
|
||||
executed */
|
||||
if (GPR[RS] < 0)
|
||||
DELAY_SLOT (PC + offset);
|
||||
DELAY_SLOT (CIA + offset);
|
||||
}
|
||||
|
||||
|
||||
@ -506,7 +505,7 @@
|
||||
address_word offset = EXTEND16 (OFFSET) << 2;
|
||||
RA = (CIA + 8);
|
||||
if (GPR[RS] < 0)
|
||||
DELAY_SLOT (PC + offset);
|
||||
DELAY_SLOT (CIA + offset);
|
||||
else
|
||||
NULLIFY_NEXT_INSTRUCTION ();
|
||||
}
|
||||
@ -532,7 +531,7 @@
|
||||
/* NOTE: The branch occurs AFTER the next instruction has been
|
||||
executed */
|
||||
if (GPR[RS] < 0)
|
||||
DELAY_SLOT (PC + offset);
|
||||
DELAY_SLOT (CIA + offset);
|
||||
else
|
||||
NULLIFY_NEXT_INSTRUCTION ();
|
||||
}
|
||||
@ -557,7 +556,7 @@
|
||||
{
|
||||
address_word offset = EXTEND16 (OFFSET) << 2;
|
||||
if (GPR[RS] != GPR[RT])
|
||||
DELAY_SLOT (PC + offset);
|
||||
DELAY_SLOT (CIA + offset);
|
||||
}
|
||||
|
||||
|
||||
@ -579,7 +578,7 @@
|
||||
{
|
||||
address_word offset = EXTEND16 (OFFSET) << 2;
|
||||
if (GPR[RS] != GPR[RT])
|
||||
DELAY_SLOT (PC + offset);
|
||||
DELAY_SLOT (CIA + offset);
|
||||
else
|
||||
NULLIFY_NEXT_INSTRUCTION ();
|
||||
}
|
||||
@ -3554,7 +3553,7 @@
|
||||
int condition = (PREVCOC1() == boolean);
|
||||
/* NOTE: The branch occurs AFTER the next instruction has been executed */
|
||||
if (condition) {
|
||||
DELAY_SLOT (PC + offset);
|
||||
DELAY_SLOT (CIA + offset);
|
||||
}
|
||||
else if (likely) {
|
||||
NULLIFY_NEXT_INSTRUCTION ();
|
||||
|
||||
@ -22,8 +22,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
#define SIM_MAIN_H
|
||||
|
||||
/* This simulator doesn't cache the Current Instruction Address */
|
||||
#define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA)
|
||||
#define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA)
|
||||
/* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
|
||||
/* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
|
||||
|
||||
#define SIM_HAVE_BIENDIAN
|
||||
|
||||
@ -99,11 +99,11 @@ typedef enum {
|
||||
fmt_uninterpreted = 0x20000000,
|
||||
} FP_formats;
|
||||
|
||||
unsigned64 value_fpr PARAMS ((SIM_DESC sd, int fpr, FP_formats));
|
||||
#define ValueFPR(FPR,FMT) value_fpr (sd, (FPR), (FMT))
|
||||
unsigned64 value_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats));
|
||||
#define ValueFPR(FPR,FMT) value_fpr (sd, cia, (FPR), (FMT))
|
||||
|
||||
void store_fpr PARAMS ((SIM_DESC sd, int fpr, FP_formats fmt, unsigned64 value));
|
||||
#define StoreFPR(FPR,FMT,VALUE) store_fpr (sd, (FPR), (FMT), (VALUE))
|
||||
void store_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
|
||||
#define StoreFPR(FPR,FMT,VALUE) store_fpr (sd, cia, (FPR), (FMT), (VALUE))
|
||||
|
||||
int NaN PARAMS ((unsigned64 op, FP_formats fmt));
|
||||
int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
|
||||
@ -117,8 +117,8 @@ unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
|
||||
unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
|
||||
unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
|
||||
unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
|
||||
unsigned64 convert PARAMS ((SIM_DESC sd, int rm, unsigned64 op, FP_formats from, FP_formats to));
|
||||
#define Convert(rm,op,from,to) convert(sd,rm,op,from,to)
|
||||
unsigned64 convert PARAMS ((SIM_DESC sd, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
|
||||
#define Convert(rm,op,from,to) convert(sd,cia,rm,op,from,to)
|
||||
|
||||
/* Macro to update FPSR condition-code field. This is complicated by
|
||||
the fact that there is a hole in the index range of the bits within
|
||||
@ -295,7 +295,6 @@ struct _sim_cpu {
|
||||
|
||||
|
||||
/* The following are internal simulator state variables: */
|
||||
sim_cia cia;
|
||||
#define CPU_CIA(CPU) (PC)
|
||||
address_word ipc; /* internal Instruction PC */
|
||||
address_word dspc; /* delay-slot PC */
|
||||
@ -309,17 +308,17 @@ struct _sim_cpu {
|
||||
address_word target = (TARGET); \
|
||||
instruction_word delay_insn; \
|
||||
sim_events_slip (sd, 1); \
|
||||
PC = CIA + 4; \
|
||||
CIA = CIA + 4; \
|
||||
STATE |= simDELAYSLOT; \
|
||||
delay_insn = IMEM (PC); \
|
||||
idecode_issue (sd, delay_insn, (PC)); \
|
||||
STATE &= !simDELAYSLOT; \
|
||||
PC = target; \
|
||||
delay_insn = IMEM (CIA); \
|
||||
idecode_issue (sd, delay_insn, (CIA)); \
|
||||
STATE &= ~simDELAYSLOT; \
|
||||
NIA = target; \
|
||||
} while (0)
|
||||
#define NULLIFY_NEXT_INSTRUCTION() \
|
||||
do { \
|
||||
sim_events_slip (sd, 1); \
|
||||
NIA = CIA + 4; \
|
||||
NIA = CIA + 8; \
|
||||
} while (0)
|
||||
|
||||
|
||||
@ -629,32 +628,32 @@ struct sim_state {
|
||||
run-time errors in the simulator. */
|
||||
#define SimulatorFault (0xFFFFFFFF)
|
||||
|
||||
void signal_exception (SIM_DESC sd, int exception, ...);
|
||||
#define SignalException(exc,instruction) signal_exception (sd, (exc), (instruction))
|
||||
#define SignalExceptionInterrupt() signal_exception (sd, Interrupt)
|
||||
#define SignalExceptionInstructionFetch() signal_exception (sd, InstructionFetch)
|
||||
#define SignalExceptionAddressStore() signal_exception (sd, AddressStore)
|
||||
#define SignalExceptionAddressLoad() signal_exception (sd, AddressLoad)
|
||||
#define SignalExceptionSimulatorFault(buf) signal_exception (sd, SimulatorFault, buf)
|
||||
#define SignalExceptionFPE() signal_exception (sd, FPE)
|
||||
#define SignalExceptionIntegerOverflow() signal_exception (sd, IntegerOverflow)
|
||||
#define SignalExceptionCoProcessorUnusable() signal_exception (sd, CoProcessorUnusable)
|
||||
void signal_exception (SIM_DESC sd, address_word cia, int exception, ...);
|
||||
#define SignalException(exc,instruction) signal_exception (sd, cia, (exc), (instruction))
|
||||
#define SignalExceptionInterrupt() signal_exception (sd, NULL_CIA, Interrupt)
|
||||
#define SignalExceptionInstructionFetch() signal_exception (sd, cia, InstructionFetch)
|
||||
#define SignalExceptionAddressStore() signal_exception (sd, cia, AddressStore)
|
||||
#define SignalExceptionAddressLoad() signal_exception (sd, cia, AddressLoad)
|
||||
#define SignalExceptionSimulatorFault(buf) signal_exception (sd, cia, SimulatorFault, buf)
|
||||
#define SignalExceptionFPE() signal_exception (sd, cia, FPE)
|
||||
#define SignalExceptionIntegerOverflow() signal_exception (sd, cia, IntegerOverflow)
|
||||
#define SignalExceptionCoProcessorUnusable() signal_exception (sd, cia, CoProcessorUnusable)
|
||||
|
||||
|
||||
/* Co-processor accesses */
|
||||
|
||||
void cop_lw PARAMS ((SIM_DESC sd, int coproc_num, int coproc_reg, unsigned int memword));
|
||||
void cop_ld PARAMS ((SIM_DESC sd, int coproc_num, int coproc_reg, uword64 memword));
|
||||
unsigned int cop_sw PARAMS ((SIM_DESC sd, int coproc_num, int coproc_reg));
|
||||
uword64 cop_sd PARAMS ((SIM_DESC sd, int coproc_num, int coproc_reg));
|
||||
void cop_lw PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
|
||||
void cop_ld PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
|
||||
unsigned int cop_sw PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg));
|
||||
uword64 cop_sd PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg));
|
||||
|
||||
#define COP_LW(coproc_num,coproc_reg,memword) cop_lw(sd,coproc_num,coproc_reg,memword)
|
||||
#define COP_LD(coproc_num,coproc_reg,memword) cop_ld(sd,coproc_num,coproc_reg,memword)
|
||||
#define COP_SW(coproc_num,coproc_reg) cop_sw(sd,coproc_num,coproc_reg)
|
||||
#define COP_SD(coproc_num,coproc_reg) cop_sd(sd,coproc_num,coproc_reg)
|
||||
#define COP_LW(coproc_num,coproc_reg,memword) cop_lw(sd,cia,coproc_num,coproc_reg,memword)
|
||||
#define COP_LD(coproc_num,coproc_reg,memword) cop_ld(sd,cia,coproc_num,coproc_reg,memword)
|
||||
#define COP_SW(coproc_num,coproc_reg) cop_sw(sd,cia,coproc_num,coproc_reg)
|
||||
#define COP_SD(coproc_num,coproc_reg) cop_sd(sd,cia,coproc_num,coproc_reg)
|
||||
|
||||
void decode_coproc PARAMS ((SIM_DESC sd,unsigned int instruction));
|
||||
#define DecodeCoproc(instruction) decode_coproc(sd, (instruction))
|
||||
void decode_coproc PARAMS ((SIM_DESC sd, address_word cia, unsigned int instruction));
|
||||
#define DecodeCoproc(instruction) decode_coproc(sd, cia, (instruction))
|
||||
|
||||
|
||||
|
||||
@ -691,29 +690,29 @@ void decode_coproc PARAMS ((SIM_DESC sd,unsigned int instruction));
|
||||
#define AccessLength_DOUBLEWORD (7)
|
||||
#define AccessLength_QUADWORD (15)
|
||||
|
||||
int address_translation PARAMS ((SIM_DESC sd, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
|
||||
int address_translation PARAMS ((SIM_DESC sd, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
|
||||
#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
|
||||
address_translation(sd, vAddr,IorD,LorS,pAddr,CCA,raw)
|
||||
address_translation(sd,cia,vAddr,IorD,LorS,pAddr,CCA,raw)
|
||||
|
||||
void load_memory PARAMS ((SIM_DESC sd, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, address_word pAddr, address_word vAddr, int IorD));
|
||||
void load_memory PARAMS ((SIM_DESC sd, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, address_word pAddr, address_word vAddr, int IorD));
|
||||
#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
|
||||
load_memory(sd,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD)
|
||||
load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD)
|
||||
|
||||
void store_memory PARAMS ((SIM_DESC sd, int CCA, int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
|
||||
void store_memory PARAMS ((SIM_DESC sd, address_word cia, int CCA, int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
|
||||
#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
|
||||
store_memory(sd,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr)
|
||||
store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr)
|
||||
|
||||
void cache_op PARAMS ((SIM_DESC sd, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
|
||||
#define CacheOp(op,pAddr,vAddr,instruction) cache_op(sd,op,pAddr,vAddr,instruction)
|
||||
void cache_op PARAMS ((SIM_DESC sd, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
|
||||
#define CacheOp(op,pAddr,vAddr,instruction) cache_op(sd,cia,op,pAddr,vAddr,instruction)
|
||||
|
||||
void sync_operation PARAMS ((SIM_DESC sd, int stype));
|
||||
#define SyncOperation(stype) sync_operation (sd, (stype))
|
||||
void sync_operation PARAMS ((SIM_DESC sd, address_word cia, int stype));
|
||||
#define SyncOperation(stype) sync_operation (sd, cia, (stype))
|
||||
|
||||
void prefetch PARAMS ((SIM_DESC sd, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
|
||||
#define Prefetch(CCA,pAddr,vAddr,DATA,hint) prefetch(sd,CCA,pAddr,vAddr,DATA,hint)
|
||||
void prefetch PARAMS ((SIM_DESC sd, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
|
||||
#define Prefetch(CCA,pAddr,vAddr,DATA,hint) prefetch(sd,cia,CCA,pAddr,vAddr,DATA,hint)
|
||||
|
||||
unsigned32 ifetch32 PARAMS ((SIM_DESC sd, address_word cia));
|
||||
#define IMEM(CIA) ifetch32 (SD, (CIA))
|
||||
unsigned32 ifetch32 PARAMS ((SIM_DESC sd, address_word cia, address_word vaddr));
|
||||
#define IMEM(CIA) ifetch32 (SD, (CIA), (CIA))
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user