darlinghq/darling-gdb
1
0
Fork 0
mirror of https://github.com/darlinghq/darling-gdb.git synced 2025-02-13 13:35:56 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Support Intel MPX

Browse Source 
gas/

2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
	    Kirill Yukhin  <kirill.yukhin@intel.com>
	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

	* config/tc-i386.c (BND_PREFIX): New.
	(struct _i386_insn): Add new field bnd_prefix.
	(add_bnd_prefix): New.
	(cpu_arch): Add MPX.
	(i386_operand_type): Add regbnd.
	(md_assemble): Handle BND prefixes.
	(parse_insn): Likewise.
	(output_branch): Likewise.
	(output_jump): Likewise.
	(build_modrm_byte): Handle regbnd.
	(OPTION_MADD_BND_PREFIX): New.
	(md_longopts): Add entry for 'madd-bnd-prefix'.
	(md_parse_option): Handle madd-bnd-prefix option.
	(md_show_usage): Add description for madd-bnd-prefix
	option.
	* doc/c-i386.texi: Document mpx/.mpx and -madd-bnd-prefix.

gas/testsuite/

2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
	    Kirill Yukhin  <kirill.yukhin@intel.com>
	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

	* gas/i386/mpx-add-bnd-prefix.s: New.
	* gas/i386/mpx-add-bnd-prefix.d: New.
	* gas/i386/mpx-inval-1.l: New.
	* gas/i386/mpx-inval-1.s: New.
	* gas/i386/mpx.d: New.
	* gas/i386/mpx.s: New.
	* gas/i386/x86-64-mpx-add-bnd-prefix.d: New.
	* gas/i386/x86-64-mpx-add-bnd-prefix.s: New.
	* gas/i386/x86-64-mpx-addr32.d: New.
	* gas/i386/x86-64-mpx-addr32.s: New.
	* gas/i386/x86-64-mpx-inval-1.l: New.
	* gas/i386/x86-64-mpx-inval-1.s: New.
	* gas/i386/x86-64-mpx-inval-2.l: New.
	* gas/i386/x86-64-mpx-inval-2.s: New.
	* gas/i386/x86-64-mpx.d: New.
	* gas/i386/x86-64-mpx.s: New.
	* gas/i386/nops.d: Adjust to MPX changes.
	* gas/i386/nops.s: Likewise.
	* gas/i386/x86-64-nops.d: Likewise.
	* gas/i386/x86-64-nops.s: Likewise.
	* gas/i386/ilp32/x86-64-nops.d: Likewise.
	* gas/i386/i386.exp: Run new MPX tests.

include/opcode/

2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
	    Kirill Yukhin  <kirill.yukhin@intel.com>
	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

	* i386.h (BND_PREFIX_OPCODE): New.

opcodes/

2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
	    Kirill Yukhin  <kirill.yukhin@intel.com>
	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

	* i386-dis.c (BND_Fixup): New.
	(Ebnd): New.
	(Ev_bnd): New.
	(Gbnd): New.
	(BND): New.
	(v_bnd_mode): New.
	(bnd_mode): New.
	(MOD enum): Add new entries.
	(PREFIX enum): Likewise.
	(dis tables): Replace XX with BND for near branch and call
	instructions.
	(prefix_table): Add new entries.
	(mod_table): Likewise.
	(names_bnd): New.
	(intel_names_bnd): New.
	(att_names_bnd): New.
	(BND_PREFIX): New.
	(prefix_name): Handle BND_PREFIX.
	(print_insn): Initialize names_bnd.
	(intel_operand_size): Handle new modes.
	(OP_E_register): Likewise.
	(OP_E_memory): Likewise.
	(OP_G): Likewise.
	* i386-gen.c (cpu_flag_init): Add CpuMPX.
	(cpu_flags): Add CpuMPX.
	(operand_type_init): Add RegBND.
	(opcode_modifiers): Add BNDPrefixOk.
	(operand_types): Add RegBND.
	* i386-init.h: Regenerate.
	* i386-opc.h (CpuMPX): New.
	(CpuUnused): Comment out.
	(i386_cpu_flags): Add cpumpx.
	(BNDPrefixOk): New.
	(i386_opcode_modifier): Add bndprefixok.
	(RegBND): New.
	(i386_operand_type): Add regbnd.
	* i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
	Add MPX instructions and bnd prefix.
	* i386-reg.tbl: Add bnd0-bnd3 registers.
	* i386-tbl.h: Regenerate.
This commit is contained in:
H.J. Lu 2013-07-24 15:47:25 +00:00
parent 6656a72dcb
commit 7e8b059be6
36 changed files with 11851 additions and 10228 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
gas/ChangeLog
View File

@ -1,3 +1,24 @@
2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/tc-i386.c (BND_PREFIX): New.
(struct _i386_insn): Add new field bnd_prefix.
(add_bnd_prefix): New.
(cpu_arch): Add MPX.
(i386_operand_type): Add regbnd.
(md_assemble): Handle BND prefixes.
(parse_insn): Likewise.
(output_branch): Likewise.
(output_jump): Likewise.
(build_modrm_byte): Handle regbnd.
(OPTION_MADD_BND_PREFIX): New.
(md_longopts): Add entry for 'madd-bnd-prefix'.
(md_parse_option): Handle madd-bnd-prefix option.
(md_show_usage): Add description for madd-bnd-prefix
option.
* doc/c-i386.texi: Document mpx/.mpx and -madd-bnd-prefix.
2013-07-24 Tristan Gingold <gingold@adacore.com>
* config/tc-ppc.c (md_apply_fix): Adjust BFD_RELOC_PPC_B16 on

52
gas/config/tc-i386.c
View File

@ -67,6 +67,7 @@
#define DATA_PREFIX 3
#define REP_PREFIX 4
#define HLE_PREFIX REP_PREFIX
#define BND_PREFIX REP_PREFIX
#define LOCK_PREFIX 5
#define REX_PREFIX 6 /* must come last. */
#define MAX_PREFIXES 7 /* max prefixes per opcode */
@ -296,6 +297,9 @@ struct _i386_insn
/* HLE prefix. */
const char *hle_prefix;
/* Have BND prefix. */
const char *bnd_prefix;
/* Error message. */
enum i386_error error;
};
@ -442,6 +446,11 @@ static int allow_pseudo_reg = 0;
/* 1 if register prefix % not required. */
static int allow_naked_reg = 0;
/* 1 if the assembler should add BND prefix for all control-tranferring
instructions supporting it, even if this prefix wasn't specified
explicitly. */
static int add_bnd_prefix = 0;
/* 1 if pseudo index register, eiz/riz, is allowed . */
static int allow_index_reg = 0;
@ -779,6 +788,8 @@ static const arch_entry cpu_arch[] =
CPU_PRFCHW_FLAGS, 0, 0 },
{ STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
CPU_SMAP_FLAGS, 0, 0 },
{ STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
CPU_MPX_FLAGS, 0, 0 },
};
#ifdef I386COFF
@ -1540,6 +1551,7 @@ static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
static const i386_operand_type regbnd = OPERAND_TYPE_REGBND;
enum operand_type
{
@ -3214,6 +3226,21 @@ md_assemble (char *line)
if (i.hle_prefix && !check_hle ())
return;
/* Check BND prefix. */
if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
as_bad (_("expecting valid branch instruction after `bnd'"));
if (i.tm.cpu_flags.bitfield.cpumpx
&& flag_code == CODE_64BIT
&& i.prefix[ADDR_PREFIX])
as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
/* Insert BND prefix. */
if (add_bnd_prefix
&& i.tm.opcode_modifier.bndprefixok
&& !i.prefix[BND_PREFIX])
add_prefix (BND_PREFIX_OPCODE);
/* Check string instruction segment overrides. */
if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
{
@ -3416,6 +3443,8 @@ parse_insn (char *line, char *mnemonic)
case PREFIX_REP:
if (current_templates->start->cpu_flags.bitfield.cpuhle)
i.hle_prefix = current_templates->start->name;
else if (current_templates->start->cpu_flags.bitfield.cpumpx)
i.bnd_prefix = current_templates->start->name;
else
i.rep_prefix = current_templates->start->name;
break;
@ -5892,6 +5921,7 @@ build_modrm_byte (void)
|| i.types[op].bitfield.regmmx
|| i.types[op].bitfield.regxmm
|| i.types[op].bitfield.regymm
|| i.types[op].bitfield.regbnd
|| i.types[op].bitfield.sreg2
|| i.types[op].bitfield.sreg3
|| i.types[op].bitfield.control
@ -6031,6 +6061,13 @@ output_branch (void)
i.prefixes--;
}
/* BND prefixed jump. */
if (i.prefix[BND_PREFIX] != 0)
{
FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
i.prefixes -= 1;
}
if (i.prefixes != 0 && !intel_syntax)
as_warn (_("skipping prefixes on this instruction"));
@ -6125,6 +6162,13 @@ output_jump (void)
i.prefixes -= 1;
}
/* BND prefixed jump. */
if (i.prefix[BND_PREFIX] != 0)
{
FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
i.prefixes -= 1;
}
if (i.prefixes != 0 && !intel_syntax)
as_warn (_("skipping prefixes on this instruction"));
@ -8536,6 +8580,7 @@ const char *md_shortopts = "qn";
#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
#define OPTION_X32 (OPTION_MD_BASE + 14)
#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
struct option md_longopts[] =
{
@ -8559,6 +8604,7 @@ struct option md_longopts[] =
{"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
{"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
{"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
{"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
{NULL, no_argument, NULL, 0}
};
size_t md_longopts_size = sizeof (md_longopts);
@ -8816,6 +8862,10 @@ md_parse_option (int c, char *arg)
as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
break;
case OPTION_MADD_BND_PREFIX:
add_bnd_prefix = 1;
break;
default:
return 0;
}
@ -8960,6 +9010,8 @@ md_show_usage (FILE *stream)
-mnaked-reg don't require `%%' prefix for registers\n"));
fprintf (stream, _("\
-mold-gcc support old (<= 2.8.1) versions of gcc\n"));
fprintf (stream, _("\
-madd-bnd-prefix add BND prefix for all valid branches\n"));
}
#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \

9
gas/doc/c-i386.texi
View File

@ -150,6 +150,7 @@ accept various extension mnemonics. For example,
@code{rdseed},
@code{prfchw},
@code{smap},
@code{mpx},
@code{noavx},
@code{vmx},
@code{vmfunc},
@ -250,6 +251,12 @@ take precedent.
This opetion specifies that registers don't require a @samp{%} prefix.
The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
@cindex @samp{-madd-bnd-prefix} option, i386
@cindex @samp{-madd-bnd-prefix} option, x86-64
@item -madd-bnd-prefix
This option forces the assembler to add BND prefix to all branches, even
if such prefix was not explicitly specified in the source code.
@end table
@c man end
@ -1028,7 +1035,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
@item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
@item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
@item @samp{.smap}
@item @samp{.smap} @tab @samp{.mpx}
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}

27
gas/testsuite/ChangeLog
View File

@ -1,3 +1,30 @@
2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* gas/i386/mpx-add-bnd-prefix.s: New.
* gas/i386/mpx-add-bnd-prefix.d: New.
* gas/i386/mpx-inval-1.l: New.
* gas/i386/mpx-inval-1.s: New.
* gas/i386/mpx.d: New.
* gas/i386/mpx.s: New.
* gas/i386/x86-64-mpx-add-bnd-prefix.d: New.
* gas/i386/x86-64-mpx-add-bnd-prefix.s: New.
* gas/i386/x86-64-mpx-addr32.d: New.
* gas/i386/x86-64-mpx-addr32.s: New.
* gas/i386/x86-64-mpx-inval-1.l: New.
* gas/i386/x86-64-mpx-inval-1.s: New.
* gas/i386/x86-64-mpx-inval-2.l: New.
* gas/i386/x86-64-mpx-inval-2.s: New.
* gas/i386/x86-64-mpx.d: New.
* gas/i386/x86-64-mpx.s: New.
* gas/i386/nops.d: Adjust to MPX changes.
* gas/i386/nops.s: Likewise.
* gas/i386/x86-64-nops.d: Likewise.
* gas/i386/x86-64-nops.s: Likewise.
* gas/i386/ilp32/x86-64-nops.d: Likewise.
* gas/i386/i386.exp: Run new MPX tests.
2013-07-24 Tristan Gingold <gingold@adacore.com>
* gas/ppc/test2xcoff32.s, gas/ppc/test2xcoff32.d: New files

8
gas/testsuite/gas/i386/i386.exp
View File

@ -245,6 +245,9 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "prefetch"
run_dump_test "prefetch-intel"
run_dump_test "smap"
run_dump_test "mpx"
run_list_test "mpx-inval-1" "-al"
run_dump_test "mpx-add-bnd-prefix"
# These tests require support for 8 and 16 bit relocs,
# so we only run them for ELF and COFF targets.
@ -506,6 +509,11 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-prefetch"
run_dump_test "x86-64-prefetch-intel"
run_dump_test "x86-64-smap"
run_dump_test "x86-64-mpx"
run_list_test "x86-64-mpx-inval-1" "-al"
run_list_test "x86-64-mpx-inval-2" "-al"
run_dump_test "x86-64-mpx-addr32"
run_dump_test "x86-64-mpx-add-bnd-prefix"
if { ![istarget "*-*-aix*"]
&& ![istarget "*-*-beos*"]

8
gas/testsuite/gas/i386/ilp32/x86-64-nops.d
View File

@ -23,29 +23,21 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 1e ff nop %edi
[ ]*[a-f0-9]+: 0f 1f ff nop %edi
[ ]*[a-f0-9]+: 0f 19 5a 22 nopl 0x22\(%rdx\)
[ ]*[a-f0-9]+: 0f 1a 5a 22 nopl 0x22\(%rdx\)
[ ]*[a-f0-9]+: 0f 1b 5a 22 nopl 0x22\(%rdx\)
[ ]*[a-f0-9]+: 0f 1c 5a 22 nopl 0x22\(%rdx\)
[ ]*[a-f0-9]+: 0f 1d 5a 22 nopl 0x22\(%rdx\)
[ ]*[a-f0-9]+: 0f 1e 5a 22 nopl 0x22\(%rdx\)
[ ]*[a-f0-9]+: 0f 1f 5a 22 nopl 0x22\(%rdx\)
[ ]*[a-f0-9]+: 0f 19 9c 1d 11 22 33 44 nopl 0x44332211\(%rbp,%rbx,1\)
[ ]*[a-f0-9]+: 0f 1a 9c 1d 11 22 33 44 nopl 0x44332211\(%rbp,%rbx,1\)
[ ]*[a-f0-9]+: 0f 1b 9c 1d 11 22 33 44 nopl 0x44332211\(%rbp,%rbx,1\)
[ ]*[a-f0-9]+: 0f 1c 9c 1d 11 22 33 44 nopl 0x44332211\(%rbp,%rbx,1\)
[ ]*[a-f0-9]+: 0f 1d 9c 1d 11 22 33 44 nopl 0x44332211\(%rbp,%rbx,1\)
[ ]*[a-f0-9]+: 0f 1e 9c 1d 11 22 33 44 nopl 0x44332211\(%rbp,%rbx,1\)
[ ]*[a-f0-9]+: 0f 1f 9c 1d 11 22 33 44 nopl 0x44332211\(%rbp,%rbx,1\)
[ ]*[a-f0-9]+: 0f 19 04 60 nopl \(%rax,%riz,2\)
[ ]*[a-f0-9]+: 0f 1a 04 60 nopl \(%rax,%riz,2\)
[ ]*[a-f0-9]+: 0f 1b 04 60 nopl \(%rax,%riz,2\)
[ ]*[a-f0-9]+: 0f 1c 04 60 nopl \(%rax,%riz,2\)
[ ]*[a-f0-9]+: 0f 1d 04 60 nopl \(%rax,%riz,2\)
[ ]*[a-f0-9]+: 0f 1e 04 60 nopl \(%rax,%riz,2\)
[ ]*[a-f0-9]+: 0f 1f 04 60 nopl \(%rax,%riz,2\)
[ ]*[a-f0-9]+: 0f 19 04 59 nopl \(%rcx,%rbx,2\)
[ ]*[a-f0-9]+: 0f 1a 04 59 nopl \(%rcx,%rbx,2\)
[ ]*[a-f0-9]+: 0f 1b 04 59 nopl \(%rcx,%rbx,2\)
[ ]*[a-f0-9]+: 0f 1c 04 59 nopl \(%rcx,%rbx,2\)
[ ]*[a-f0-9]+: 0f 1d 04 59 nopl \(%rcx,%rbx,2\)
[ ]*[a-f0-9]+: 0f 1e 04 59 nopl \(%rcx,%rbx,2\)

24
gas/testsuite/gas/i386/mpx-add-bnd-prefix.d Normal file
View File

@ -0,0 +1,24 @@
#as: -madd-bnd-prefix
#objdump: -drw
#name: Check -madd-bnd-prefix
.*: +file format .*
Disassembly of section .text:
0+ <foo-0x14>:
[ ]*[a-f0-9]+: f2 e8 0e 00 00 00 bnd call 14 <foo>
[ ]*[a-f0-9]+: f2 ff 10 bnd call \*\(%eax\)
[ ]*[a-f0-9]+: f2 74 08 bnd je 14 <foo>
[ ]*[a-f0-9]+: f2 eb 05 bnd jmp 14 <foo>
[ ]*[a-f0-9]+: f2 ff 23 bnd jmp \*\(%ebx\)
[ ]*[a-f0-9]+: f2 c3 bnd ret
0+14 <foo>:
[ ]*[a-f0-9]+: f2 c3 bnd ret
[ ]*[a-f0-9]+: f2 c3 bnd ret
[ ]*[a-f0-9]+: f2 e8 f6 ff ff ff bnd call 14 <foo>
[ ]*[a-f0-9]+: 01 c3 add %eax,%ebx
[ ]*[a-f0-9]+: e2 f2 loop 14 <foo>
#pass

19
gas/testsuite/gas/i386/mpx-add-bnd-prefix.s Normal file
View File

@ -0,0 +1,19 @@
# Check -madd-bnd-prefix option
.text
call foo
call *(%eax)
je foo
jmp foo
jmp *(%ebx)
ret
foo:
# Use of REPNE prefix - we shouldn't get any error
repne ret
# BND prefix already exists - we shouldn't get any error here
bnd ret
bnd call foo
# Following instructions can't have BND prefix even if
# -madd-bnd-prefix is specified
add %eax, %ebx
loop foo

55
gas/testsuite/gas/i386/mpx-inval-1.l Normal file
View File

@ -0,0 +1,55 @@
.*: Assembler messages:
.*:6: Error: expecting valid branch instruction after `bnd'
.*:7: Error: expecting valid branch instruction after `bnd'
.*:8: Error: expecting valid branch instruction after `bnd'
.*:8: Warning: skipping prefixes on this instruction
.*:9: Error: expecting valid branch instruction after `bnd'
.*:9: Warning: skipping prefixes on this instruction
.*:10: Error: expecting valid branch instruction after `bnd'
.*:11: Error: expecting valid branch instruction after `bnd'
.*:14: Error: expecting valid branch instruction after `bnd'
.*:15: Error: expecting valid branch instruction after `bnd'
.*:16: Error: expecting valid branch instruction after `bnd'
.*:17: Error: expecting valid branch instruction after `bnd'
.*:18: Error: expecting valid branch instruction after `bnd'
.*:19: Error: expecting valid branch instruction after `bnd'
GAS LISTING .*
[ ]*1[ ]+\# MPX instructions
[ ]*2[ ]+\.allow_index_reg
[ ]*3[ ]+\.text
[ ]*4[ ]+\.extern xxx
[ ]*5[ ]+foo:
[ ]*6[ ]+\?\?\?\? F201C3 bnd add %eax, %ebx \# Bad
\*\*\*\* Error:expecting valid branch instruction after `bnd'
[ ]*7[ ]+\?\?\?\? 66F2AB bnd stosw \(%edi\) \# Bad
\*\*\*\* Error:expecting valid branch instruction after `bnd'
[ ]*8[ ]+\?\?\?\? 9A000000 bnd lcall \$0x1234,\$xxx
\*\*\*\* Error:expecting valid branch instruction after `bnd'
\*\*\*\* Warning:skipping prefixes on this instruction
[ ]*8[ ]+003412
[ ]*9[ ]+\?\?\?\? EA000000 bnd ljmp \$0x1234,\$xxx
\*\*\*\* Error:expecting valid branch instruction after `bnd'
\*\*\*\* Warning:skipping prefixes on this instruction
[ ]*9[ ]+003412
[ ]*10[ ]+\?\?\?\? F2E200 bnd loop foo
\*\*\*\* Error:expecting valid branch instruction after `bnd'
[ ]*11[ ]+\?\?\?\? 67F2E300 bnd jcxz foo
\*\*\*\* Error:expecting valid branch instruction after `bnd'
[ ]*12[ ]+
[ ]*13[ ]+\.intel_syntax noprefix
[ ]*14[ ]+\?\?\?\? F201C3 bnd add ebx, eax \# Bad
\*\*\*\* Error:expecting valid branch instruction after `bnd'
[ ]*15[ ]+\?\?\?\? 66F2AB bnd stos WORD PTR\[edi] \# Bad
\*\*\*\* Error:expecting valid branch instruction after `bnd'
[ ]*16[ ]+\?\?\?\? 9A000000 bnd lcall 0x1234,xxx
\*\*\*\* Error:expecting valid branch instruction after `bnd'
[ ]*16[ ]+003412
[ ]*17[ ]+\?\?\?\? EA000000 bnd ljmp 0x1234,xxx
\*\*\*\* Error:expecting valid branch instruction after `bnd'
[ ]*17[ ]+003412
[ ]*18[ ]+\?\?\?\? F2E200 bnd loop foo
\*\*\*\* Error:expecting valid branch instruction after `bnd'
[ ]*19[ ]+\?\?\?\? 67F2E300 bnd jcxz foo
\*\*\*\* Error:expecting valid branch instruction after `bnd'

19
gas/testsuite/gas/i386/mpx-inval-1.s Normal file
View File

@ -0,0 +1,19 @@
# MPX instructions
.allow_index_reg
.text
.extern xxx
foo:
bnd add %eax, %ebx # Bad
bnd stosw (%edi) # Bad
bnd lcall $0x1234,$xxx
bnd ljmp $0x1234,$xxx
bnd loop foo
bnd jcxz foo
.intel_syntax noprefix
bnd add ebx, eax # Bad
bnd stos WORD PTR[edi] # Bad
bnd lcall 0x1234,xxx
bnd ljmp 0x1234,xxx
bnd loop foo
bnd jcxz foo

139
gas/testsuite/gas/i386/mpx.d Normal file
View File

@ -0,0 +1,139 @@
#objdump: -drw
#name: i386 MPX
.*: +file format .*
Disassembly of section .text:
0+ <foo-0x2c1>:
[ ]*[a-f0-9]+: f3 0f 1b 08 bndmk \(%eax\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 0d 99 03 00 00 bndmk 0x399,%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 4a 03 bndmk 0x3\(%edx\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 0c 08 bndmk \(%eax,%ecx,1\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 0c 0d 00 00 00 00 bndmk 0x0\(,%ecx,1\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 4c 01 03 bndmk 0x3\(%ecx,%eax,1\),%bnd1
[ ]*[a-f0-9]+: 66 0f 1a 08 bndmov \(%eax\),%bnd1
[ ]*[a-f0-9]+: 66 0f 1a 0d 99 03 00 00 bndmov 0x399,%bnd1
[ ]*[a-f0-9]+: 66 0f 1a 52 03 bndmov 0x3\(%edx\),%bnd2
[ ]*[a-f0-9]+: 66 0f 1a 14 10 bndmov \(%eax,%edx,1\),%bnd2
[ ]*[a-f0-9]+: 66 0f 1a 14 05 00 00 00 00 bndmov 0x0\(,%eax,1\),%bnd2
[ ]*[a-f0-9]+: 66 0f 1a 4c 01 03 bndmov 0x3\(%ecx,%eax,1\),%bnd1
[ ]*[a-f0-9]+: 66 0f 1a c2 bndmov %bnd2,%bnd0
[ ]*[a-f0-9]+: 66 0f 1b 08 bndmov %bnd1,\(%eax\)
[ ]*[a-f0-9]+: 66 0f 1b 0d 99 03 00 00 bndmov %bnd1,0x399
[ ]*[a-f0-9]+: 66 0f 1b 52 03 bndmov %bnd2,0x3\(%edx\)
[ ]*[a-f0-9]+: 66 0f 1b 14 10 bndmov %bnd2,\(%eax,%edx,1\)
[ ]*[a-f0-9]+: 66 0f 1b 14 05 00 00 00 00 bndmov %bnd2,0x0\(,%eax,1\)
[ ]*[a-f0-9]+: 66 0f 1b 4c 01 03 bndmov %bnd1,0x3\(%ecx,%eax,1\)
[ ]*[a-f0-9]+: 66 0f 1a d0 bndmov %bnd0,%bnd2
[ ]*[a-f0-9]+: f3 0f 1a 09 bndcl \(%ecx\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a c9 bndcl %ecx,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a c8 bndcl %eax,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0d 99 03 00 00 bndcl 0x399,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 4a 03 bndcl 0x3\(%edx\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0c 08 bndcl \(%eax,%ecx,1\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0c 0d 00 00 00 00 bndcl 0x0\(,%ecx,1\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 4c 01 03 bndcl 0x3\(%ecx,%eax,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 09 bndcu \(%ecx\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a c9 bndcu %ecx,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a c8 bndcu %eax,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0d 99 03 00 00 bndcu 0x399,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 4a 03 bndcu 0x3\(%edx\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0c 08 bndcu \(%eax,%ecx,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0c 0d 00 00 00 00 bndcu 0x0\(,%ecx,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 4c 01 03 bndcu 0x3\(%ecx,%eax,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 09 bndcn \(%ecx\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b c9 bndcn %ecx,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b c8 bndcn %eax,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0d 99 03 00 00 bndcn 0x399,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 4a 03 bndcn 0x3\(%edx\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0c 08 bndcn \(%eax,%ecx,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0c 0d 00 00 00 00 bndcn 0x0\(,%ecx,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 4c 01 03 bndcn 0x3\(%ecx,%eax,1\),%bnd1
[ ]*[a-f0-9]+: 0f 1b 44 18 03 bndstx %bnd0,0x3\(%eax,%ebx,1\)
[ ]*[a-f0-9]+: 0f 1b 54 13 03 bndstx %bnd2,0x3\(%ebx,%edx,1\)
[ ]*[a-f0-9]+: 0f 1b 14 15 03 00 00 00 bndstx %bnd2,0x3\(,%edx,1\)
[ ]*[a-f0-9]+: 0f 1b 9a 99 03 00 00 bndstx %bnd3,0x399\(%edx\)
[ ]*[a-f0-9]+: 0f 1b 93 34 12 00 00 bndstx %bnd2,0x1234\(%ebx\)
[ ]*[a-f0-9]+: 0f 1b 53 03 bndstx %bnd2,0x3\(%ebx\)
[ ]*[a-f0-9]+: 0f 1b 0a bndstx %bnd1,\(%edx\)
[ ]*[a-f0-9]+: 0f 1a 44 18 03 bndldx 0x3\(%eax,%ebx,1\),%bnd0
[ ]*[a-f0-9]+: 0f 1a 54 13 03 bndldx 0x3\(%ebx,%edx,1\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 14 15 03 00 00 00 bndldx 0x3\(,%edx,1\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 9a 99 03 00 00 bndldx 0x399\(%edx\),%bnd3
[ ]*[a-f0-9]+: 0f 1a 93 34 12 00 00 bndldx 0x1234\(%ebx\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 53 03 bndldx 0x3\(%ebx\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%edx\),%bnd1
[ ]*[a-f0-9]+: f2 e8 6f 01 00 00 bnd call 2c1 <foo>
[ ]*[a-f0-9]+: f2 ff 10 bnd call \*\(%eax\)
[ ]*[a-f0-9]+: f2 0f 84 65 01 00 00 bnd je 2c1 <foo>
[ ]*[a-f0-9]+: f2 e9 5f 01 00 00 bnd jmp 2c1 <foo>
[ ]*[a-f0-9]+: f2 ff 21 bnd jmp \*\(%ecx\)
[ ]*[a-f0-9]+: f2 c3 bnd ret
[ ]*[a-f0-9]+: f3 0f 1b 08 bndmk \(%eax\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 0d 99 03 00 00 bndmk 0x399,%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 49 03 bndmk 0x3\(%ecx\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 0c 08 bndmk \(%eax,%ecx,1\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 0c 0d 00 00 00 00 bndmk 0x0\(,%ecx,1\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 4c 02 03 bndmk 0x3\(%edx,%eax,1\),%bnd1
[ ]*[a-f0-9]+: 66 0f 1a 08 bndmov \(%eax\),%bnd1
[ ]*[a-f0-9]+: 66 0f 1a 0d 99 03 00 00 bndmov 0x399,%bnd1
[ ]*[a-f0-9]+: 66 0f 1a 49 03 bndmov 0x3\(%ecx\),%bnd1
[ ]*[a-f0-9]+: 66 0f 1a 0c 08 bndmov \(%eax,%ecx,1\),%bnd1
[ ]*[a-f0-9]+: 66 0f 1a 0c 0d 00 00 00 00 bndmov 0x0\(,%ecx,1\),%bnd1
[ ]*[a-f0-9]+: 66 0f 1a 4c 02 03 bndmov 0x3\(%edx,%eax,1\),%bnd1
[ ]*[a-f0-9]+: 66 0f 1a c1 bndmov %bnd1,%bnd0
[ ]*[a-f0-9]+: 66 0f 1b 08 bndmov %bnd1,\(%eax\)
[ ]*[a-f0-9]+: 66 0f 1b 0d 99 03 00 00 bndmov %bnd1,0x399
[ ]*[a-f0-9]+: 66 0f 1b 49 03 bndmov %bnd1,0x3\(%ecx\)
[ ]*[a-f0-9]+: 66 0f 1b 0c 08 bndmov %bnd1,\(%eax,%ecx,1\)
[ ]*[a-f0-9]+: 66 0f 1b 0c 0d 00 00 00 00 bndmov %bnd1,0x0\(,%ecx,1\)
[ ]*[a-f0-9]+: 66 0f 1b 4c 02 03 bndmov %bnd1,0x3\(%edx,%eax,1\)
[ ]*[a-f0-9]+: 66 0f 1a c8 bndmov %bnd0,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 08 bndcl \(%eax\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a c9 bndcl %ecx,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a c8 bndcl %eax,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0d 99 03 00 00 bndcl 0x399,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 49 03 bndcl 0x3\(%ecx\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0c 08 bndcl \(%eax,%ecx,1\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0c 0d 00 00 00 00 bndcl 0x0\(,%ecx,1\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 4c 02 03 bndcl 0x3\(%edx,%eax,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 08 bndcu \(%eax\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a c9 bndcu %ecx,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a c8 bndcu %eax,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0d 99 03 00 00 bndcu 0x399,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 49 03 bndcu 0x3\(%ecx\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0c 08 bndcu \(%eax,%ecx,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0c 0d 00 00 00 00 bndcu 0x0\(,%ecx,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 4c 02 03 bndcu 0x3\(%edx,%eax,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 08 bndcn \(%eax\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b c9 bndcn %ecx,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b c8 bndcn %eax,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0d 99 03 00 00 bndcn 0x399,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 49 03 bndcn 0x3\(%ecx\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0c 08 bndcn \(%eax,%ecx,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0c 0d 00 00 00 00 bndcn 0x0\(,%ecx,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 4c 02 03 bndcn 0x3\(%edx,%eax,1\),%bnd1
[ ]*[a-f0-9]+: 0f 1b 44 18 03 bndstx %bnd0,0x3\(%eax,%ebx,1\)
[ ]*[a-f0-9]+: 0f 1b 54 13 03 bndstx %bnd2,0x3\(%ebx,%edx,1\)
[ ]*[a-f0-9]+: 0f 1b 14 0d 00 00 00 00 bndstx %bnd2,0x0\(,%ecx,1\)
[ ]*[a-f0-9]+: 0f 1b 9a 99 03 00 00 bndstx %bnd3,0x399\(%edx\)
[ ]*[a-f0-9]+: 0f 1b 14 1d 03 00 00 00 bndstx %bnd2,0x3\(,%ebx,1\)
[ ]*[a-f0-9]+: 0f 1b 0a bndstx %bnd1,\(%edx\)
[ ]*[a-f0-9]+: 0f 1a 44 18 03 bndldx 0x3\(%eax,%ebx,1\),%bnd0
[ ]*[a-f0-9]+: 0f 1a 54 13 03 bndldx 0x3\(%ebx,%edx,1\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 14 0d 00 00 00 00 bndldx 0x0\(,%ecx,1\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 9a 99 03 00 00 bndldx 0x399\(%edx\),%bnd3
[ ]*[a-f0-9]+: 0f 1a 14 1d 03 00 00 00 bndldx 0x3\(,%ebx,1\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%edx\),%bnd1
[ ]*[a-f0-9]+: f2 e8 0e 00 00 00 bnd call 2c1 <foo>
[ ]*[a-f0-9]+: f2 ff d0 bnd call \*%eax
[ ]*[a-f0-9]+: f2 74 08 bnd je 2c1 <foo>
[ ]*[a-f0-9]+: f2 eb 05 bnd jmp 2c1 <foo>
[ ]*[a-f0-9]+: f2 ff e1 bnd jmp \*%ecx
[ ]*[a-f0-9]+: f2 c3 bnd ret
0+2c1 <foo>:
[ ]*[a-f0-9]+: f2 c3 bnd ret
#pass

165
gas/testsuite/gas/i386/mpx.s Normal file
View File

@ -0,0 +1,165 @@
# MPX instructions
.allow_index_reg
.text
### bndmk
bndmk (%eax), %bnd1
bndmk (0x399), %bnd1
bndmk 0x3(%edx), %bnd1
bndmk (%eax,%ecx), %bnd1
bndmk (,%ecx,1), %bnd1
bndmk 0x3(%ecx,%eax,1), %bnd1
### bndmov
bndmov (%eax), %bnd1
bndmov (0x399), %bnd1
bndmov 0x3(%edx), %bnd2
bndmov (%eax,%edx), %bnd2
bndmov (,%eax,1), %bnd2
bndmov 0x3(%ecx,%eax,1), %bnd1
bndmov %bnd2, %bnd0
bndmov %bnd1, (%eax)
bndmov %bnd1, (0x399)
bndmov %bnd2, 0x3(%edx)
bndmov %bnd2, (%eax,%edx)
bndmov %bnd2, (,%eax,1)
bndmov %bnd1, 0x3(%ecx,%eax,1)
bndmov %bnd0, %bnd2
### bndcl
bndcl (%ecx), %bnd1
bndcl %ecx, %bnd1
bndcl %ax, %bnd1
bndcl (0x399), %bnd1
bndcl 0x3(%edx), %bnd1
bndcl (%eax,%ecx), %bnd1
bndcl (,%ecx,1), %bnd1
bndcl 0x3(%ecx,%eax,1), %bnd1
### bndcu
bndcu (%ecx), %bnd1
bndcu %ecx, %bnd1
bndcu %ax, %bnd1
bndcu (0x399), %bnd1
bndcu 0x3(%edx), %bnd1
bndcu (%eax,%ecx), %bnd1
bndcu (,%ecx,1), %bnd1
bndcu 0x3(%ecx,%eax,1), %bnd1
### bndcn
bndcn (%ecx), %bnd1
bndcn %ecx, %bnd1
bndcn %ax, %bnd1
bndcn (0x399), %bnd1
bndcn 0x3(%edx), %bnd1
bndcn (%eax,%ecx), %bnd1
bndcn (,%ecx,1), %bnd1
bndcn 0x3(%ecx,%eax,1), %bnd1
### bndstx
bndstx %bnd0, 0x3(%eax,%ebx,1)
bndstx %bnd2, 3(%ebx,%edx)
bndstx %bnd2, 3(,%edx,1)
bndstx %bnd3, 0x399(%edx)
bndstx %bnd2, 0x1234(%ebx)
bndstx %bnd2, 3(%ebx,1)
bndstx %bnd1, (%edx)
### bndldx
bndldx 0x3(%eax,%ebx,1), %bnd0
bndldx 3(%ebx,%edx), %bnd2
bndldx 3(,%edx,1), %bnd2
bndldx 0x399(%edx), %bnd3
bndldx 0x1234(%ebx), %bnd2
bndldx 3(%ebx,1), %bnd2
bndldx (%edx), %bnd1
### bnd
bnd call foo
bnd call *(%eax)
bnd je foo
bnd jmp foo
bnd jmp *(%ecx)
bnd ret
.intel_syntax noprefix
bndmk bnd1, [eax]
bndmk bnd1, [0x399]
bndmk bnd1, [ecx+0x3]
bndmk bnd1, [eax+ecx]
bndmk bnd1, [ecx*1]
bndmk bnd1, [edx+1*eax+0x3]
### bndmov
bndmov bnd1, [eax]
bndmov bnd1, [0x399]
bndmov bnd1, [ecx+0x3]
bndmov bnd1, [eax+ecx]
bndmov bnd1, [ecx*1]
bndmov bnd1, [edx+1*eax+0x3]
bndmov bnd0, bnd1
bndmov [eax], bnd1
bndmov [0x399], bnd1
bndmov [ecx+0x3], bnd1
bndmov [eax+ecx], bnd1
bndmov [ecx*1], bnd1
bndmov [edx+1*eax+0x3], bnd1
bndmov bnd1, bnd0
### bndcl
bndcl bnd1, [eax]
bndcl bnd1, ecx
bndcl bnd1, ax
bndcl bnd1, [0x399]
bndcl bnd1, [ecx+0x3]
bndcl bnd1, [eax+ecx]
bndcl bnd1, [ecx*1]
bndcl bnd1, [edx+1*eax+0x3]
### bndcu
bndcu bnd1, [eax]
bndcu bnd1, ecx
bndcu bnd1, ax
bndcu bnd1, [0x399]
bndcu bnd1, [ecx+0x3]
bndcu bnd1, [eax+ecx]
bndcu bnd1, [ecx*1]
bndcu bnd1, [edx+1*eax+0x3]
### bndcn
bndcn bnd1, [eax]
bndcn bnd1, ecx
bndcn bnd1, ax
bndcn bnd1, [0x399]
bndcn bnd1, [ecx+0x3]
bndcn bnd1, [eax+ecx]
bndcn bnd1, [ecx*1]
bndcn bnd1, [edx+1*eax+0x3]
### bndstx
bndstx [eax+ebx*1+0x3], bnd0
bndstx [ebx+edx+3], bnd2
bndstx [ecx*1], bnd2
bndstx [edx+0x399], bnd3
bndstx [1*ebx+3], bnd2
bndstx [edx], bnd1
### bndldx
bndldx bnd0, [eax+ebx*1+0x3]
bndldx bnd2, [ebx+edx+3]
bndldx bnd2, [ecx*1]
bndldx bnd3, [edx+0x399]
bndldx bnd2, [1*ebx+3]
bndldx bnd1, [edx]
### bnd
bnd call foo
bnd call eax
bnd je foo
bnd jmp foo
bnd jmp ecx
bnd ret
foo: bnd ret

8
gas/testsuite/gas/i386/nops.d
View File

@ -22,29 +22,21 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 1e ff nop %edi
[ ]*[a-f0-9]+: 0f 1f ff nop %edi
[ ]*[a-f0-9]+: 0f 19 5a 22 nopl 0x22\(%edx\)
[ ]*[a-f0-9]+: 0f 1a 5a 22 nopl 0x22\(%edx\)
[ ]*[a-f0-9]+: 0f 1b 5a 22 nopl 0x22\(%edx\)
[ ]*[a-f0-9]+: 0f 1c 5a 22 nopl 0x22\(%edx\)
[ ]*[a-f0-9]+: 0f 1d 5a 22 nopl 0x22\(%edx\)
[ ]*[a-f0-9]+: 0f 1e 5a 22 nopl 0x22\(%edx\)
[ ]*[a-f0-9]+: 0f 1f 5a 22 nopl 0x22\(%edx\)
[ ]*[a-f0-9]+: 0f 19 9c 1d 11 22 33 44 nopl 0x44332211\(%ebp,%ebx,1\)
[ ]*[a-f0-9]+: 0f 1a 9c 1d 11 22 33 44 nopl 0x44332211\(%ebp,%ebx,1\)
[ ]*[a-f0-9]+: 0f 1b 9c 1d 11 22 33 44 nopl 0x44332211\(%ebp,%ebx,1\)
[ ]*[a-f0-9]+: 0f 1c 9c 1d 11 22 33 44 nopl 0x44332211\(%ebp,%ebx,1\)
[ ]*[a-f0-9]+: 0f 1d 9c 1d 11 22 33 44 nopl 0x44332211\(%ebp,%ebx,1\)
[ ]*[a-f0-9]+: 0f 1e 9c 1d 11 22 33 44 nopl 0x44332211\(%ebp,%ebx,1\)
[ ]*[a-f0-9]+: 0f 1f 9c 1d 11 22 33 44 nopl 0x44332211\(%ebp,%ebx,1\)
[ ]*[a-f0-9]+: 0f 19 04 60 nopl \(%eax,%eiz,2\)
[ ]*[a-f0-9]+: 0f 1a 04 60 nopl \(%eax,%eiz,2\)
[ ]*[a-f0-9]+: 0f 1b 04 60 nopl \(%eax,%eiz,2\)
[ ]*[a-f0-9]+: 0f 1c 04 60 nopl \(%eax,%eiz,2\)
[ ]*[a-f0-9]+: 0f 1d 04 60 nopl \(%eax,%eiz,2\)
[ ]*[a-f0-9]+: 0f 1e 04 60 nopl \(%eax,%eiz,2\)
[ ]*[a-f0-9]+: 0f 1f 04 60 nopl \(%eax,%eiz,2\)
[ ]*[a-f0-9]+: 0f 19 04 59 nopl \(%ecx,%ebx,2\)
[ ]*[a-f0-9]+: 0f 1a 04 59 nopl \(%ecx,%ebx,2\)
[ ]*[a-f0-9]+: 0f 1b 04 59 nopl \(%ecx,%ebx,2\)
[ ]*[a-f0-9]+: 0f 1c 04 59 nopl \(%ecx,%ebx,2\)
[ ]*[a-f0-9]+: 0f 1d 04 59 nopl \(%ecx,%ebx,2\)
[ ]*[a-f0-9]+: 0f 1e 04 59 nopl \(%ecx,%ebx,2\)

8
gas/testsuite/gas/i386/nops.s
View File

@ -20,8 +20,6 @@
# with base and imm8
.byte 0x0f, 0x19, 0x5A, 0x22
.byte 0x0f, 0x1a, 0x5A, 0x22
.byte 0x0f, 0x1b, 0x5A, 0x22
.byte 0x0f, 0x1c, 0x5A, 0x22
.byte 0x0f, 0x1d, 0x5A, 0x22
.byte 0x0f, 0x1e, 0x5A, 0x22
@ -29,24 +27,18 @@
# with sib and imm32
.byte 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44
.byte 0x0f, 0x1a, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44
.byte 0x0f, 0x1b, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44
.byte 0x0f, 0x1c, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44
.byte 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44
.byte 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44
.byte 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44
.byte 0x0f, 0x19, 0x04, 0x60
.byte 0x0f, 0x1a, 0x04, 0x60
.byte 0x0f, 0x1b, 0x04, 0x60
.byte 0x0f, 0x1c, 0x04, 0x60
.byte 0x0f, 0x1d, 0x04, 0x60
.byte 0x0f, 0x1e, 0x04, 0x60
.byte 0x0f, 0x1f, 0x04, 0x60
.byte 0x0f, 0x19, 0x04, 0x59
.byte 0x0f, 0x1a, 0x04, 0x59
.byte 0x0f, 0x1b, 0x04, 0x59
.byte 0x0f, 0x1c, 0x04, 0x59
.byte 0x0f, 0x1d, 0x04, 0x59
.byte 0x0f, 0x1e, 0x04, 0x59

24
gas/testsuite/gas/i386/x86-64-mpx-add-bnd-prefix.d Normal file
View File

@ -0,0 +1,24 @@
#as: -madd-bnd-prefix
#objdump: -drw
#name: Check -madd-bnd-prefix (x86-64)
.*: +file format .*
Disassembly of section .text:
0+ <foo-0x14>:
[ ]*[a-f0-9]+: f2 e8 0e 00 00 00 bnd callq 14 <foo>
[ ]*[a-f0-9]+: f2 ff 10 bnd callq \*\(%rax\)
[ ]*[a-f0-9]+: f2 74 08 bnd je 14 <foo>
[ ]*[a-f0-9]+: f2 eb 05 bnd jmp 14 <foo>
[ ]*[a-f0-9]+: f2 ff 23 bnd jmpq \*\(%rbx\)
[ ]*[a-f0-9]+: f2 c3 bnd retq
0+14 <foo>:
[ ]*[a-f0-9]+: f2 c3 bnd retq
[ ]*[a-f0-9]+: f2 c3 bnd retq
[ ]*[a-f0-9]+: f2 e8 f6 ff ff ff bnd callq 14 <foo>
[ ]*[a-f0-9]+: 48 01 c3 add %rax,%rbx
[ ]*[a-f0-9]+: e2 f1 loop 14 <foo>
#pass

19
gas/testsuite/gas/i386/x86-64-mpx-add-bnd-prefix.s Normal file
View File

@ -0,0 +1,19 @@
# Check -madd-bnd-prefix option
.text
call foo
call *(%rax)
je foo
jmp foo
jmp *(%rbx)
ret
foo:
# Use of REPNE prefix - we shouldn't get any error
repne ret
# BND prefix already exists - we shouldn't get any error here
bnd ret
bnd call foo
# Following instructions can't have BND prefix even if
# -madd-bnd-prefix is specified
add %rax, %rbx
loop foo

40
gas/testsuite/gas/i386/x86-64-mpx-addr32.d Normal file
View File

@ -0,0 +1,40 @@
#objdump: -drw
#name: x86-64 MPX addr32 tests
.*: +file format .*
Disassembly of section .text:
0000000000000000 <.text>:
[ ]*[a-f0-9]+: 67 f3 0f 1b 08 addr32 bndmk \(%rax\),%bnd1
[ ]*[a-f0-9]+: 67 f3 0f 1b 4c 19 03 addr32 bndmk 0x3\(%rcx,%rbx,1\),%bnd1
[ ]*[a-f0-9]+: 67 66 41 0f 1a 08 addr32 bndmov \(%r8\),%bnd1
[ ]*[a-f0-9]+: 67 66 41 0f 1a 4c 11 03 addr32 bndmov 0x3\(%r9,%rdx,1\),%bnd1
[ ]*[a-f0-9]+: 67 66 0f 1b 08 addr32 bndmov %bnd1,\(%rax\)
[ ]*[a-f0-9]+: 67 66 0f 1b 4c 01 03 addr32 bndmov %bnd1,0x3\(%rcx,%rax,1\)
[ ]*[a-f0-9]+: 67 f3 0f 1a 09 addr32 bndcl \(%rcx\),%bnd1
[ ]*[a-f0-9]+: 67 f3 0f 1a 4c 01 03 addr32 bndcl 0x3\(%rcx,%rax,1\),%bnd1
[ ]*[a-f0-9]+: 67 f2 0f 1a 09 addr32 bndcu \(%rcx\),%bnd1
[ ]*[a-f0-9]+: 67 f2 0f 1a 4c 01 03 addr32 bndcu 0x3\(%rcx,%rax,1\),%bnd1
[ ]*[a-f0-9]+: 67 f2 0f 1b 09 addr32 bndcn \(%rcx\),%bnd1
[ ]*[a-f0-9]+: 67 f2 0f 1b 4c 01 03 addr32 bndcn 0x3\(%rcx,%rax,1\),%bnd1
[ ]*[a-f0-9]+: 67 0f 1b 44 18 03 addr32 bndstx %bnd0,0x3\(%rax,%rbx,1\)
[ ]*[a-f0-9]+: 67 0f 1b 53 03 addr32 bndstx %bnd2,0x3\(%rbx\)
[ ]*[a-f0-9]+: 67 0f 1a 44 18 03 addr32 bndldx 0x3\(%rax,%rbx,1\),%bnd0
[ ]*[a-f0-9]+: 67 0f 1a 53 03 addr32 bndldx 0x3\(%rbx\),%bnd2
[ ]*[a-f0-9]+: 67 f3 0f 1b 08 addr32 bndmk \(%rax\),%bnd1
[ ]*[a-f0-9]+: 67 f3 0f 1b 4c 02 03 addr32 bndmk 0x3\(%rdx,%rax,1\),%bnd1
[ ]*[a-f0-9]+: 67 66 0f 1a 08 addr32 bndmov \(%rax\),%bnd1
[ ]*[a-f0-9]+: 67 66 0f 1a 4c 02 03 addr32 bndmov 0x3\(%rdx,%rax,1\),%bnd1
[ ]*[a-f0-9]+: 67 66 0f 1b 08 addr32 bndmov %bnd1,\(%rax\)
[ ]*[a-f0-9]+: 67 66 0f 1b 4c 02 03 addr32 bndmov %bnd1,0x3\(%rdx,%rax,1\)
[ ]*[a-f0-9]+: 67 f3 0f 1a 08 addr32 bndcl \(%rax\),%bnd1
[ ]*[a-f0-9]+: 67 f3 0f 1a 4c 02 03 addr32 bndcl 0x3\(%rdx,%rax,1\),%bnd1
[ ]*[a-f0-9]+: 67 f2 0f 1a 08 addr32 bndcu \(%rax\),%bnd1
[ ]*[a-f0-9]+: 67 f2 0f 1a 4c 02 03 addr32 bndcu 0x3\(%rdx,%rax,1\),%bnd1
[ ]*[a-f0-9]+: 67 f2 0f 1b 08 addr32 bndcn \(%rax\),%bnd1
[ ]*[a-f0-9]+: 67 f2 0f 1b 4c 02 03 addr32 bndcn 0x3\(%rdx,%rax,1\),%bnd1
[ ]*[a-f0-9]+: 67 0f 1b 44 18 03 addr32 bndstx %bnd0,0x3\(%rax,%rbx,1\)
[ ]*[a-f0-9]+: 67 0f 1b 14 1d 03 00 00 00 addr32 bndstx %bnd2,0x3\(,%rbx,1\)
[ ]*[a-f0-9]+: 67 0f 1a 44 18 03 addr32 bndldx 0x3\(%rax,%rbx,1\),%bnd0
[ ]*[a-f0-9]+: 67 0f 1a 14 1d 03 00 00 00 addr32 bndldx 0x3\(,%rbx,1\),%bnd2

32
gas/testsuite/gas/i386/x86-64-mpx-addr32.s Normal file
View File

@ -0,0 +1,32 @@
.byte 0x67; bndmk (%rax),%bnd1
.byte 0x67; bndmk 0x3(%rcx,%rbx,1),%bnd1
.byte 0x67; bndmov (%r8),%bnd1
.byte 0x67; bndmov 0x3(%r9,%rdx,1),%bnd1
.byte 0x67; bndmov %bnd1,(%rax)
.byte 0x67; bndmov %bnd1,0x3(%rcx,%rax,1)
.byte 0x67; bndcl (%rcx),%bnd1
.byte 0x67; bndcl 0x3(%rcx,%rax,1),%bnd1
.byte 0x67; bndcu (%rcx),%bnd1
.byte 0x67; bndcu 0x3(%rcx,%rax,1),%bnd1
.byte 0x67; bndcn (%rcx),%bnd1
.byte 0x67; bndcn 0x3(%rcx,%rax,1),%bnd1
.byte 0x67; bndstx %bnd0,0x3(%rax,%rbx,1)
.byte 0x67; bndstx %bnd2,0x3(%rbx)
.byte 0x67; bndldx 0x3(%rax,%rbx,1),%bnd0
.byte 0x67; bndldx 0x3(%rbx),%bnd2
.byte 0x67; bndmk (%rax),%bnd1
.byte 0x67; bndmk 0x3(%rdx,%rax,1),%bnd1
.byte 0x67; bndmov (%rax),%bnd1
.byte 0x67; bndmov 0x3(%rdx,%rax,1),%bnd1
.byte 0x67; bndmov %bnd1,(%rax)
.byte 0x67; bndmov %bnd1,0x3(%rdx,%rax,1)
.byte 0x67; bndcl (%rax),%bnd1
.byte 0x67; bndcl 0x3(%rdx,%rax,1),%bnd1
.byte 0x67; bndcu (%rax),%bnd1
.byte 0x67; bndcu 0x3(%rdx,%rax,1),%bnd1
.byte 0x67; bndcn (%rax),%bnd1
.byte 0x67; bndcn 0x3(%rdx,%rax,1),%bnd1
.byte 0x67; bndstx %bnd0,0x3(%rax,%rbx,1)
.byte 0x67; bndstx %bnd2,0x3(,%rbx,1)
.byte 0x67; bndldx 0x3(%rax,%rbx,1),%bnd0
.byte 0x67; bndldx 0x3(,%rbx,1),%bnd2

33
gas/testsuite/gas/i386/x86-64-mpx-inval-1.l Normal file
View File

@ -0,0 +1,33 @@
.*: Assembler messages:
.*:4: Error: expecting valid branch instruction after `bnd'
.*:5: Error: expecting valid branch instruction after `bnd'
.*:6: Error: expecting valid branch instruction after `bnd'
.*:7: Error: expecting valid branch instruction after `bnd'
.*:10: Error: expecting valid branch instruction after `bnd'
.*:11: Error: expecting valid branch instruction after `bnd'
.*:12: Error: expecting valid branch instruction after `bnd'
.*:13: Error: expecting valid branch instruction after `bnd'
GAS LISTING .*
[ ]*1[ ]+\# MPX instructions
[ ]*2[ ]+\.allow_index_reg
[ ]*3[ ]+\.text
[ ]*4[ ]+\?\?\?\? F24801C3 bnd add %rax, %rbx \# Bad
\*\*\*\* Error:expecting valid branch instruction after `bnd'
[ ]*5[ ]+\?\?\?\? 6766F2AB bnd stosw \(%edi\) \# Bad
\*\*\*\* Error:expecting valid branch instruction after `bnd'
[ ]*6[ ]+\?\?\?\? F2E200 bnd loop foo
\*\*\*\* Error:expecting valid branch instruction after `bnd'
[ ]*7[ ]+\?\?\?\? F2E300 bnd jrcxz foo
\*\*\*\* Error:expecting valid branch instruction after `bnd'
[ ]*8[ ]+
[ ]*9[ ]+\.intel_syntax noprefix
[ ]*10[ ]+\?\?\?\? F24801C3 bnd add rbx, rax \# Bad
\*\*\*\* Error:expecting valid branch instruction after `bnd'
[ ]*11[ ]+\?\?\?\? 6766F2AB bnd stos WORD PTR \[edi] \# Bad
\*\*\*\* Error:expecting valid branch instruction after `bnd'
[ ]*12[ ]+\?\?\?\? F2E200 bnd loop foo
\*\*\*\* Error:expecting valid branch instruction after `bnd'
[ ]*13[ ]+\?\?\?\? F2E300 bnd jrcxz foo
\*\*\*\* Error:expecting valid branch instruction after `bnd'

13
gas/testsuite/gas/i386/x86-64-mpx-inval-1.s Normal file
View File

@ -0,0 +1,13 @@
# MPX instructions
.allow_index_reg
.text
bnd add %rax, %rbx # Bad
bnd stosw (%edi) # Bad
bnd loop foo
bnd jrcxz foo
.intel_syntax noprefix
bnd add rbx, rax # Bad
bnd stos WORD PTR [edi] # Bad
bnd loop foo
bnd jrcxz foo

173
gas/testsuite/gas/i386/x86-64-mpx-inval-2.l Normal file
View File

@ -0,0 +1,173 @@
.*: Assembler messages:
.*:6: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:7: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:10: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:11: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:13: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:14: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:17: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:18: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:21: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:22: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:25: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:26: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:29: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:30: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:33: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:34: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:37: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:38: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:41: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:42: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:44: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:45: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:48: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:49: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:52: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:53: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:56: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:57: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:60: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:61: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:64: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:65: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
GAS LISTING .*
[ ]*1[ ]+\# MPX instructions
[ ]*2[ ]+\.allow_index_reg
[ ]*3[ ]+\.text
[ ]*4[ ]+
[ ]*5[ ]+\#\#\# bndmk
[ ]*6[ ]+\?\?\?\? 67F30F1B bndmk \(%eax\), %bnd1
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*6[ ]+08
[ ]*7[ ]+\?\?\?\? 67F30F1B bndmk 0x3\(%ecx,%ebx,1\), %bnd1
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*7[ ]+4C1903
[ ]*8[ ]+
[ ]*9[ ]+\#\#\# bndmov
[ ]*10[ ]+\?\?\?\? 6766410F bndmov \(%r8d\), %bnd1
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*10[ ]+1A08
[ ]*11[ ]+\?\?\?\? 6766410F bndmov 0x3\(%r9d,%edx,1\), %bnd1
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*11[ ]+1A4C1103
[ ]*12[ ]+
[ ]*13[ ]+\?\?\?\? 67660F1B bndmov %bnd1, \(%eax\)
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*13[ ]+08
[ ]*14[ ]+\?\?\?\? 67660F1B bndmov %bnd1, 0x3\(%ecx,%eax,1\)
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*14[ ]+4C0103
[ ]*15[ ]+
[ ]*16[ ]+\#\#\# bndcl
[ ]*17[ ]+\?\?\?\? 67F30F1A bndcl \(%ecx\), %bnd1
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*17[ ]+09
[ ]*18[ ]+\?\?\?\? 67F30F1A bndcl 0x3\(%ecx,%eax,1\), %bnd1
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*18[ ]+4C0103
[ ]*19[ ]+
[ ]*20[ ]+\#\#\# bndcu
[ ]*21[ ]+\?\?\?\? 67F20F1A bndcu \(%ecx\), %bnd1
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*21[ ]+09
[ ]*22[ ]+\?\?\?\? 67F20F1A bndcu 0x3\(%ecx,%eax,1\), %bnd1
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*22[ ]+4C0103
[ ]*23[ ]+
[ ]*24[ ]+\#\#\# bndcn
[ ]*25[ ]+\?\?\?\? 67F20F1B bndcn \(%ecx\), %bnd1
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*25[ ]+09
[ ]*26[ ]+\?\?\?\? 67F20F1B bndcn 0x3\(%ecx,%eax,1\), %bnd1
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*26[ ]+4C0103
[ ]*27[ ]+
[ ]*28[ ]+\#\#\# bndstx
[ ]*29[ ]+\?\?\?\? 670F1B44 bndstx %bnd0, 0x3\(%eax,%ebx,1\)
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*29[ ]+1803
[ ]*30[ ]+\?\?\?\? 670F1B53 bndstx %bnd2, 3\(%ebx,1\)
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
GAS LISTING .*
[ ]*30[ ]+03
[ ]*31[ ]+
[ ]*32[ ]+\#\#\# bndldx
[ ]*33[ ]+\?\?\?\? 670F1A44 bndldx 0x3\(%eax,%ebx,1\), %bnd0
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*33[ ]+1803
[ ]*34[ ]+\?\?\?\? 670F1A53 bndldx 3\(%ebx,1\), %bnd2
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*34[ ]+03
[ ]*35[ ]+
[ ]*36[ ]+\.intel_syntax noprefix
[ ]*37[ ]+\?\?\?\? 67F30F1B bndmk bnd1, \[eax\]
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*37[ ]+08
[ ]*38[ ]+\?\?\?\? 67F30F1B bndmk bnd1, \[edx\+1\*eax\+0x3\]
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*38[ ]+4C0203
[ ]*39[ ]+
[ ]*40[ ]+\#\#\# bndmov
[ ]*41[ ]+\?\?\?\? 67660F1A bndmov bnd1, \[eax\]
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*41[ ]+08
[ ]*42[ ]+\?\?\?\? 67660F1A bndmov bnd1, \[edx\+1\*eax\+0x3\]
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*42[ ]+4C0203
[ ]*43[ ]+
[ ]*44[ ]+\?\?\?\? 67660F1B bndmov \[eax\], bnd1
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*44[ ]+08
[ ]*45[ ]+\?\?\?\? 67660F1B bndmov \[edx\+1\*eax\+0x3\], bnd1
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*45[ ]+4C0203
[ ]*46[ ]+
[ ]*47[ ]+\#\#\# bndcl
[ ]*48[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[eax\]
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*48[ ]+08
[ ]*49[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[edx\+1\*eax\+0x3\]
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*49[ ]+4C0203
[ ]*50[ ]+
[ ]*51[ ]+\#\#\# bndcu
[ ]*52[ ]+\?\?\?\? 67F20F1A bndcu bnd1, \[eax\]
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*52[ ]+08
[ ]*53[ ]+\?\?\?\? 67F20F1A bndcu bnd1, \[edx\+1\*eax\+0x3\]
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*53[ ]+4C0203
[ ]*54[ ]+
[ ]*55[ ]+\#\#\# bndcn
[ ]*56[ ]+\?\?\?\? 67F20F1B bndcn bnd1, \[eax\]
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*56[ ]+08
[ ]*57[ ]+\?\?\?\? 67F20F1B bndcn bnd1, \[edx\+1\*eax\+0x3\]
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*57[ ]+4C0203
[ ]*58[ ]+
GAS LISTING .*
[ ]*59[ ]+\#\#\# bndstx
[ ]*60[ ]+\?\?\?\? 670F1B44 bndstx \[eax\+ebx\*1\+0x3\], bnd0
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*60[ ]+1803
[ ]*61[ ]+\?\?\?\? 670F1B14 bndstx \[1\*ebx\+3\], bnd2
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*61[ ]+1D030000
[ ]*61[ ]+00
[ ]*62[ ]+
[ ]*63[ ]+\#\#\# bndldx
[ ]*64[ ]+\?\?\?\? 670F1A44 bndldx bnd0, \[eax\+ebx\*1\+0x3\]
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*64[ ]+1803
[ ]*65[ ]+\?\?\?\? 670F1A14 bndldx bnd2, \[1\*ebx\+3\]
\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*65[ ]+1D030000
[ ]*65[ ]+00

65
gas/testsuite/gas/i386/x86-64-mpx-inval-2.s Normal file
View File

@ -0,0 +1,65 @@
# MPX instructions
.allow_index_reg
.text
### bndmk
bndmk (%eax), %bnd1
bndmk 0x3(%ecx,%ebx,1), %bnd1
### bndmov
bndmov (%r8d), %bnd1
bndmov 0x3(%r9d,%edx,1), %bnd1
bndmov %bnd1, (%eax)
bndmov %bnd1, 0x3(%ecx,%eax,1)
### bndcl
bndcl (%ecx), %bnd1
bndcl 0x3(%ecx,%eax,1), %bnd1
### bndcu
bndcu (%ecx), %bnd1
bndcu 0x3(%ecx,%eax,1), %bnd1
### bndcn
bndcn (%ecx), %bnd1
bndcn 0x3(%ecx,%eax,1), %bnd1
### bndstx
bndstx %bnd0, 0x3(%eax,%ebx,1)
bndstx %bnd2, 3(%ebx,1)
### bndldx
bndldx 0x3(%eax,%ebx,1), %bnd0
bndldx 3(%ebx,1), %bnd2
.intel_syntax noprefix
bndmk bnd1, [eax]
bndmk bnd1, [edx+1*eax+0x3]
### bndmov
bndmov bnd1, [eax]
bndmov bnd1, [edx+1*eax+0x3]
bndmov [eax], bnd1
bndmov [edx+1*eax+0x3], bnd1
### bndcl
bndcl bnd1, [eax]
bndcl bnd1, [edx+1*eax+0x3]
### bndcu
bndcu bnd1, [eax]
bndcu bnd1, [edx+1*eax+0x3]
### bndcn
bndcn bnd1, [eax]
bndcn bnd1, [edx+1*eax+0x3]
### bndstx
bndstx [eax+ebx*1+0x3], bnd0
bndstx [1*ebx+3], bnd2
### bndldx
bndldx bnd0, [eax+ebx*1+0x3]
bndldx bnd2, [1*ebx+3]

191
gas/testsuite/gas/i386/x86-64-mpx.d Normal file
View File

@ -0,0 +1,191 @@
#objdump: -drw
#name: x86-64 MPX
.*: +file format .*
Disassembly of section .text:
0+ <foo-0x434>:
[ ]*[a-f0-9]+: f3 41 0f 1b 0b bndmk \(%r11\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 08 bndmk \(%rax\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 0c 25 99 03 00 00 bndmk 0x399,%bnd1
[ ]*[a-f0-9]+: f3 41 0f 1b 49 03 bndmk 0x3\(%r9\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 48 03 bndmk 0x3\(%rax\),%bnd1
[ ]*[a-f0-9]+: f3 42 0f 1b 0c 25 03 00 00 00 bndmk 0x3\(,%r12,1\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 0c 08 bndmk \(%rax,%rcx,1\),%bnd1
[ ]*[a-f0-9]+: f3 41 0f 1b 4c 03 03 bndmk 0x3\(%r11,%rax,1\),%bnd1
[ ]*[a-f0-9]+: f3 42 0f 1b 4c 0b 03 bndmk 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: 66 41 0f 1a 0b bndmov \(%r11\),%bnd1
[ ]*[a-f0-9]+: 66 0f 1a 08 bndmov \(%rax\),%bnd1
[ ]*[a-f0-9]+: 66 0f 1a 0c 25 99 03 00 00 bndmov 0x399,%bnd1
[ ]*[a-f0-9]+: 66 41 0f 1a 51 03 bndmov 0x3\(%r9\),%bnd2
[ ]*[a-f0-9]+: 66 0f 1a 50 03 bndmov 0x3\(%rax\),%bnd2
[ ]*[a-f0-9]+: 66 42 0f 1a 04 25 03 00 00 00 bndmov 0x3\(,%r12,1\),%bnd0
[ ]*[a-f0-9]+: 66 0f 1a 14 10 bndmov \(%rax,%rdx,1\),%bnd2
[ ]*[a-f0-9]+: 66 41 0f 1a 4c 03 03 bndmov 0x3\(%r11,%rax,1\),%bnd1
[ ]*[a-f0-9]+: 66 42 0f 1a 4c 0b 03 bndmov 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: 66 0f 1a c2 bndmov %bnd2,%bnd0
[ ]*[a-f0-9]+: 66 41 0f 1b 0b bndmov %bnd1,\(%r11\)
[ ]*[a-f0-9]+: 66 0f 1b 08 bndmov %bnd1,\(%rax\)
[ ]*[a-f0-9]+: 66 0f 1b 0c 25 99 03 00 00 bndmov %bnd1,0x399
[ ]*[a-f0-9]+: 66 41 0f 1b 51 03 bndmov %bnd2,0x3\(%r9\)
[ ]*[a-f0-9]+: 66 0f 1b 50 03 bndmov %bnd2,0x3\(%rax\)
[ ]*[a-f0-9]+: 66 42 0f 1b 04 25 03 00 00 00 bndmov %bnd0,0x3\(,%r12,1\)
[ ]*[a-f0-9]+: 66 0f 1b 14 10 bndmov %bnd2,\(%rax,%rdx,1\)
[ ]*[a-f0-9]+: 66 41 0f 1b 4c 03 03 bndmov %bnd1,0x3\(%r11,%rax,1\)
[ ]*[a-f0-9]+: 66 42 0f 1b 4c 0b 03 bndmov %bnd1,0x3\(%rbx,%r9,1\)
[ ]*[a-f0-9]+: 66 0f 1a d0 bndmov %bnd0,%bnd2
[ ]*[a-f0-9]+: f3 41 0f 1a 0b bndcl \(%r11\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 08 bndcl \(%rax\),%bnd1
[ ]*[a-f0-9]+: f3 49 0f 1a cb bndcl %r11,%bnd1
[ ]*[a-f0-9]+: f3 48 0f 1a c9 bndcl %rcx,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a c8 bndcl %eax,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0c 25 99 03 00 00 bndcl 0x399,%bnd1
[ ]*[a-f0-9]+: f3 41 0f 1a 51 03 bndcl 0x3\(%r9\),%bnd2
[ ]*[a-f0-9]+: f3 0f 1a 50 03 bndcl 0x3\(%rax\),%bnd2
[ ]*[a-f0-9]+: f3 42 0f 1a 04 25 03 00 00 00 bndcl 0x3\(,%r12,1\),%bnd0
[ ]*[a-f0-9]+: f3 0f 1a 14 10 bndcl \(%rax,%rdx,1\),%bnd2
[ ]*[a-f0-9]+: f3 41 0f 1a 4c 03 03 bndcl 0x3\(%r11,%rax,1\),%bnd1
[ ]*[a-f0-9]+: f3 42 0f 1a 4c 0b 03 bndcl 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1a 0b bndcu \(%r11\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 08 bndcu \(%rax\),%bnd1
[ ]*[a-f0-9]+: f2 49 0f 1a cb bndcu %r11,%bnd1
[ ]*[a-f0-9]+: f2 48 0f 1a c9 bndcu %rcx,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a c8 bndcu %eax,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0c 25 99 03 00 00 bndcu 0x399,%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1a 51 03 bndcu 0x3\(%r9\),%bnd2
[ ]*[a-f0-9]+: f2 0f 1a 50 03 bndcu 0x3\(%rax\),%bnd2
[ ]*[a-f0-9]+: f2 42 0f 1a 04 25 03 00 00 00 bndcu 0x3\(,%r12,1\),%bnd0
[ ]*[a-f0-9]+: f2 0f 1a 14 10 bndcu \(%rax,%rdx,1\),%bnd2
[ ]*[a-f0-9]+: f2 41 0f 1a 4c 03 03 bndcu 0x3\(%r11,%rax,1\),%bnd1
[ ]*[a-f0-9]+: f2 42 0f 1a 4c 0b 03 bndcu 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1b 0b bndcn \(%r11\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 08 bndcn \(%rax\),%bnd1
[ ]*[a-f0-9]+: f2 49 0f 1b cb bndcn %r11,%bnd1
[ ]*[a-f0-9]+: f2 48 0f 1b c9 bndcn %rcx,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b c8 bndcn %eax,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0c 25 99 03 00 00 bndcn 0x399,%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1b 51 03 bndcn 0x3\(%r9\),%bnd2
[ ]*[a-f0-9]+: f2 0f 1b 50 03 bndcn 0x3\(%rax\),%bnd2
[ ]*[a-f0-9]+: f2 42 0f 1b 04 25 03 00 00 00 bndcn 0x3\(,%r12,1\),%bnd0
[ ]*[a-f0-9]+: f2 0f 1b 14 10 bndcn \(%rax,%rdx,1\),%bnd2
[ ]*[a-f0-9]+: f2 41 0f 1b 4c 03 03 bndcn 0x3\(%r11,%rax,1\),%bnd1
[ ]*[a-f0-9]+: f2 42 0f 1b 4c 0b 03 bndcn 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: 0f 1b 44 18 03 bndstx %bnd0,0x3\(%rax,%rbx,1\)
[ ]*[a-f0-9]+: 0f 1b 54 13 03 bndstx %bnd2,0x3\(%rbx,%rdx,1\)
[ ]*[a-f0-9]+: 41 0f 1b 9c 24 99 03 00 00 bndstx %bnd3,0x399\(%r12\)
[ ]*[a-f0-9]+: 41 0f 1b 8b 34 12 00 00 bndstx %bnd1,0x1234\(%r11\)
[ ]*[a-f0-9]+: 0f 1b 93 34 12 00 00 bndstx %bnd2,0x1234\(%rbx\)
[ ]*[a-f0-9]+: 0f 1b 14 1d 03 00 00 00 bndstx %bnd2,0x3\(,%rbx,1\)
[ ]*[a-f0-9]+: 42 0f 1b 14 25 03 00 00 00 bndstx %bnd2,0x3\(,%r12,1\)
[ ]*[a-f0-9]+: 0f 1b 0a bndstx %bnd1,\(%rdx\)
[ ]*[a-f0-9]+: 0f 1a 44 18 03 bndldx 0x3\(%rax,%rbx,1\),%bnd0
[ ]*[a-f0-9]+: 0f 1a 54 13 03 bndldx 0x3\(%rbx,%rdx,1\),%bnd2
[ ]*[a-f0-9]+: 41 0f 1a 9c 24 99 03 00 00 bndldx 0x399\(%r12\),%bnd3
[ ]*[a-f0-9]+: 41 0f 1a 8b 34 12 00 00 bndldx 0x1234\(%r11\),%bnd1
[ ]*[a-f0-9]+: 0f 1a 93 34 12 00 00 bndldx 0x1234\(%rbx\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 14 1d 03 00 00 00 bndldx 0x3\(,%rbx,1\),%bnd2
[ ]*[a-f0-9]+: 42 0f 1a 14 25 03 00 00 00 bndldx 0x3\(,%r12,1\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%rdx\),%bnd1
[ ]*[a-f0-9]+: f2 e8 34 02 00 00 bnd callq 434 <foo>
[ ]*[a-f0-9]+: f2 ff 10 bnd callq \*\(%rax\)
[ ]*[a-f0-9]+: f2 41 ff 13 bnd callq \*\(%r11\)
[ ]*[a-f0-9]+: f2 0f 84 26 02 00 00 bnd je 434 <foo>
[ ]*[a-f0-9]+: f2 e9 20 02 00 00 bnd jmpq 434 <foo>
[ ]*[a-f0-9]+: f2 ff 21 bnd jmpq \*\(%rcx\)
[ ]*[a-f0-9]+: f2 41 ff 24 24 bnd jmpq \*\(%r12\)
[ ]*[a-f0-9]+: f2 c3 bnd retq
[ ]*[a-f0-9]+: f3 41 0f 1b 0b bndmk \(%r11\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 08 bndmk \(%rax\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 0c 25 99 03 00 00 bndmk 0x399,%bnd1
[ ]*[a-f0-9]+: f3 41 0f 1b 49 03 bndmk 0x3\(%r9\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 48 03 bndmk 0x3\(%rax\),%bnd1
[ ]*[a-f0-9]+: f3 42 0f 1b 0c 25 03 00 00 00 bndmk 0x3\(,%r12,1\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1b 0c 08 bndmk \(%rax,%rcx,1\),%bnd1
[ ]*[a-f0-9]+: f3 41 0f 1b 4c 03 03 bndmk 0x3\(%r11,%rax,1\),%bnd1
[ ]*[a-f0-9]+: f3 42 0f 1b 4c 0b 03 bndmk 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: 66 41 0f 1a 0b bndmov \(%r11\),%bnd1
[ ]*[a-f0-9]+: 66 0f 1a 08 bndmov \(%rax\),%bnd1
[ ]*[a-f0-9]+: 66 0f 1a 0c 25 99 03 00 00 bndmov 0x399,%bnd1
[ ]*[a-f0-9]+: 66 41 0f 1a 51 03 bndmov 0x3\(%r9\),%bnd2
[ ]*[a-f0-9]+: 66 0f 1a 50 03 bndmov 0x3\(%rax\),%bnd2
[ ]*[a-f0-9]+: 66 42 0f 1a 04 25 03 00 00 00 bndmov 0x3\(,%r12,1\),%bnd0
[ ]*[a-f0-9]+: 66 0f 1a 14 10 bndmov \(%rax,%rdx,1\),%bnd2
[ ]*[a-f0-9]+: 66 41 0f 1a 4c 03 03 bndmov 0x3\(%r11,%rax,1\),%bnd1
[ ]*[a-f0-9]+: 66 42 0f 1a 4c 0b 03 bndmov 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: 66 0f 1a c2 bndmov %bnd2,%bnd0
[ ]*[a-f0-9]+: 66 41 0f 1b 0b bndmov %bnd1,\(%r11\)
[ ]*[a-f0-9]+: 66 0f 1b 08 bndmov %bnd1,\(%rax\)
[ ]*[a-f0-9]+: 66 0f 1b 0c 25 99 03 00 00 bndmov %bnd1,0x399
[ ]*[a-f0-9]+: 66 41 0f 1b 51 03 bndmov %bnd2,0x3\(%r9\)
[ ]*[a-f0-9]+: 66 0f 1b 50 03 bndmov %bnd2,0x3\(%rax\)
[ ]*[a-f0-9]+: 66 42 0f 1b 04 25 03 00 00 00 bndmov %bnd0,0x3\(,%r12,1\)
[ ]*[a-f0-9]+: 66 0f 1b 14 10 bndmov %bnd2,\(%rax,%rdx,1\)
[ ]*[a-f0-9]+: 66 41 0f 1b 4c 03 03 bndmov %bnd1,0x3\(%r11,%rax,1\)
[ ]*[a-f0-9]+: 66 42 0f 1b 4c 0b 03 bndmov %bnd1,0x3\(%rbx,%r9,1\)
[ ]*[a-f0-9]+: 66 0f 1a d0 bndmov %bnd0,%bnd2
[ ]*[a-f0-9]+: f3 41 0f 1a 0b bndcl \(%r11\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 08 bndcl \(%rax\),%bnd1
[ ]*[a-f0-9]+: f3 49 0f 1a cb bndcl %r11,%bnd1
[ ]*[a-f0-9]+: f3 48 0f 1a c9 bndcl %rcx,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a c8 bndcl %eax,%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0c 25 99 03 00 00 bndcl 0x399,%bnd1
[ ]*[a-f0-9]+: f3 41 0f 1a 49 03 bndcl 0x3\(%r9\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 48 03 bndcl 0x3\(%rax\),%bnd1
[ ]*[a-f0-9]+: f3 42 0f 1a 0c 25 03 00 00 00 bndcl 0x3\(,%r12,1\),%bnd1
[ ]*[a-f0-9]+: f3 0f 1a 0c 08 bndcl \(%rax,%rcx,1\),%bnd1
[ ]*[a-f0-9]+: f3 41 0f 1a 4c 03 03 bndcl 0x3\(%r11,%rax,1\),%bnd1
[ ]*[a-f0-9]+: f3 42 0f 1a 4c 0b 03 bndcl 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1a 0b bndcu \(%r11\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 08 bndcu \(%rax\),%bnd1
[ ]*[a-f0-9]+: f2 49 0f 1a cb bndcu %r11,%bnd1
[ ]*[a-f0-9]+: f2 48 0f 1a c9 bndcu %rcx,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a c8 bndcu %eax,%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0c 25 99 03 00 00 bndcu 0x399,%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1a 49 03 bndcu 0x3\(%r9\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 48 03 bndcu 0x3\(%rax\),%bnd1
[ ]*[a-f0-9]+: f2 42 0f 1a 0c 25 03 00 00 00 bndcu 0x3\(,%r12,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1a 0c 08 bndcu \(%rax,%rcx,1\),%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1a 4c 03 03 bndcu 0x3\(%r11,%rax,1\),%bnd1
[ ]*[a-f0-9]+: f2 42 0f 1a 4c 0b 03 bndcu 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1b 0b bndcn \(%r11\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 08 bndcn \(%rax\),%bnd1
[ ]*[a-f0-9]+: f2 49 0f 1b cb bndcn %r11,%bnd1
[ ]*[a-f0-9]+: f2 48 0f 1b c9 bndcn %rcx,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b c8 bndcn %eax,%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0c 25 99 03 00 00 bndcn 0x399,%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1b 49 03 bndcn 0x3\(%r9\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 48 03 bndcn 0x3\(%rax\),%bnd1
[ ]*[a-f0-9]+: f2 42 0f 1b 0c 0d 03 00 00 00 bndcn 0x3\(,%r9,1\),%bnd1
[ ]*[a-f0-9]+: f2 0f 1b 0c 08 bndcn \(%rax,%rcx,1\),%bnd1
[ ]*[a-f0-9]+: f2 41 0f 1b 4c 03 03 bndcn 0x3\(%r11,%rax,1\),%bnd1
[ ]*[a-f0-9]+: f2 42 0f 1b 4c 0b 03 bndcn 0x3\(%rbx,%r9,1\),%bnd1
[ ]*[a-f0-9]+: 0f 1b 44 18 03 bndstx %bnd0,0x3\(%rax,%rbx,1\)
[ ]*[a-f0-9]+: 0f 1b 54 13 03 bndstx %bnd2,0x3\(%rbx,%rdx,1\)
[ ]*[a-f0-9]+: 41 0f 1b 9c 24 99 03 00 00 bndstx %bnd3,0x399\(%r12\)
[ ]*[a-f0-9]+: 41 0f 1b 8b 34 12 00 00 bndstx %bnd1,0x1234\(%r11\)
[ ]*[a-f0-9]+: 0f 1b 93 34 12 00 00 bndstx %bnd2,0x1234\(%rbx\)
[ ]*[a-f0-9]+: 0f 1b 14 1d 03 00 00 00 bndstx %bnd2,0x3\(,%rbx,1\)
[ ]*[a-f0-9]+: 42 0f 1b 14 25 03 00 00 00 bndstx %bnd2,0x3\(,%r12,1\)
[ ]*[a-f0-9]+: 0f 1b 0a bndstx %bnd1,\(%rdx\)
[ ]*[a-f0-9]+: 0f 1a 44 18 03 bndldx 0x3\(%rax,%rbx,1\),%bnd0
[ ]*[a-f0-9]+: 0f 1a 54 13 03 bndldx 0x3\(%rbx,%rdx,1\),%bnd2
[ ]*[a-f0-9]+: 41 0f 1a 9c 24 99 03 00 00 bndldx 0x399\(%r12\),%bnd3
[ ]*[a-f0-9]+: 41 0f 1a 8b 34 12 00 00 bndldx 0x1234\(%r11\),%bnd1
[ ]*[a-f0-9]+: 0f 1a 93 34 12 00 00 bndldx 0x1234\(%rbx\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 14 1d 03 00 00 00 bndldx 0x3\(,%rbx,1\),%bnd2
[ ]*[a-f0-9]+: 42 0f 1a 14 25 03 00 00 00 bndldx 0x3\(,%r12,1\),%bnd2
[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%rdx\),%bnd1
[ ]*[a-f0-9]+: f2 e8 16 00 00 00 bnd callq 434 <foo>
[ ]*[a-f0-9]+: f2 ff d0 bnd callq \*%rax
[ ]*[a-f0-9]+: f2 41 ff d3 bnd callq \*%r11
[ ]*[a-f0-9]+: f2 74 0c bnd je 434 <foo>
[ ]*[a-f0-9]+: f2 eb 09 bnd jmp 434 <foo>
[ ]*[a-f0-9]+: f2 ff e1 bnd jmpq \*%rcx
[ ]*[a-f0-9]+: f2 41 ff e4 bnd jmpq \*%r12
[ ]*[a-f0-9]+: f2 c3 bnd retq
0+434 <foo>:
[ ]*[a-f0-9]+: f2 c3 bnd retq
#pass

217
gas/testsuite/gas/i386/x86-64-mpx.s Normal file
View File

@ -0,0 +1,217 @@
# MPX instructions
.allow_index_reg
.text
### bndmk
bndmk (%r11), %bnd1
bndmk (%rax), %bnd1
bndmk (0x399), %bnd1
bndmk 0x3(%r9), %bnd1
bndmk 0x3(%rax), %bnd1
bndmk 0x3(,%r12,1), %bnd1
bndmk (%rax,%rcx), %bnd1
bndmk 0x3(%r11,%rax,1), %bnd1
bndmk 0x3(%rbx,%r9,1), %bnd1
### bndmov
bndmov (%r11), %bnd1
bndmov (%rax), %bnd1
bndmov (0x399), %bnd1
bndmov 0x3(%r9), %bnd2
bndmov 0x3(%rax), %bnd2
bndmov 0x3(,%r12,1), %bnd0
bndmov (%rax,%rdx), %bnd2
bndmov 0x3(%r11,%rax,1), %bnd1
bndmov 0x3(%rbx,%r9,1), %bnd1
bndmov %bnd2, %bnd0
bndmov %bnd1, (%r11)
bndmov %bnd1, (%rax)
bndmov %bnd1, (0x399)
bndmov %bnd2, 0x3(%r9)
bndmov %bnd2, 0x3(%rax)
bndmov %bnd0, 0x3(,%r12,1)
bndmov %bnd2, (%rax,%rdx)
bndmov %bnd1, 0x3(%r11,%rax,1)
bndmov %bnd1, 0x3(%rbx,%r9,1)
bndmov %bnd0, %bnd2
### bndcl
bndcl (%r11), %bnd1
bndcl (%rax), %bnd1
bndcl %r11, %bnd1
bndcl %rcx, %bnd1
bndcl %ax, %bnd1
bndcl (0x399), %bnd1
bndcl 0x3(%r9), %bnd2
bndcl 0x3(%rax), %bnd2
bndcl 0x3(,%r12,1), %bnd0
bndcl (%rax,%rdx), %bnd2
bndcl 0x3(%r11,%rax,1), %bnd1
bndcl 0x3(%rbx,%r9,1), %bnd1
### bndcu
bndcu (%r11), %bnd1
bndcu (%rax), %bnd1
bndcu %r11, %bnd1
bndcu %rcx, %bnd1
bndcu %ax, %bnd1
bndcu (0x399), %bnd1
bndcu 0x3(%r9), %bnd2
bndcu 0x3(%rax), %bnd2
bndcu 0x3(,%r12,1), %bnd0
bndcu (%rax,%rdx), %bnd2
bndcu 0x3(%r11,%rax,1), %bnd1
bndcu 0x3(%rbx,%r9,1), %bnd1
### bndcn
bndcn (%r11), %bnd1
bndcn (%rax), %bnd1
bndcn %r11, %bnd1
bndcn %rcx, %bnd1
bndcn %ax, %bnd1
bndcn (0x399), %bnd1
bndcn 0x3(%r9), %bnd2
bndcn 0x3(%rax), %bnd2
bndcn 0x3(,%r12,1), %bnd0
bndcn (%rax,%rdx), %bnd2
bndcn 0x3(%r11,%rax,1), %bnd1
bndcn 0x3(%rbx,%r9,1), %bnd1
### bndstx
bndstx %bnd0, 0x3(%rax,%rbx,1)
bndstx %bnd2, 3(%rbx,%rdx)
bndstx %bnd3, 0x399(%r12)
bndstx %bnd1, 0x1234(%r11)
bndstx %bnd2, 0x1234(%rbx)
bndstx %bnd2, 3(,%rbx,1)
bndstx %bnd2, 3(,%r12,1)
bndstx %bnd1, (%rdx)
### bndldx
bndldx 0x3(%rax,%rbx,1), %bnd0
bndldx 3(%rbx,%rdx), %bnd2
bndldx 0x399(%r12), %bnd3
bndldx 0x1234(%r11), %bnd1
bndldx 0x1234(%rbx), %bnd2
bndldx 3(,%rbx,1), %bnd2
bndldx 3(,%r12,1), %bnd2
bndldx (%rdx), %bnd1
### bnd
bnd call foo
bnd call *(%rax)
bnd call *(%r11)
bnd je foo
bnd jmp foo
bnd jmp *(%rcx)
bnd jmp *(%r12)
bnd ret
.intel_syntax noprefix
bndmk bnd1, [r11]
bndmk bnd1, [rax]
bndmk bnd1, [0x399]
bndmk bnd1, [r9+0x3]
bndmk bnd1, [rax+0x3]
bndmk bnd1, [1*r12+0x3]
bndmk bnd1, [rax+rcx]
bndmk bnd1, [r11+1*rax+0x3]
bndmk bnd1, [rbx+1*r9+0x3]
### bndmov
bndmov bnd1, [r11]
bndmov bnd1, [rax]
bndmov bnd1, [0x399]
bndmov bnd2, [r9+0x3]
bndmov bnd2, [rax+0x3]
bndmov bnd0, [1*r12+0x3]
bndmov bnd2, [rax+rdx]
bndmov bnd1, [r11+1*rax+0x3]
bndmov bnd1, [rbx+1*r9+0x3]
bndmov bnd0, bnd2
bndmov [r11], bnd1
bndmov [rax], bnd1
bndmov [0x399], bnd1
bndmov [r9+0x3], bnd2
bndmov [rax+0x3], bnd2
bndmov [1*r12+0x3], bnd0
bndmov [rax+rdx], bnd2
bndmov [r11+1*rax+0x3], bnd1
bndmov [rbx+1*r9+0x3], bnd1
bndmov bnd2, bnd0
### bndcl
bndcl bnd1, [r11]
bndcl bnd1, [rax]
bndcl bnd1, r11
bndcl bnd1, rcx
bndcl bnd1, ax
bndcl bnd1, [0x399]
bndcl bnd1, [r9+0x3]
bndcl bnd1, [rax+0x3]
bndcl bnd1, [1*r12+0x3]
bndcl bnd1, [rax+rcx]
bndcl bnd1, [r11+1*rax+0x3]
bndcl bnd1, [rbx+1*r9+0x3]
### bndcu
bndcu bnd1, [r11]
bndcu bnd1, [rax]
bndcu bnd1, r11
bndcu bnd1, rcx
bndcu bnd1, ax
bndcu bnd1, [0x399]
bndcu bnd1, [r9+0x3]
bndcu bnd1, [rax+0x3]
bndcu bnd1, [1*r12+0x3]
bndcu bnd1, [rax+rcx]
bndcu bnd1, [r11+1*rax+0x3]
bndcu bnd1, [rbx+1*r9+0x3]
### bndcn
bndcn bnd1, [r11]
bndcn bnd1, [rax]
bndcn bnd1, r11
bndcn bnd1, rcx
bndcn bnd1, ax
bndcn bnd1, [0x399]
bndcn bnd1, [r9+0x3]
bndcn bnd1, [rax+0x3]
bndcn bnd1, [1*r9+0x3]
bndcn bnd1, [rax+rcx]
bndcn bnd1, [r11+1*rax+0x3]
bndcn bnd1, [rbx+1*r9+0x3]
### bndstx
bndstx [rax+rbx*1+0x3], bnd0
bndstx [rbx+rdx+3], bnd2
bndstx [r12+0x399], bnd3
bndstx [r11+0x1234], bnd1
bndstx [rbx+0x1234], bnd2
bndstx [1*rbx+3], bnd2
bndstx [1*r12+3], bnd2
bndstx [rdx], bnd1
### bndldx
bndldx bnd0, [rax+rbx*1+0x3]
bndldx bnd2, [rbx+rdx+3]
bndldx bnd3, [r12+0x399]
bndldx bnd1, [r11+0x1234]
bndldx bnd2, [rbx+0x1234]
bndldx bnd2, [1*rbx+3]
bndldx bnd2, [1*r12+3]
bndldx bnd1, [rdx]
### bnd
bnd call foo
bnd call rax
bnd call r11
bnd je foo
bnd jmp foo
bnd jmp rcx
bnd jmp r12
bnd ret
foo: bnd ret

8
gas/testsuite/gas/i386/x86-64-nops.d
View File

@ -22,29 +22,21 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 1e ff nop %edi
[ ]*[a-f0-9]+: 0f 1f ff nop %edi
[ ]*[a-f0-9]+: 0f 19 5a 22 nopl 0x22\(%rdx\)
[ ]*[a-f0-9]+: 0f 1a 5a 22 nopl 0x22\(%rdx\)
[ ]*[a-f0-9]+: 0f 1b 5a 22 nopl 0x22\(%rdx\)
[ ]*[a-f0-9]+: 0f 1c 5a 22 nopl 0x22\(%rdx\)
[ ]*[a-f0-9]+: 0f 1d 5a 22 nopl 0x22\(%rdx\)
[ ]*[a-f0-9]+: 0f 1e 5a 22 nopl 0x22\(%rdx\)
[ ]*[a-f0-9]+: 0f 1f 5a 22 nopl 0x22\(%rdx\)
[ ]*[a-f0-9]+: 0f 19 9c 1d 11 22 33 44 nopl 0x44332211\(%rbp,%rbx,1\)
[ ]*[a-f0-9]+: 0f 1a 9c 1d 11 22 33 44 nopl 0x44332211\(%rbp,%rbx,1\)
[ ]*[a-f0-9]+: 0f 1b 9c 1d 11 22 33 44 nopl 0x44332211\(%rbp,%rbx,1\)
[ ]*[a-f0-9]+: 0f 1c 9c 1d 11 22 33 44 nopl 0x44332211\(%rbp,%rbx,1\)
[ ]*[a-f0-9]+: 0f 1d 9c 1d 11 22 33 44 nopl 0x44332211\(%rbp,%rbx,1\)
[ ]*[a-f0-9]+: 0f 1e 9c 1d 11 22 33 44 nopl 0x44332211\(%rbp,%rbx,1\)
[ ]*[a-f0-9]+: 0f 1f 9c 1d 11 22 33 44 nopl 0x44332211\(%rbp,%rbx,1\)
[ ]*[a-f0-9]+: 0f 19 04 60 nopl \(%rax,%riz,2\)
[ ]*[a-f0-9]+: 0f 1a 04 60 nopl \(%rax,%riz,2\)
[ ]*[a-f0-9]+: 0f 1b 04 60 nopl \(%rax,%riz,2\)
[ ]*[a-f0-9]+: 0f 1c 04 60 nopl \(%rax,%riz,2\)
[ ]*[a-f0-9]+: 0f 1d 04 60 nopl \(%rax,%riz,2\)
[ ]*[a-f0-9]+: 0f 1e 04 60 nopl \(%rax,%riz,2\)
[ ]*[a-f0-9]+: 0f 1f 04 60 nopl \(%rax,%riz,2\)
[ ]*[a-f0-9]+: 0f 19 04 59 nopl \(%rcx,%rbx,2\)
[ ]*[a-f0-9]+: 0f 1a 04 59 nopl \(%rcx,%rbx,2\)
[ ]*[a-f0-9]+: 0f 1b 04 59 nopl \(%rcx,%rbx,2\)
[ ]*[a-f0-9]+: 0f 1c 04 59 nopl \(%rcx,%rbx,2\)
[ ]*[a-f0-9]+: 0f 1d 04 59 nopl \(%rcx,%rbx,2\)
[ ]*[a-f0-9]+: 0f 1e 04 59 nopl \(%rcx,%rbx,2\)

8
gas/testsuite/gas/i386/x86-64-nops.s
View File

@ -20,8 +20,6 @@
# with base and imm8
.byte 0x0f, 0x19, 0x5A, 0x22
.byte 0x0f, 0x1a, 0x5A, 0x22
.byte 0x0f, 0x1b, 0x5A, 0x22
.byte 0x0f, 0x1c, 0x5A, 0x22
.byte 0x0f, 0x1d, 0x5A, 0x22
.byte 0x0f, 0x1e, 0x5A, 0x22
@ -29,24 +27,18 @@
# with sib and imm32
.byte 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44
.byte 0x0f, 0x1a, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44
.byte 0x0f, 0x1b, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44
.byte 0x0f, 0x1c, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44
.byte 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44
.byte 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44
.byte 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44
.byte 0x0f, 0x19, 0x04, 0x60
.byte 0x0f, 0x1a, 0x04, 0x60
.byte 0x0f, 0x1b, 0x04, 0x60
.byte 0x0f, 0x1c, 0x04, 0x60
.byte 0x0f, 0x1d, 0x04, 0x60
.byte 0x0f, 0x1e, 0x04, 0x60
.byte 0x0f, 0x1f, 0x04, 0x60
.byte 0x0f, 0x19, 0x04, 0x59
.byte 0x0f, 0x1a, 0x04, 0x59
.byte 0x0f, 0x1b, 0x04, 0x59
.byte 0x0f, 0x1c, 0x04, 0x59
.byte 0x0f, 0x1d, 0x04, 0x59
.byte 0x0f, 0x1e, 0x04, 0x59

6
include/opcode/ChangeLog
View File

@ -1,3 +1,9 @@
2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* i386.h (BND_PREFIX_OPCODE): New.
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
* mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and

1
include/opcode/i386.h
View File

@ -78,6 +78,7 @@
#define REPE_PREFIX_OPCODE 0xf3
#define XACQUIRE_PREFIX_OPCODE 0xf2
#define XRELEASE_PREFIX_OPCODE 0xf3
#define BND_PREFIX_OPCODE 0xf2
#define TWO_BYTE_OPCODE_ESCAPE 0x0f
#define NOP_OPCODE (char) 0x90

45
opcodes/ChangeLog
View File

@ -1,3 +1,48 @@
2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* i386-dis.c (BND_Fixup): New.
(Ebnd): New.
(Ev_bnd): New.
(Gbnd): New.
(BND): New.
(v_bnd_mode): New.
(bnd_mode): New.
(MOD enum): Add new entries.
(PREFIX enum): Likewise.
(dis tables): Replace XX with BND for near branch and call
instructions.
(prefix_table): Add new entries.
(mod_table): Likewise.
(names_bnd): New.
(intel_names_bnd): New.
(att_names_bnd): New.
(BND_PREFIX): New.
(prefix_name): Handle BND_PREFIX.
(print_insn): Initialize names_bnd.
(intel_operand_size): Handle new modes.
(OP_E_register): Likewise.
(OP_E_memory): Likewise.
(OP_G): Likewise.
* i386-gen.c (cpu_flag_init): Add CpuMPX.
(cpu_flags): Add CpuMPX.
(operand_type_init): Add RegBND.
(opcode_modifiers): Add BNDPrefixOk.
(operand_types): Add RegBND.
* i386-init.h: Regenerate.
* i386-opc.h (CpuMPX): New.
(CpuUnused): Comment out.
(i386_cpu_flags): Add cpumpx.
(BNDPrefixOk): New.
(i386_opcode_modifier): Add bndprefixok.
(RegBND): New.
(i386_operand_type): Add regbnd.
* i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
Add MPX instructions and bnd prefix.
* i386-reg.tbl: Add bnd0-bnd3 registers.
* i386-tbl.h: Regenerate.
2013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
* mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add

173
opcodes/i386-dis.c
View File

@ -108,6 +108,7 @@ static void OP_3DNowSuffix (int, int);
static void CMP_Fixup (int, int);
static void BadOp (void);
static void REP_Fixup (int, int);
static void BND_Fixup (int, int);
static void HLE_Fixup1 (int, int);
static void HLE_Fixup2 (int, int);
static void HLE_Fixup3 (int, int);
@ -222,8 +223,10 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define Bad_Opcode NULL, { { NULL, 0 } }
#define Eb { OP_E, b_mode }
#define Ebnd { OP_E, bnd_mode }
#define EbS { OP_E, b_swap_mode }
#define Ev { OP_E, v_mode }
#define Ev_bnd { OP_E, v_bnd_mode }
#define EvS { OP_E, v_swap_mode }
#define Ed { OP_E, d_mode }
#define Edq { OP_E, dq_mode }
@ -246,6 +249,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define Mx { OP_M, x_mode }
#define Mxmm { OP_M, xmm_mode }
#define Gb { OP_G, b_mode }
#define Gbnd { OP_G, bnd_mode }
#define Gv { OP_G, v_mode }
#define Gd { OP_G, d_mode }
#define Gdq { OP_G, dq_mode }
@ -423,6 +427,8 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define Ebh3 { HLE_Fixup3, b_mode }
#define Evh3 { HLE_Fixup3, v_mode }
#define BND { BND_Fixup, 0 }
#define cond_jump_flag { NULL, cond_jump_mode }
#define loop_jcxz_flag { NULL, loop_jcxz_mode }
@ -485,10 +491,12 @@ enum
a_mode,
cond_jump_mode,
loop_jcxz_mode,
v_bnd_mode,
/* operand size depends on REX prefixes. */
dq_mode,
/* registers like dq_mode, memory like w_mode. */
dqw_mode,
bnd_mode,
/* 4- or 6-byte pointer operand */
f_mode,
const_1_mode,
@ -672,6 +680,9 @@ enum
MOD_0F18_REG_5,
MOD_0F18_REG_6,
MOD_0F18_REG_7,
MOD_0F1A_PREFIX_0,
MOD_0F1B_PREFIX_0,
MOD_0F1B_PREFIX_1,
MOD_0F20,
MOD_0F21,
MOD_0F22,
@ -766,6 +777,8 @@ enum
PREFIX_0F11,
PREFIX_0F12,
PREFIX_0F16,
PREFIX_0F1A,
PREFIX_0F1B,
PREFIX_0F2A,
PREFIX_0F2B,
PREFIX_0F2C,
@ -1800,23 +1813,23 @@ static const struct dis386 dis386[] = {
{ "outs{b|}", { indirDXr, Xb } },
{ X86_64_TABLE (X86_64_6F) },
/* 70 */
{ "joH", { Jb, XX, cond_jump_flag } },
{ "jnoH", { Jb, XX, cond_jump_flag } },
{ "jbH", { Jb, XX, cond_jump_flag } },
{ "jaeH", { Jb, XX, cond_jump_flag } },
{ "jeH", { Jb, XX, cond_jump_flag } },
{ "jneH", { Jb, XX, cond_jump_flag } },
{ "jbeH", { Jb, XX, cond_jump_flag } },
{ "jaH", { Jb, XX, cond_jump_flag } },
{ "joH", { Jb, BND, cond_jump_flag } },
{ "jnoH", { Jb, BND, cond_jump_flag } },
{ "jbH", { Jb, BND, cond_jump_flag } },
{ "jaeH", { Jb, BND, cond_jump_flag } },
{ "jeH", { Jb, BND, cond_jump_flag } },
{ "jneH", { Jb, BND, cond_jump_flag } },
{ "jbeH", { Jb, BND, cond_jump_flag } },
{ "jaH", { Jb, BND, cond_jump_flag } },
/* 78 */
{ "jsH", { Jb, XX, cond_jump_flag } },
{ "jnsH", { Jb, XX, cond_jump_flag } },
{ "jpH", { Jb, XX, cond_jump_flag } },
{ "jnpH", { Jb, XX, cond_jump_flag } },
{ "jlH", { Jb, XX, cond_jump_flag } },
{ "jgeH", { Jb, XX, cond_jump_flag } },
{ "jleH", { Jb, XX, cond_jump_flag } },
{ "jgH", { Jb, XX, cond_jump_flag } },
{ "jsH", { Jb, BND, cond_jump_flag } },
{ "jnsH", { Jb, BND, cond_jump_flag } },
{ "jpH", { Jb, BND, cond_jump_flag } },
{ "jnpH", { Jb, BND, cond_jump_flag } },
{ "jlH", { Jb, BND, cond_jump_flag } },
{ "jgeH", { Jb, BND, cond_jump_flag } },
{ "jleH", { Jb, BND, cond_jump_flag } },
{ "jgH", { Jb, BND, cond_jump_flag } },
/* 80 */
{ REG_TABLE (REG_80) },
{ REG_TABLE (REG_81) },
@ -1892,8 +1905,8 @@ static const struct dis386 dis386[] = {
/* c0 */
{ REG_TABLE (REG_C0) },
{ REG_TABLE (REG_C1) },
{ "retT", { Iw } },
{ "retT", { XX } },
{ "retT", { Iw, BND } },
{ "retT", { BND } },
{ X86_64_TABLE (X86_64_C4) },
{ X86_64_TABLE (X86_64_C5) },
{ REG_TABLE (REG_C6) },
@ -1935,10 +1948,10 @@ static const struct dis386 dis386[] = {
{ "outB", { Ib, AL } },
{ "outG", { Ib, zAX } },
/* e8 */
{ "callT", { Jv } },
{ "jmpT", { Jv } },
{ "callT", { Jv, BND } },
{ "jmpT", { Jv, BND } },
{ X86_64_TABLE (X86_64_EA) },
{ "jmp", { Jb } },
{ "jmp", { Jb, BND } },
{ "inB", { AL, indirDX } },
{ "inG", { zAX, indirDX } },
{ "outB", { indirDX, AL } },
@ -1994,8 +2007,8 @@ static const struct dis386 dis386_twobyte[] = {
/* 18 */
{ REG_TABLE (REG_0F18) },
{ "nopQ", { Ev } },
{ "nopQ", { Ev } },
{ "nopQ", { Ev } },
{ PREFIX_TABLE (PREFIX_0F1A) },
{ PREFIX_TABLE (PREFIX_0F1B) },
{ "nopQ", { Ev } },
{ "nopQ", { Ev } },
{ "nopQ", { Ev } },
@ -2109,23 +2122,23 @@ static const struct dis386 dis386_twobyte[] = {
{ PREFIX_TABLE (PREFIX_0F7E) },
{ PREFIX_TABLE (PREFIX_0F7F) },
/* 80 */
{ "joH", { Jv, XX, cond_jump_flag } },
{ "jnoH", { Jv, XX, cond_jump_flag } },
{ "jbH", { Jv, XX, cond_jump_flag } },
{ "jaeH", { Jv, XX, cond_jump_flag } },
{ "jeH", { Jv, XX, cond_jump_flag } },
{ "jneH", { Jv, XX, cond_jump_flag } },
{ "jbeH", { Jv, XX, cond_jump_flag } },
{ "jaH", { Jv, XX, cond_jump_flag } },
{ "joH", { Jv, BND, cond_jump_flag } },
{ "jnoH", { Jv, BND, cond_jump_flag } },
{ "jbH", { Jv, BND, cond_jump_flag } },
{ "jaeH", { Jv, BND, cond_jump_flag } },
{ "jeH", { Jv, BND, cond_jump_flag } },
{ "jneH", { Jv, BND, cond_jump_flag } },
{ "jbeH", { Jv, BND, cond_jump_flag } },
{ "jaH", { Jv, BND, cond_jump_flag } },
/* 88 */
{ "jsH", { Jv, XX, cond_jump_flag } },
{ "jnsH", { Jv, XX, cond_jump_flag } },
{ "jpH", { Jv, XX, cond_jump_flag } },
{ "jnpH", { Jv, XX, cond_jump_flag } },
{ "jlH", { Jv, XX, cond_jump_flag } },
{ "jgeH", { Jv, XX, cond_jump_flag } },
{ "jleH", { Jv, XX, cond_jump_flag } },
{ "jgH", { Jv, XX, cond_jump_flag } },
{ "jsH", { Jv, BND, cond_jump_flag } },
{ "jnsH", { Jv, BND, cond_jump_flag } },
{ "jpH", { Jv, BND, cond_jump_flag } },
{ "jnpH", { Jv, BND, cond_jump_flag } },
{ "jlH", { Jv, BND, cond_jump_flag } },
{ "jgeH", { Jv, BND, cond_jump_flag } },
{ "jleH", { Jv, BND, cond_jump_flag } },
{ "jgH", { Jv, BND, cond_jump_flag } },
/* 90 */
{ "seto", { Eb } },
{ "setno", { Eb } },
@ -2366,6 +2379,7 @@ static const char **names_seg;
static const char *index64;
static const char *index32;
static const char **index16;
static const char **names_bnd;
static const char *intel_names64[] = {
"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
@ -2433,6 +2447,14 @@ static const char *att_names_mm[] = {
"%mm4", "%mm5", "%mm6", "%mm7"
};
static const char *intel_names_bnd[] = {
"bnd0", "bnd1", "bnd2", "bnd3"
};
static const char *att_names_bnd[] = {
"%bnd0", "%bnd1", "%bnd2", "%bnd3"
};
static const char **names_xmm;
static const char *intel_names_xmm[] = {
"xmm0", "xmm1", "xmm2", "xmm3",
@ -2623,9 +2645,9 @@ static const struct dis386 reg_table[][8] = {
{
{ "incQ", { Evh1 } },
{ "decQ", { Evh1 } },
{ "call{T|}", { indirEv } },
{ "call{T|}", { indirEv, BND } },
{ "Jcall{T|}", { indirEp } },
{ "jmp{T|}", { indirEv } },
{ "jmp{T|}", { indirEv, BND } },
{ "Jjmp{T|}", { indirEp } },
{ "pushU", { stackEv } },
{ Bad_Opcode },
@ -2870,6 +2892,22 @@ static const struct dis386 prefix_table[][4] = {
{ "movhpd", { XM, EXq } },
},
/* PREFIX_0F1A */
{
{ MOD_TABLE (MOD_0F1A_PREFIX_0) },
{ "bndcl", { Gbnd, Ev_bnd } },
{ "bndmov", { Gbnd, Ebnd } },
{ "bndcu", { Gbnd, Ev_bnd } },
},
/* PREFIX_0F1B */
{
{ MOD_TABLE (MOD_0F1B_PREFIX_0) },
{ MOD_TABLE (MOD_0F1B_PREFIX_1) },
{ "bndmov", { Ebnd, Gbnd } },
{ "bndcn", { Gbnd, Ev_bnd } },
},
/* PREFIX_0F2A */
{
{ "cvtpi2ps", { XM, EMCq } },
@ -10250,6 +10288,21 @@ static const struct dis386 mod_table[][2] = {
/* MOD_0F18_REG_7 */
{ "nop/reserved", { Mb } },
},
{
/* MOD_0F1A_PREFIX_0 */
{ "bndldx", { Gbnd, Ev_bnd } },
{ "nopQ", { Ev } },
},
{
/* MOD_0F1B_PREFIX_0 */
{ "bndstx", { Ev_bnd, Gbnd } },
{ "nopQ", { Ev } },
},
{
/* MOD_0F1B_PREFIX_1 */
{ "bndmk", { Gbnd, Ev_bnd } },
{ "nopQ", { Ev } },
},
{
/* MOD_0F20 */
{ Bad_Opcode },
@ -10655,6 +10708,7 @@ static const struct dis386 rm_table[][8] = {
#define REP_PREFIX (0xf3 | 0x100)
#define XACQUIRE_PREFIX (0xf2 | 0x200)
#define XRELEASE_PREFIX (0xf3 | 0x400)
#define BND_PREFIX (0xf2 | 0x400)
static int
ckprefix (void)
@ -10892,6 +10946,8 @@ prefix_name (int pref, int sizeflag)
return "xacquire";
case XRELEASE_PREFIX:
return "xrelease";
case BND_PREFIX:
return "bnd";
default:
return NULL;
}
@ -11397,6 +11453,7 @@ print_insn (bfd_vma pc, disassemble_info *info)
names8rex = intel_names8rex;
names_seg = intel_names_seg;
names_mm = intel_names_mm;
names_bnd = intel_names_bnd;
names_xmm = intel_names_xmm;
names_ymm = intel_names_ymm;
index64 = intel_index64;
@ -11416,6 +11473,7 @@ print_insn (bfd_vma pc, disassemble_info *info)
names8rex = att_names8rex;
names_seg = att_names_seg;
names_mm = att_names_mm;
names_bnd = att_names_bnd;
names_xmm = att_names_xmm;
names_ymm = att_names_ymm;
index64 = att_index64;
@ -12766,6 +12824,7 @@ intel_operand_size (int bytemode, int sizeflag)
}
/* FALLTHRU */
case v_mode:
case v_bnd_mode:
case v_swap_mode:
case dq_mode:
USED_REX (REX_W);
@ -13035,6 +13094,9 @@ OP_E_register (int bytemode, int sizeflag)
case m_mode:
names = address_mode == mode_64bit ? names64 : names32;
break;
case bnd_mode:
names = names_bnd;
break;
case stack_v_mode:
if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
{
@ -13044,6 +13106,7 @@ OP_E_register (int bytemode, int sizeflag)
bytemode = v_mode;
/* FALLTHRU */
case v_mode:
case v_bnd_mode:
case v_swap_mode:
case dq_mode:
case dqb_mode:
@ -13095,6 +13158,9 @@ OP_E_memory (int bytemode, int sizeflag)
int base, rbase;
int vindex = 0;
int scale = 0;
int addr32flag = !((sizeflag & AFLAG)
|| bytemode == v_bnd_mode
|| bytemode == bnd_mode);
const char **indexes64 = names64;
const char **indexes32 = names32;
@ -13190,7 +13256,9 @@ OP_E_memory (int bytemode, int sizeflag)
}
}
if (havebase || haveindex || riprel)
if ((havebase || haveindex || riprel)
&& (bytemode != v_bnd_mode)
&& (bytemode != bnd_mode))
used_prefixes |= PREFIX_ADDR;
if (havedisp || (intel_syntax && riprel))
@ -13203,7 +13271,7 @@ OP_E_memory (int bytemode, int sizeflag)
}
*obufp = '\0';
if (havebase)
oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
oappend (address_mode == mode_64bit && !addr32flag
? names64[rbase] : names32[rbase]);
if (havesib)
{
@ -13220,12 +13288,10 @@ OP_E_memory (int bytemode, int sizeflag)
*obufp = '\0';
}
if (haveindex)
oappend (address_mode == mode_64bit
&& (sizeflag & AFLAG)
oappend (address_mode == mode_64bit && !addr32flag
? indexes64[vindex] : indexes32[vindex]);
else
oappend (address_mode == mode_64bit
&& (sizeflag & AFLAG)
oappend (address_mode == mode_64bit && !addr32flag
? index64 : index32);
*obufp++ = scale_char;
@ -13391,6 +13457,9 @@ OP_G (int bytemode, int sizeflag)
case q_mode:
oappend (names64[modrm.reg + add]);
break;
case bnd_mode:
oappend (names_bnd[modrm.reg]);
break;
case v_mode:
case dq_mode:
case dqb_mode:
@ -14521,6 +14590,16 @@ REP_Fixup (int bytemode, int sizeflag)
}
}
/* For BND-prefixed instructions 0xF2 prefix should be displayed as
"bnd". */
static void
BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
{
if (prefixes & PREFIX_REPNZ)
all_prefixes[last_repnz_prefix] = BND_PREFIX;
}
/* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
"xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
*/

7
opcodes/i386-gen.c
View File

@ -208,6 +208,8 @@ static initializer cpu_flag_init[] =
"CpuPRFCHW" },
{ "CPU_SMAP_FLAGS",
"CpuSMAP" },
{ "CPU_MPX_FLAGS",
"CpuMPX" },
};
static initializer operand_type_init[] =
@ -308,6 +310,8 @@ static initializer operand_type_init[] =
"Imm32|Imm32S|Imm64|Disp32|Disp64" },
{ "OPERAND_TYPE_VEC_IMM4",
"Vec_Imm4" },
{ "OPERAND_TYPE_REGBND",
"RegBND" },
};
typedef struct bitfield
@ -384,6 +388,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuSMAP),
BITFIELD (Cpu64),
BITFIELD (CpuNo64),
BITFIELD (CpuMPX),
#ifdef CpuUnused
BITFIELD (CpuUnused),
#endif
@ -417,6 +422,7 @@ static bitfield opcode_modifiers[] =
BITFIELD (No_ldSuf),
BITFIELD (FWait),
BITFIELD (IsString),
BITFIELD (BNDPrefixOk),
BITFIELD (IsLockable),
BITFIELD (RegKludge),
BITFIELD (FirstXmm0),
@ -493,6 +499,7 @@ static bitfield operand_types[] =
BITFIELD (Unspecified),
BITFIELD (Anysize),
BITFIELD (Vec_Imm4),
BITFIELD (RegBND),
#ifdef OTUnused
BITFIELD (OTUnused),
#endif

171
opcodes/i386-init.h
View File

@ -23,7 +23,7 @@
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 0, 1, 1 } }
1, 1, 0, 1 } }
#define CPU_GENERIC32_FLAGS \
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@ -34,7 +34,7 @@
#define CPU_GENERIC64_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0, 0 } }
#define CPU_NONE_FLAGS \
@ -106,7 +106,7 @@
#define CPU_NOCONA_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0, 0 } }
#define CPU_CORE_FLAGS \
@ -118,13 +118,13 @@
#define CPU_CORE2_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0, 0 } }
#define CPU_COREI7_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0, 0 } }
#define CPU_K6_FLAGS \
@ -148,44 +148,44 @@
#define CPU_K8_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0, 0 } }
#define CPU_AMDFAM10_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0, 0 } }
#define CPU_BDVER1_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, \
1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, \
0, 0, 0, 0 } }
1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, \
1, 0, 0, 0 } }
#define CPU_BDVER2_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, \
1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, \
0, 0, 0, 0 } }
1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, \
1, 0, 0, 0 } }
#define CPU_BDVER3_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, \
0, 0, 0, 0 } }
1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, \
1, 0, 0, 0 } }
#define CPU_BTVER1_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, \
0, 0, 0, 0 } }
0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, \
1, 0, 0, 0 } }
#define CPU_BTVER2_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, \
0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, \
0, 0, 0, 0 } }
0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, \
1, 0, 0, 0 } }
#define CPU_8087_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@ -485,275 +485,286 @@
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 0, 1, 1 } }
1, 1, 0, 1 } }
#define CPU_K1OM_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 0, 1, 1 } }
1, 1, 0, 1 } }
#define CPU_ADX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
0, 0, 0, 0 } }
#define CPU_RDSEED_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0, 0 } }
#define CPU_PRFCHW_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
0, 0, 0, 0 } }
#define CPU_SMAP_FLAGS \
#define CPU_RDSEED_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
0, 0, 0, 0 } }
#define CPU_PRFCHW_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 0, 0, 0 } }
#define CPU_SMAP_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 1, 0, 0 } }
#define CPU_MPX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0 } }
#define OPERAND_TYPE_NONE \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REG8 \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REG16 \
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REG32 \
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REG64 \
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM1 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM8 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM8S \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM16 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32S \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM64 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_BASEINDEX \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DISP8 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DISP16 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DISP32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DISP32S \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DISP64 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_INOUTPORTREG \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_SHIFTCOUNT \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_CONTROL \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_TEST \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DEBUG \
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_FLOATREG \
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_FLOATACC \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_SREG2 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_SREG3 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_ACC \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_JUMPABSOLUTE \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REGMMX \
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REGXMM \
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REGYMM \
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_ESSEG \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_ACC32 \
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_ACC64 \
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_INOUTPORTREG \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REG16_INOUTPORTREG \
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DISP16_32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_ANYDISP \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM16_32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM16_32S \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM16_32_32S \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32_64 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32_32S_DISP32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM64_DISP64 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32_32S_64_DISP32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32_32S_64_DISP32_64 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_VEC_IMM4 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 0 } }
0, 0, 0, 0, 1, 0, 0 } }
#define OPERAND_TYPE_REGBND \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 1, 0 } }

12
opcodes/i386-opc.h
View File

@ -144,6 +144,8 @@ enum
CpuINVPCID,
/* VMFUNC Instruction required */
CpuVMFUNC,
/* Intel MPX Instructions required */
CpuMPX,
/* 64bit support available, used by -march= in assembler. */
CpuLM,
/* RDRSEED instruction required. */
@ -169,7 +171,7 @@ enum
/* If you get a compiler error for zero width of the unused field,
comment it out. */
#define CpuUnused (CpuMax + 1)
/* #define CpuUnused (CpuMax + 1) */
/* We can check if an instruction is available with array instead
of bitfield. */
@ -233,6 +235,7 @@ typedef union i386_cpu_flags
unsigned int cpurtm:1;
unsigned int cpuinvpcid:1;
unsigned int cpuvmfunc:1;
unsigned int cpumpx:1;
unsigned int cpulm:1;
unsigned int cpurdseed:1;
unsigned int cpuadx:1;
@ -305,6 +308,8 @@ enum
FWait,
/* quick test for string instructions */
IsString,
/* quick test if branch instruction is MPX supported */
BNDPrefixOk,
/* quick test for lockable instructions */
IsLockable,
/* fake an extra reg operand for clr, imul and special register
@ -455,6 +460,7 @@ typedef struct i386_opcode_modifier
unsigned int no_ldsuf:1;
unsigned int fwait:1;
unsigned int isstring:1;
unsigned int bndprefixok:1;
unsigned int islockable:1;
unsigned int regkludge:1;
unsigned int firstxmm0:1;
@ -591,6 +597,9 @@ enum
/* Vector 4 bit immediate. */
Vec_Imm4,
/* Bound register. */
RegBND,
/* The last bitfield in i386_operand_type. */
OTMax
};
@ -653,6 +662,7 @@ typedef union i386_operand_type
unsigned int unspecified:1;
unsigned int anysize:1;
unsigned int vec_imm4:1;
unsigned int regbnd:1;
#ifdef OTUnused
unsigned int unused:(OTNumOfBits - OTUnused);
#endif

95
opcodes/i386-opc.tbl
View File

@ -319,10 +319,10 @@ shrd, 3, 0xfad, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, {
shrd, 2, 0xfad, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
// Control transfer instructions.
call, 1, 0xe8, None, 1, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp16|Disp32 }
call, 1, 0xe8, None, 1, Cpu64, JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Disp16|Disp32|Disp32S }
call, 1, 0xff, 0x2, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute }
call, 1, 0xff, 0x2, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
call, 1, 0xe8, None, 1, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp16|Disp32 }
call, 1, 0xe8, None, 1, Cpu64, JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32|Disp32S }
call, 1, 0xff, 0x2, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute }
call, 1, 0xff, 0x2, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
// Intel Syntax
call, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
// Intel Syntax
@ -330,9 +330,9 @@ call, 1, 0xff, 0x3, 1, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q
lcall, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
lcall, 1, 0xff, 0x3, 1, 0, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute }
jmp, 1, 0xeb, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jmp, 1, 0xff, 0x4, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute }
jmp, 1, 0xff, 0x4, 1, Cpu64, Modrm|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
jmp, 1, 0xeb, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jmp, 1, 0xff, 0x4, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute }
jmp, 1, 0xff, 0x4, 1, Cpu64, Modrm|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
// Intel Syntax.
jmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
// Intel Syntax.
@ -340,10 +340,10 @@ jmp, 1, 0xff, 0x5, 1, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|
ljmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
ljmp, 1, 0xff, 0x5, 1, 0, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute }
ret, 0, 0xc3, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk, { 0 }
ret, 1, 0xc2, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk, { Imm16 }
ret, 0, 0xc3, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk, { 0 }
ret, 1, 0xc2, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk, { Imm16 }
ret, 0, 0xc3, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, { 0 }
ret, 1, 0xc2, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, { Imm16 }
ret, 0, 0xc3, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { 0 }
ret, 1, 0xc2, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
lret, 0, 0xcb, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { 0 }
lret, 1, 0xca, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { Imm16 }
// Intel Syntax.
@ -356,36 +356,36 @@ leave, 0, 0xc9, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_
leave, 0, 0xc9, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { 0 }
// Conditional jumps.
jo, 1, 0x70, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jno, 1, 0x71, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jb, 1, 0x72, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jc, 1, 0x72, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jnae, 1, 0x72, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jnb, 1, 0x73, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jnc, 1, 0x73, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jae, 1, 0x73, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
je, 1, 0x74, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jz, 1, 0x74, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jne, 1, 0x75, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jnz, 1, 0x75, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jbe, 1, 0x76, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jna, 1, 0x76, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jnbe, 1, 0x77, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
ja, 1, 0x77, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
js, 1, 0x78, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jns, 1, 0x79, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jp, 1, 0x7a, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jpe, 1, 0x7a, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jnp, 1, 0x7b, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jpo, 1, 0x7b, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jl, 1, 0x7c, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jnge, 1, 0x7c, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jnl, 1, 0x7d, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jge, 1, 0x7d, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jle, 1, 0x7e, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jng, 1, 0x7e, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jnle, 1, 0x7f, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jg, 1, 0x7f, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
jo, 1, 0x70, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jno, 1, 0x71, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jb, 1, 0x72, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jc, 1, 0x72, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jnae, 1, 0x72, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jnb, 1, 0x73, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jnc, 1, 0x73, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jae, 1, 0x73, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
je, 1, 0x74, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jz, 1, 0x74, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jne, 1, 0x75, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jnz, 1, 0x75, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jbe, 1, 0x76, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jna, 1, 0x76, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jnbe, 1, 0x77, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
ja, 1, 0x77, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
js, 1, 0x78, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jns, 1, 0x79, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jp, 1, 0x7a, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jpe, 1, 0x7a, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jnp, 1, 0x7b, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jpo, 1, 0x7b, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jl, 1, 0x7c, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jnge, 1, 0x7c, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jnl, 1, 0x7d, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jge, 1, 0x7d, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jle, 1, 0x7e, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jng, 1, 0x7e, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jnle, 1, 0x7f, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
jg, 1, 0x7f, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
// jcxz vs. jecxz is chosen on the basis of the address size prefix.
jcxz, 1, 0xe3, None, 1, CpuNo64, JumpByte|Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
@ -3056,3 +3056,16 @@ rdseed, 1, 0xfc7, 0x7, 2, CpuRdSeed, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS
// SMAP instructions.
clac, 0, 0xf01, 0xca, 2, CpuSMAP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
stac, 0, 0xf01, 0xcb, 2, CpuSMAP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
// BND prefix
bnd, 0, 0xf2, None, 1, CpuMPX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
// MPX instructions.
bndmk, 2, 0xf30f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
bndmov, 2, 0x660f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegBND, RegBND }
bndmov, 2, 0x660f1b, None, 2, CpuMPX, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegBND }
bndcl, 2, 0xf30f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
bndcu, 2, 0xf20f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
bndcn, 2, 0xf20f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
bndstx, 2, 0x0f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
bndldx, 2, 0x0f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }

5
opcodes/i386-reg.tbl
View File

@ -205,6 +205,11 @@ ymm12, RegYMM, RegRex, 4, Dw2Inval, Dw2Inval
ymm13, RegYMM, RegRex, 5, Dw2Inval, Dw2Inval
ymm14, RegYMM, RegRex, 6, Dw2Inval, Dw2Inval
ymm15, RegYMM, RegRex, 7, Dw2Inval, Dw2Inval
// Bound registers for MPX
bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval
bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval
bnd2, RegBND, 0, 2, Dw2Inval, Dw2Inval
bnd3, RegBND, 0, 3, Dw2Inval, Dw2Inval
// No type will make these registers rejected for all purposes except
// for addressing. This saves creating one extra type for RIP/EIP.
rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16

20179
opcodes/i386-tbl.h
View File

File diff suppressed because it is too large Load Diff