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2013-06-17 Catherine Moore <clm@codesourcery.com>

Browse Source 
Maciej W. Rozycki  <macro@codesourcery.com>
	    Chao-Ying Fu  <fu@mips.com>

	gas/testsuite/
	* gas/mips/mips.exp: Run new tests.
	* gas/mips/eva.d: New.
	* gas/mips/eva.s: New.
	* gas/mips/micromips@eva.d: New.

	gas/
	* config/tc-mips.c (mips_set_options): Add ase_eva.
	(mips_set_options mips_opts): Add ase_eva.
	(file_ase_eva): Declare.
	(ISA_SUPPORTS_EVA_ASE): Define.
	(IS_SEXT_9BIT_NUM): Define.
	(MIPS_CPU_ASE_EVA): Define.
	(is_opcode_valid): Add support for ase_eva.
	(macro_build): Likewise.
	(macro): Likewise.
	(validate_mips_insn): Likewise.
	(validate_micromips_insn): Likewise.
	(mips_ip): Likewise.
	(options): Add OPTION_EVA and OPTION_NO_EVA.
	(md_longopts): Add -meva and -mno-eva.
	(md_parse_option): Process new options.
	(mips_after_parse_args): Check for valid EVA combinations.
	(s_mipsset): Likewise.

	include/
	* opcode/mips.h (OP_SH_EVAOFFSET): Define.
	(OP_MASK_EVAOFFSET): Define.
	(INSN_ASE_MASK): Delete.
	(ASE_EVA): Define.
	(M_CACHEE_AB, M_CACHEE_OB): New.
	(M_LBE_OB, M_LBE_AB): New.
	(M_LBUE_OB, M_LBUE_AB): New.
	(M_LHE_OB, M_LHE_AB): New.
	(M_LHUE_OB, M_LHUE_AB): New.
	(M_LLE_AB, M_LLE_OB): New.
	(M_LWE_OB, M_LWE_AB): New.
	(M_LWLE_AB, M_LWLE_OB): New.
	(M_LWRE_AB, M_LWRE_OB): New.
	(M_PREFE_AB, M_PREFE_OB): New.
	(M_SCE_AB, M_SCE_OB): New.
	(M_SBE_OB, M_SBE_AB): New.
	(M_SHE_OB, M_SHE_AB): New.
	(M_SWE_OB, M_SWE_AB): New.
	(M_SWLE_AB, M_SWLE_OB): New.
	(M_SWRE_AB, M_SWRE_OB): New.
	(MICROMIPSOP_SH_EVAOFFSET): Define.
	(MICROMIPSOP_MASK_EVAOFFSET): Define.

	opcodes/
	* micromips-opc.c (EVA): Define.
	(TLBINV): Define.
	(micromips_opcodes): Add EVA opcodes.
	* mips-dis.c (mips_arch_choices): Update for ASE_EVA.
	(print_insn_args): Handle EVA offsets.
	(print_insn_micromips): Likewise.
	* mips-opc.c (EVA): Define.
	(TLBINV): Define.
	(mips_builtin_opcodes): Add EVA opcodes.
This commit is contained in:
Catherine Moore 2013-06-17 22:59:10 +00:00
parent de40ceb6d5
commit 7f3c40729d
13 changed files with 3998 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
gas/ChangeLog
View File

@ -1,3 +1,25 @@
2013-06-17 Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
Chao-Ying Fu <fu@mips.com>
* config/tc-mips.c (mips_set_options): Add ase_eva.
(mips_set_options mips_opts): Add ase_eva.
(file_ase_eva): Declare.
(ISA_SUPPORTS_EVA_ASE): Define.
(IS_SEXT_9BIT_NUM): Define.
(MIPS_CPU_ASE_EVA): Define.
(is_opcode_valid): Add support for ase_eva.
(macro_build): Likewise.
(macro): Likewise.
(validate_mips_insn): Likewise.
(validate_micromips_insn): Likewise.
(mips_ip): Likewise.
(options): Add OPTION_EVA and OPTION_NO_EVA.
(md_longopts): Add -meva and -mno-eva.
(md_parse_option): Process new options.
(mips_after_parse_args): Check for valid EVA combinations.
(s_mipsset): Likewise.
2013-06-14 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
* dwarf2dbg.h (dwarf2_move_insn): Declare.

306
gas/config/tc-mips.c
View File

@ -216,6 +216,7 @@ struct mips_set_options
int ase_smartmips;
int ase_dsp;
int ase_dspr2;
int ase_eva;
int ase_mt;
int ase_mcu;
int ase_virt;
@ -292,8 +293,9 @@ static int file_mips_single_float = 0;
static struct mips_set_options mips_opts =
{
/* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
/* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
/* ase_mcu */ -1, /* ase_virt */ -1, /* mips16 */ -1,/* micromips */ -1,
/* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1,
/* ase_eva */ -1, /* ase_mt */ -1, /* ase_mcu */ -1,
/* ase_virt */ -1, /* mips16 */ -1, /* micromips */ -1,
/* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
/* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* gp32 */ 0,
/* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
@ -365,6 +367,14 @@ static int file_ase_dspr2;
|| mips_opts.isa == ISA_MIPS64R2 \
|| mips_opts.micromips)
/* True if -meva was passed or implied by arguments passed on the
command line (e.g., by -march). */
static int file_ase_eva;
#define ISA_SUPPORTS_EVA_ASE (mips_opts.isa == ISA_MIPS32R2 \
|| mips_opts.isa == ISA_MIPS64R2 \
|| mips_opts.micromips)
/* True if -mmt was passed or implied by arguments passed on the
command line (e.g., by -march). */
static int file_ase_mt;
@ -1217,6 +1227,10 @@ static int mips_relax_branch;
#define IS_SEXT_12BIT_NUM(x) \
(((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
/* Is the given value a sign-extended 9-bit value? */
#define IS_SEXT_9BIT_NUM(x) \
(((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
/* Is the given value a zero-extended 32-bit value? Or a negated one? */
#define IS_ZEXT_32BIT_NUM(x) \
(((x) &~ (offsetT) 0xffffffff) == 0 \
@ -1411,6 +1425,7 @@ struct mips_cpu_info
#define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
#define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
#define MIPS_CPU_ASE_VIRT 0x0100 /* CPU implements Virtualization ASE */
#define MIPS_CPU_ASE_EVA 0x0200 /* CPU implements EVA ASE */
static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
@ -2268,6 +2283,8 @@ is_opcode_valid (const struct mips_opcode *mo)
ase |= ASE_DSP64;
if (mips_opts.ase_dspr2)
ase |= ASE_DSPR2;
if (mips_opts.ase_eva)
ase |= ASE_EVA;
if (mips_opts.ase_mt)
ase |= ASE_MT;
if (mips_opts.ase_mips3d)
@ -5076,6 +5093,10 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
continue;
case 'j':
INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, insn, va_arg (args, int));
continue;
default:
abort ();
}
@ -6453,7 +6474,7 @@ macro (struct mips_cl_insn *ip)
const char *fmt;
int likely = 0;
int coproc = 0;
int off12 = 0;
int offbits = 16;
int call = 0;
int jals = 0;
int dbl = 0;
@ -6461,7 +6482,6 @@ macro (struct mips_cl_insn *ip)
int ust = 0;
int lp = 0;
int ab = 0;
int off0 = 0;
int off;
offsetT maxnum;
bfd_reloc_code_real_type r;
@ -8101,13 +8121,111 @@ macro (struct mips_cl_insn *ip)
break;
case M_LBUE_AB:
ab = 1;
case M_LBUE_OB:
s = "lbue";
fmt = "t,+j(b)";
offbits = 9;
goto ld_st;
case M_LHUE_AB:
ab = 1;
case M_LHUE_OB:
s = "lhue";
fmt = "t,+j(b)";
offbits = 9;
goto ld_st;
case M_LBE_AB:
ab = 1;
case M_LBE_OB:
s = "lbe";
fmt = "t,+j(b)";
offbits = 9;
goto ld_st;
case M_LHE_AB:
ab = 1;
case M_LHE_OB:
s = "lhe";
fmt = "t,+j(b)";
offbits = 9;
goto ld_st;
case M_LLE_AB:
ab = 1;
case M_LLE_OB:
s = "lle";
fmt = "t,+j(b)";
offbits = 9;
goto ld_st;
case M_LWE_AB:
ab = 1;
case M_LWE_OB:
s = "lwe";
fmt = "t,+j(b)";
offbits = 9;
goto ld_st;
case M_LWLE_AB:
ab = 1;
case M_LWLE_OB:
s = "lwle";
fmt = "t,+j(b)";
offbits = 9;
goto ld_st;
case M_LWRE_AB:
ab = 1;
case M_LWRE_OB:
s = "lwre";
fmt = "t,+j(b)";
offbits = 9;
goto ld_st;
case M_SBE_AB:
ab = 1;
case M_SBE_OB:
s = "sbe";
fmt = "t,+j(b)";
offbits = 9;
goto ld_st;
case M_SCE_AB:
ab = 1;
case M_SCE_OB:
s = "sce";
fmt = "t,+j(b)";
offbits = 9;
goto ld_st;
case M_SHE_AB:
ab = 1;
case M_SHE_OB:
s = "she";
fmt = "t,+j(b)";
offbits = 9;
goto ld_st;
case M_SWE_AB:
ab = 1;
case M_SWE_OB:
s = "swe";
fmt = "t,+j(b)";
offbits = 9;
goto ld_st;
case M_SWLE_AB:
ab = 1;
case M_SWLE_OB:
s = "swle";
fmt = "t,+j(b)";
offbits = 9;
goto ld_st;
case M_SWRE_AB:
ab = 1;
case M_SWRE_OB:
s = "swre";
fmt = "t,+j(b)";
offbits = 9;
goto ld_st;
case M_ACLR_AB:
ab = 1;
case M_ACLR_OB:
s = "aclr";
treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
fmt = "\\,~(b)";
off12 = 1;
offbits = 12;
goto ld_st;
case M_ASET_AB:
ab = 1;
@ -8115,7 +8233,7 @@ macro (struct mips_cl_insn *ip)
s = "aset";
treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
fmt = "\\,~(b)";
off12 = 1;
offbits = 12;
goto ld_st;
case M_LB_AB:
ab = 1;
@ -8162,7 +8280,7 @@ macro (struct mips_cl_insn *ip)
case M_LWC2_OB:
s = "lwc2";
fmt = COP12_FMT;
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
/* Itbl support may require additional care here. */
coproc = 1;
goto ld_st;
@ -8179,14 +8297,14 @@ macro (struct mips_cl_insn *ip)
case M_LWL_OB:
s = "lwl";
fmt = MEM12_FMT;
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_LWR_AB:
ab = 1;
case M_LWR_OB:
s = "lwr";
fmt = MEM12_FMT;
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_LDC1_AB:
ab = 1;
@ -8200,7 +8318,7 @@ macro (struct mips_cl_insn *ip)
case M_LDC2_OB:
s = "ldc2";
fmt = COP12_FMT;
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
/* Itbl support may require additional care here. */
coproc = 1;
goto ld_st;
@ -8223,35 +8341,35 @@ macro (struct mips_cl_insn *ip)
case M_LDL_OB:
s = "ldl";
fmt = MEM12_FMT;
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_LDR_AB:
ab = 1;
case M_LDR_OB:
s = "ldr";
fmt = MEM12_FMT;
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_LL_AB:
ab = 1;
case M_LL_OB:
s = "ll";
fmt = MEM12_FMT;
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
goto ld;
case M_LLD_AB:
ab = 1;
case M_LLD_OB:
s = "lld";
fmt = MEM12_FMT;
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
goto ld;
case M_LWU_AB:
ab = 1;
case M_LWU_OB:
s = "lwu";
fmt = MEM12_FMT;
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
goto ld;
case M_LWP_AB:
ab = 1;
@ -8259,7 +8377,7 @@ macro (struct mips_cl_insn *ip)
gas_assert (mips_opts.micromips);
s = "lwp";
fmt = "t,~(b)";
off12 = 1;
offbits = 12;
lp = 1;
goto ld;
case M_LDP_AB:
@ -8268,7 +8386,7 @@ macro (struct mips_cl_insn *ip)
gas_assert (mips_opts.micromips);
s = "ldp";
fmt = "t,~(b)";
off12 = 1;
offbits = 12;
lp = 1;
goto ld;
case M_LWM_AB:
@ -8277,7 +8395,7 @@ macro (struct mips_cl_insn *ip)
gas_assert (mips_opts.micromips);
s = "lwm";
fmt = "n,~(b)";
off12 = 1;
offbits = 12;
goto ld_st;
case M_LDM_AB:
ab = 1;
@ -8285,7 +8403,7 @@ macro (struct mips_cl_insn *ip)
gas_assert (mips_opts.micromips);
s = "ldm";
fmt = "n,~(b)";
off12 = 1;
offbits = 12;
goto ld_st;
ld:
@ -8331,7 +8449,7 @@ macro (struct mips_cl_insn *ip)
case M_SWC2_OB:
s = "swc2";
fmt = COP12_FMT;
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
/* Itbl support may require additional care here. */
coproc = 1;
goto ld_st;
@ -8348,42 +8466,56 @@ macro (struct mips_cl_insn *ip)
case M_SWL_OB:
s = "swl";
fmt = MEM12_FMT;
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_SWR_AB:
ab = 1;
case M_SWR_OB:
s = "swr";
fmt = MEM12_FMT;
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_SC_AB:
ab = 1;
case M_SC_OB:
s = "sc";
fmt = MEM12_FMT;
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_SCD_AB:
ab = 1;
case M_SCD_OB:
s = "scd";
fmt = MEM12_FMT;
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_CACHE_AB:
ab = 1;
case M_CACHE_OB:
s = "cache";
fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_CACHEE_AB:
ab = 1;
case M_CACHEE_OB:
s = "cachee";
fmt = "k,+j(b)";
offbits = 9;
goto ld_st;
case M_PREF_AB:
ab = 1;
case M_PREF_OB:
s = "pref";
fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_PREFE_AB:
ab = 1;
case M_PREFE_OB:
s = "prefe";
fmt = "k,+j(b)";
offbits = 9;
goto ld_st;
case M_SDC1_AB:
ab = 1;
@ -8397,7 +8529,7 @@ macro (struct mips_cl_insn *ip)
case M_SDC2_OB:
s = "sdc2";
fmt = COP12_FMT;
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
/* Itbl support may require additional care here. */
coproc = 1;
goto ld_st;
@ -8421,14 +8553,14 @@ macro (struct mips_cl_insn *ip)
case M_SDL_OB:
s = "sdl";
fmt = MEM12_FMT;
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_SDR_AB:
ab = 1;
case M_SDR_OB:
s = "sdr";
fmt = MEM12_FMT;
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_SWP_AB:
ab = 1;
@ -8436,7 +8568,7 @@ macro (struct mips_cl_insn *ip)
gas_assert (mips_opts.micromips);
s = "swp";
fmt = "t,~(b)";
off12 = 1;
offbits = 12;
goto ld_st;
case M_SDP_AB:
ab = 1;
@ -8444,7 +8576,7 @@ macro (struct mips_cl_insn *ip)
gas_assert (mips_opts.micromips);
s = "sdp";
fmt = "t,~(b)";
off12 = 1;
offbits = 12;
goto ld_st;
case M_SWM_AB:
ab = 1;
@ -8452,7 +8584,7 @@ macro (struct mips_cl_insn *ip)
gas_assert (mips_opts.micromips);
s = "swm";
fmt = "n,~(b)";
off12 = 1;
offbits = 12;
goto ld_st;
case M_SDM_AB:
ab = 1;
@ -8460,7 +8592,7 @@ macro (struct mips_cl_insn *ip)
gas_assert (mips_opts.micromips);
s = "sdm";
fmt = "n,~(b)";
off12 = 1;
offbits = 12;
ld_st:
tempreg = AT;
@ -8490,18 +8622,25 @@ macro (struct mips_cl_insn *ip)
expr1.X_add_number = offset_expr.X_add_number;
normalize_address_expr (&expr1);
if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
if ((offbits == 0 || offbits == 16)
&& !IS_SEXT_16BIT_NUM (expr1.X_add_number))
{
expr1.X_add_number = ((expr1.X_add_number + 0x8000)
& ~(bfd_vma) 0xffff);
hipart = 1;
}
else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
else if (offbits == 12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
{
expr1.X_add_number = ((expr1.X_add_number + 0x800)
& ~(bfd_vma) 0xfff);
hipart = 1;
}
else if (offbits == 9 && !IS_SEXT_9BIT_NUM (expr1.X_add_number))
{
expr1.X_add_number = ((expr1.X_add_number + 0x100)
& ~(bfd_vma) 0x1ff);
hipart = 1;
}
if (hipart)
{
load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
@ -8510,7 +8649,7 @@ macro (struct mips_cl_insn *ip)
tempreg, tempreg, breg);
breg = tempreg;
}
if (off0)
if (offbits == 0)
{
if (offset_expr.X_add_number == 0)
tempreg = breg;
@ -8519,20 +8658,20 @@ macro (struct mips_cl_insn *ip)
"t,r,j", tempreg, breg, BFD_RELOC_LO16);
macro_build (NULL, s, fmt, treg, tempreg);
}
else if (!off12)
else if (offbits == 16)
macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
else
macro_build (NULL, s, fmt,
treg, (unsigned long) offset_expr.X_add_number, breg);
}
else if (off12 || off0)
else if (offbits != 16)
{
/* A 12-bit or 0-bit offset field is too narrow to be used
for a low-part relocation, so load the whole address into
the auxillary register. In the case of "A(b)" addresses,
we first load absolute address "A" into the register and
then add base register "b". In the case of "o(b)" addresses,
we simply need to add 16-bit offset "o" to base register "b", and
/* The offset field is too narrow to be used for a low-part
relocation, so load the whole address into the auxillary
register. In the case of "A(b)" addresses, we first load
absolute address "A" into the register and then add base
register "b". In the case of "o(b)" addresses, we simply
need to add 16-bit offset "o" to base register "b", and
offset_reloc already contains the relocations associated
with "o". */
if (ab)
@ -8547,7 +8686,7 @@ macro (struct mips_cl_insn *ip)
tempreg, breg, -1,
offset_reloc[0], offset_reloc[1], offset_reloc[2]);
expr1.X_add_number = 0;
if (off0)
if (offbits == 0)
macro_build (NULL, s, fmt, treg, tempreg);
else
macro_build (NULL, s, fmt,
@ -9360,14 +9499,14 @@ macro (struct mips_cl_insn *ip)
ab = 1;
case M_SAA_OB:
s = "saa";
off0 = 1;
offbits = 0;
fmt = "t,(b)";
goto ld_st;
case M_SAAD_AB:
ab = 1;
case M_SAAD_OB:
s = "saad";
off0 = 1;
offbits = 0;
fmt = "t,(b)";
goto ld_st;
@ -10029,7 +10168,7 @@ macro (struct mips_cl_insn *ip)
case M_ULW:
s = "lwl";
s2 = "lwr";
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
off = 3;
goto uld_st;
case M_ULD_A:
@ -10037,7 +10176,7 @@ macro (struct mips_cl_insn *ip)
case M_ULD:
s = "ldl";
s2 = "ldr";
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
off = 7;
goto uld_st;
case M_USH_A:
@ -10053,7 +10192,7 @@ macro (struct mips_cl_insn *ip)
case M_USW:
s = "swl";
s2 = "swr";
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
off = 3;
ust = 1;
goto uld_st;
@ -10062,7 +10201,7 @@ macro (struct mips_cl_insn *ip)
case M_USD:
s = "sdl";
s2 = "sdr";
off12 = mips_opts.micromips;
offbits = (mips_opts.micromips ? 12 : 16);
off = 7;
ust = 1;
@ -10084,7 +10223,7 @@ macro (struct mips_cl_insn *ip)
tempreg = treg;
ep = &expr1;
}
else if (off12
else if (offbits == 12
&& (offset_expr.X_op != O_constant
|| !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
|| !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
@ -10110,7 +10249,7 @@ macro (struct mips_cl_insn *ip)
if (!target_big_endian)
ep->X_add_number += off;
if (!off12)
if (offbits != 12)
macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
else
macro_build (NULL, s, "t,~(b)",
@ -10120,7 +10259,7 @@ macro (struct mips_cl_insn *ip)
ep->X_add_number -= off;
else
ep->X_add_number += off;
if (!off12)
if (offbits != 12)
macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
else
macro_build (NULL, s2, "t,~(b)",
@ -10471,6 +10610,7 @@ validate_mips_insn (const struct mips_opcode *opc)
case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
case 'j': USE_BITS (OP_MASK_EVAOFFSET, OP_SH_EVAOFFSET); break;
default:
as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
@ -10632,6 +10772,7 @@ validate_micromips_insn (const struct mips_opcode *opc)
case 'F': USE_BITS (INSMSB); break;
case 'G': USE_BITS (EXTMSBD); break;
case 'H': USE_BITS (EXTMSBD); break;
case 'j': USE_BITS (EVAOFFSET); break;
default:
as_bad (_("Internal error: bad mips opcode "
"(unknown extension operand type `%c%c'): %s %s"),
@ -11739,6 +11880,35 @@ mips_ip (char *str, struct mips_cl_insn *ip)
INSERT_OPERAND (0, FZ, *ip, regno);
continue;
case 'j':
{
int shift = 8;
size_t i;
/* Check whether there is only a single bracketed expression
left. If so, it must be the base register and the
constant must be zero. */
if (*s == '(' && strchr (s + 1, '(') == 0)
continue;
/* If this value won't fit into the offset, then go find
a macro that will generate a 16- or 32-bit offset code
pattern. */
i = my_getSmallExpression (&imm_expr, imm_reloc, s);
if ((i == 0 && (imm_expr.X_op != O_constant
|| imm_expr.X_add_number >= 1 << shift
|| imm_expr.X_add_number < -1 << shift))
|| i > 0)
{
imm_expr.X_op = O_absent;
break;
}
INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, *ip,
imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
}
continue;
default:
as_bad (_("Internal error: bad %s opcode "
"(unknown extension operand type `+%c'): %s %s"),
@ -14559,6 +14729,8 @@ enum options
OPTION_NO_SMARTMIPS,
OPTION_DSPR2,
OPTION_NO_DSPR2,
OPTION_EVA,
OPTION_NO_EVA,
OPTION_MICROMIPS,
OPTION_NO_MICROMIPS,
OPTION_MCU,
@ -14655,6 +14827,8 @@ struct option md_longopts[] =
{"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
{"mdspr2", no_argument, NULL, OPTION_DSPR2},
{"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
{"meva", no_argument, NULL, OPTION_EVA},
{"mno-eva", no_argument, NULL, OPTION_NO_EVA},
{"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
{"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
{"mmcu", no_argument, NULL, OPTION_MCU},
@ -14907,6 +15081,14 @@ md_parse_option (int c, char *arg)
mips_opts.ase_dsp = 0;
break;
case OPTION_EVA:
mips_opts.ase_eva = 1;
break;
case OPTION_NO_EVA:
mips_opts.ase_eva = 0;
break;
case OPTION_MT:
mips_opts.ase_mt = 1;
break;
@ -15427,6 +15609,12 @@ mips_after_parse_args (void)
as_warn (_("%s ISA does not support DSP R2 ASE"),
mips_cpu_info_from_isa (mips_opts.isa)->name);
if (mips_opts.ase_eva == -1)
mips_opts.ase_eva = (arch_info->flags & MIPS_CPU_ASE_EVA) ? 1 : 0;
if (mips_opts.ase_eva && !ISA_SUPPORTS_EVA_ASE)
as_warn (_("%s ISA does not support EVA ASE"),
mips_cpu_info_from_isa (mips_opts.isa)->name);
if (mips_opts.ase_mt == -1)
mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
@ -15451,6 +15639,7 @@ mips_after_parse_args (void)
file_ase_smartmips = mips_opts.ase_smartmips;
file_ase_dsp = mips_opts.ase_dsp;
file_ase_dspr2 = mips_opts.ase_dspr2;
file_ase_eva = mips_opts.ase_eva;
file_ase_mt = mips_opts.ase_mt;
file_ase_virt = mips_opts.ase_virt;
mips_opts.gp32 = file_mips_gp32;
@ -16510,6 +16699,15 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
mips_opts.ase_dspr2 = 0;
mips_opts.ase_dsp = 0;
}
else if (strcmp (name, "eva") == 0)
{
if (!ISA_SUPPORTS_EVA_ASE)
as_warn (_("%s ISA does not support EVA ASE"),
mips_cpu_info_from_isa (mips_opts.isa)->name);
mips_opts.ase_eva = 1;
}
else if (strcmp (name, "noeva") == 0)
mips_opts.ase_eva = 0;
else if (strcmp (name, "mt") == 0)
{
if (!ISA_SUPPORTS_MT_ASE)

9
gas/testsuite/ChangeLog
View File

@ -1,3 +1,12 @@
2013-06-17 Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
Chao-Ying Fu <fu@mips.com>
* gas/mips/mips.exp: Run new tests.
* gas/mips/eva.d: New.
* gas/mips/eva.s: New.
* gas/mips/micromips@eva.d: New.
2013-06-15 Richard Sandiford <rdsandiford@googlemail.com>
* gas/mips/loc-swap-3.d: Require -32.

1442
gas/testsuite/gas/mips/eva.d Normal file
View File

File diff suppressed because it is too large Load Diff

612
gas/testsuite/gas/mips/eva.s Normal file
View File

@ -0,0 +1,612 @@
.text
.set nomips16
.set noreorder
test_eva:
lbue $0,-256($2)
lbue $3,-256
lbue $4,255($5)
lbue $6,255
lbue $7,-257($8)
lbue $9,-257
lbue $10,256($11)
lbue $12,256
lbue $13,-512($14)
lbue $15,-512
lbue $16,511($17)
lbue $18,511
lbue $19,-1024($20)
lbue $21,-1024
lbue $22,1023($23)
lbue $24,1023
lbue $25,-2048($26)
lbue $27,-2048
lbue $28,2047($29)
lbue $30,2047
lbue $31,-4096($0)
lbue $2,-4096
lbue $3,4095($4)
lbue $5,4095
lbue $6,-32768($7)
lbue $8,-32768
lbue $9,32767($10)
lbue $11,32767
lbue $12,-32769($13)
lbue $14,-32769
lbue $15,32768($16)
lbue $17,32768
lbue $18,-2147483648($19)
lbue $20,-2147483648
lbue $21,2147483647($22)
lbue $23,2147483647
lbue $24,($25)
lbue $26,MYDATA
lhue $27,-256($28)
lhue $29,-256
lhue $30,255($31)
lhue $0,255
lhue $2,-257($3)
lhue $4,-257
lhue $5,256($6)
lhue $7,256
lhue $8,-512($9)
lhue $10,-512
lhue $11,511($12)
lhue $13,511
lhue $14,-1024($15)
lhue $16,-1024
lhue $17,1023($18)
lhue $19,1023
lhue $20,-2048($21)
lhue $22,-2048
lhue $23,2047($24)
lhue $25,2047
lhue $26,-4096($27)
lhue $28,-4096
lhue $29,4095($30)
lhue $31,4095
lhue $0,-32768($2)
lhue $3,-32768
lhue $4,32767($5)
lhue $6,32767
lhue $7,-32769($8)
lhue $9,-32769
lhue $10,32768($11)
lhue $12,32768
lhue $13,-2147483648($14)
lhue $15,-2147483648
lhue $16,2147483647($17)
lhue $18,2147483647
lhue $19,($20)
lhue $21,MYDATA
lbe $22,-256($23)
lbe $24,-256
lbe $25,255($26)
lbe $27,255
lbe $28,-257($29)
lbe $30,-257
lbe $31,256($0)
lbe $2,256
lbe $3,-512($4)
lbe $5,-512
lbe $6,511($7)
lbe $8,511
lbe $9,-1024($10)
lbe $11,-1024
lbe $12,1023($13)
lbe $14,1023
lbe $15,-2048($16)
lbe $17,-2048
lbe $18,2047($19)
lbe $20,2047
lbe $21,-4096($22)
lbe $23,-4096
lbe $24,4095($25)
lbe $26,4095
lbe $27,-32768($28)
lbe $29,-32768
lbe $30,32767($31)
lbe $0,32767
lbe $2,-32769($3)
lbe $4,-32769
lbe $5,32768($6)
lbe $7,32768
lbe $8,-2147483648($9)
lbe $10,-2147483648
lbe $11,2147483647($12)
lbe $13,2147483647
lbe $14,($15)
lbe $16,MYDATA
lhe $17,-256($18)
lhe $19,-256
lhe $20,255($21)
lhe $22,255
lhe $23,-257($24)
lhe $25,-257
lhe $26,256($27)
lhe $28,256
lhe $29,-512($30)
lhe $31,-512
lhe $0,511($2)
lhe $3,511
lhe $4,-1024($5)
lhe $6,-1024
lhe $7,1023($8)
lhe $9,1023
lhe $10,-2048($11)
lhe $12,-2048
lhe $13,2047($14)
lhe $15,2047
lhe $16,-4096($17)
lhe $18,-4096
lhe $19,4095($20)
lhe $21,4095
lhe $22,-32768($23)
lhe $24,-32768
lhe $25,32767($26)
lhe $27,32767
lhe $28,-32769($29)
lhe $30,-32769
lhe $31,32768($0)
lhe $2,32768
lhe $3,-2147483648($4)
lhe $5,-2147483648
lhe $6,2147483647($7)
lhe $8,2147483647
lhe $9,($10)
lhe $11,MYDATA
lle $12,-256($13)
lle $14,-256
lle $15,255($16)
lle $17,255
lle $18,-257($19)
lle $20,-257
lle $21,256($22)
lle $23,256
lle $24,-512($25)
lle $26,-512
lle $27,511($28)
lle $29,511
lle $30,-1024($31)
lle $0,-1024
lle $2,1023($3)
lle $4,1023
lle $5,-2048($6)
lle $7,-2048
lle $8,2047($9)
lle $10,2047
lle $11,-4096($12)
lle $13,-4096
lle $14,4095($15)
lle $16,4095
lle $17,-32768($18)
lle $19,-32768
lle $20,32767($21)
lle $22,32767
lle $23,-32769($24)
lle $25,-32769
lle $26,32768($27)
lle $28,32768
lle $29,-2147483648($30)
lle $31,-2147483648
lle $0,2147483647($2)
lle $3,2147483647
lle $4,($5)
lle $6,MYDATA
lwe $7,-256($8)
lwe $9,-256
lwe $10,255($11)
lwe $12,255
lwe $13,-257($14)
lwe $15,-257
lwe $16,256($17)
lwe $18,256
lwe $19,-512($20)
lwe $21,-512
lwe $22,511($23)
lwe $24,511
lwe $25,-1024($26)
lwe $27,-1024
lwe $28,1023($29)
lwe $30,1023
lwe $31,-2048($0)
lwe $2,-2048
lwe $3,2047($4)
lwe $5,2047
lwe $6,-4096($7)
lwe $8,-4096
lwe $9,4095($10)
lwe $11,4095
lwe $12,-32768($13)
lwe $14,-32768
lwe $15,32767($16)
lwe $17,32767
lwe $18,-32769($19)
lwe $20,-32769
lwe $21,32768($22)
lwe $23,32768
lwe $24,-2147483648($25)
lwe $26,-2147483648
lwe $27,2147483647($28)
lwe $29,2147483647
lwe $30,($31)
lwe $0,MYDATA
lwle $2,-256($3)
lwle $4,-256
lwle $5,255($6)
lwle $7,255
lwle $8,-257($9)
lwle $10,-257
lwle $11,256($12)
lwle $13,256
lwle $14,-512($15)
lwle $16,-512
lwle $17,511($18)
lwle $19,511
lwle $20,-1024($21)
lwle $22,-1024
lwle $23,1023($24)
lwle $25,1023
lwle $26,-2048($27)
lwle $28,-2048
lwle $29,2047($30)
lwle $31,2047
lwle $0,-4096($2)
lwle $3,-4096
lwle $4,4095($5)
lwle $6,4095
lwle $7,-32768($8)
lwle $9,-32768
lwle $10,32767($11)
lwle $12,32767
lwle $13,-32769($14)
lwle $15,-32769
lwle $16,32768($17)
lwle $18,32768
lwle $19,-2147483648($20)
lwle $21,-2147483648
lwle $22,2147483647($23)
lwle $24,2147483647
lwle $25,($26)
lwle $27,MYDATA
lwre $28,-256($29)
lwre $30,-256
lwre $31,255($0)
lwre $2,255
lwre $3,-257($4)
lwre $5,-257
lwre $6,256($7)
lwre $8,256
lwre $9,-512($10)
lwre $11,-512
lwre $12,511($13)
lwre $14,511
lwre $15,-1024($16)
lwre $17,-1024
lwre $18,1023($19)
lwre $20,1023
lwre $21,-2048($22)
lwre $23,-2048
lwre $24,2047($25)
lwre $26,2047
lwre $27,-4096($28)
lwre $29,-4096
lwre $30,4095($31)
lwre $0,4095
lwre $2,-32768($3)
lwre $4,-32768
lwre $5,32767($6)
lwre $7,32767
lwre $8,-32769($9)
lwre $10,-32769
lwre $11,32768($12)
lwre $13,32768
lwre $14,-2147483648($15)
lwre $16,-2147483648
lwre $17,2147483647($18)
lwre $19,2147483647
lwre $20,($21)
lwre $22,MYDATA
sbe $23,-256($24)
sbe $25,-256
sbe $26,255($27)
sbe $28,255
sbe $29,-257($30)
sbe $31,-257
sbe $0,256($2)
sbe $3,256
sbe $4,-512($5)
sbe $6,-512
sbe $7,511($8)
sbe $9,511
sbe $10,-1024($11)
sbe $12,-1024
sbe $13,1023($14)
sbe $15,1023
sbe $16,-2048($17)
sbe $18,-2048
sbe $19,2047($20)
sbe $21,2047
sbe $22,-4096($23)
sbe $24,-4096
sbe $25,4095($26)
sbe $27,4095
sbe $28,-32768($29)
sbe $30,-32768
sbe $31,32767($0)
sbe $2,32767
sbe $3,-32769($4)
sbe $5,-32769
sbe $6,32768($7)
sbe $8,32768
sbe $9,-2147483648($10)
sbe $11,-2147483648
sbe $12,2147483647($13)
sbe $14,2147483647
sbe $15,($16)
sbe $17,MYDATA
sce $18,-256($19)
sce $20,-256
sce $21,255($22)
sce $23,255
sce $24,-257($25)
sce $26,-257
sce $27,256($28)
sce $29,256
sce $30,-512($31)
sce $0,-512
sce $2,511($3)
sce $4,511
sce $5,-1024($6)
sce $7,-1024
sce $8,1023($9)
sce $10,1023
sce $11,-2048($12)
sce $13,-2048
sce $14,2047($15)
sce $16,2047
sce $17,-4096($18)
sce $19,-4096
sce $20,4095($21)
sce $22,4095
sce $23,-32768($24)
sce $25,-32768
sce $26,32767($27)
sce $28,32767
sce $29,-32769($30)
sce $31,-32769
sce $0,32768($2)
sce $3,32768
sce $4,-2147483648($5)
sce $6,-2147483648
sce $7,2147483647($8)
sce $9,2147483647
sce $10,($11)
sce $12,MYDATA
she $13,-256($14)
she $15,-256
she $16,255($17)
she $18,255
she $19,-257($20)
she $21,-257
she $22,256($23)
she $24,256
she $25,-512($26)
she $27,-512
she $28,511($29)
she $30,511
she $31,-1024($0)
she $2,-1024
she $3,1023($4)
she $5,1023
she $6,-2048($7)
she $8,-2048
she $9,2047($10)
she $11,2047
she $12,-4096($13)
she $14,-4096
she $15,4095($16)
she $17,4095
she $18,-32768($19)
she $20,-32768
she $21,32767($22)
she $23,32767
she $24,-32769($25)
she $26,-32769
she $27,32768($28)
she $29,32768
she $30,-2147483648($31)
she $0,-2147483648
she $2,2147483647($3)
she $4,2147483647
she $5,($6)
she $7,MYDATA
swe $8,-256($9)
swe $10,-256
swe $11,255($12)
swe $13,255
swe $14,-257($15)
swe $16,-257
swe $17,256($18)
swe $19,256
swe $20,-512($21)
swe $22,-512
swe $23,511($24)
swe $25,511
swe $26,-1024($27)
swe $28,-1024
swe $29,1023($30)
swe $31,1023
swe $0,-2048($2)
swe $3,-2048
swe $4,2047($5)
swe $6,2047
swe $7,-4096($8)
swe $9,-4096
swe $10,4095($11)
swe $12,4095
swe $13,-32768($14)
swe $15,-32768
swe $16,32767($17)
swe $18,32767
swe $19,-32769($20)
swe $21,-32769
swe $22,32768($23)
swe $24,32768
swe $25,-2147483648($26)
swe $27,-2147483648
swe $28,2147483647($29)
swe $30,2147483647
swe $31,($0)
swe $2,MYDATA
swle $3,-256($4)
swle $5,-256
swle $6,255($7)
swle $8,255
swle $9,-257($10)
swle $11,-257
swle $12,256($13)
swle $14,256
swle $15,-512($16)
swle $17,-512
swle $18,511($19)
swle $20,511
swle $21,-1024($22)
swle $23,-1024
swle $24,1023($25)
swle $26,1023
swle $27,-2048($28)
swle $29,-2048
swle $30,2047($31)
swle $0,2047
swle $2,-4096($3)
swle $4,-4096
swle $5,4095($6)
swle $7,4095
swle $8,-32768($9)
swle $10,-32768
swle $11,32767($12)
swle $13,32767
swle $14,-32769($15)
swle $16,-32769
swle $17,32768($18)
swle $19,32768
swle $20,-2147483648($21)
swle $22,-2147483648
swle $23,2147483647($24)
swle $25,2147483647
swle $26,($27)
swle $28,MYDATA
swre $29,-256($30)
swre $31,-256
swre $0,255($2)
swre $3,255
swre $4,-257($5)
swre $6,-257
swre $7,256($8)
swre $9,256
swre $10,-512($11)
swre $12,-512
swre $13,511($14)
swre $15,511
swre $16,-1024($17)
swre $18,-1024
swre $19,1023($20)
swre $21,1023
swre $22,-2048($23)
swre $24,-2048
swre $25,2047($26)
swre $27,2047
swre $28,-4096($29)
swre $30,-4096
swre $31,4095($0)
swre $2,4095
swre $3,-32768($4)
swre $5,-32768
swre $6,32767($7)
swre $8,32767
swre $9,-32769($10)
swre $11,-32769
swre $12,32768($13)
swre $14,32768
swre $15,-2147483648($16)
swre $17,-2147483648
swre $18,2147483647($19)
swre $20,2147483647
swre $21,($22)
swre $23,MYDATA
cachee 24,-256($25)
cachee 26,-256
cachee 27,255($28)
cachee 29,255
cachee 30,-257($31)
cachee 0,-257
cachee 2,256($3)
cachee 4,256
cachee 5,-512($6)
cachee 7,-512
cachee 8,511($9)
cachee 10,511
cachee 11,-1024($12)
cachee 13,-1024
cachee 14,1023($15)
cachee 16,1023
cachee 17,-2048($18)
cachee 19,-2048
cachee 20,2047($21)
cachee 22,2047
cachee 23,-4096($24)
cachee 25,-4096
cachee 26,4095($27)
cachee 28,4095
cachee 29,-32768($30)
cachee 31,-32768
cachee 0,32767($2)
cachee 3,32767
cachee 4,-32769($5)
cachee 6,-32769
cachee 7,32768($8)
cachee 9,32768
cachee 10,-2147483648($11)
cachee 12,-2147483648
cachee 13,2147483647($14)
cachee 15,2147483647
cachee 16,($17)
cachee 18,MYDATA
prefe 19,-256($20)
prefe 21,-256
prefe 22,255($23)
prefe 24,255
prefe 25,-257($26)
prefe 27,-257
prefe 28,256($29)
prefe 30,256
prefe 31,-512($0)
prefe 2,-512
prefe 3,511($4)
prefe 5,511
prefe 6,-1024($7)
prefe 8,-1024
prefe 9,1023($10)
prefe 11,1023
prefe 12,-2048($13)
prefe 14,-2048
prefe 15,2047($16)
prefe 17,2047
prefe 18,-4096($19)
prefe 20,-4096
prefe 21,4095($22)
prefe 23,4095
prefe 24,-32768($25)
prefe 26,-32768
prefe 27,32767($28)
prefe 29,32767
prefe 30,-32769($31)
prefe 0,-32769
prefe 2,32768($3)
prefe 4,32768
prefe 5,-2147483648($6)
prefe 7,-2147483648
prefe 8,2147483647($9)
prefe 10,2147483647
prefe 11,($12)
prefe 13,MYDATA

1441
gas/testsuite/gas/mips/micromips@eva.d Normal file
View File

File diff suppressed because it is too large Load Diff

2
gas/testsuite/gas/mips/mips.exp
View File

@ -849,6 +849,8 @@ if { [istarget mips*-*-vxworks*] } {
[mips_arch_list_matching mips64r2 \
!micromips]
run_dump_test_arches "eva" [mips_arch_list_matching mips32r2 !octeon]
run_list_test "illegal" "-32"
run_list_test "baddata1" "-32"
run_list_test "jalr" ""

27
include/opcode/ChangeLog
View File

@ -1,3 +1,30 @@
2013-06-17 Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
Chao-Ying Fu <fu@mips.com>
* mips.h (OP_SH_EVAOFFSET): Define.
(OP_MASK_EVAOFFSET): Define.
(INSN_ASE_MASK): Delete.
(ASE_EVA): Define.
(M_CACHEE_AB, M_CACHEE_OB): New.
(M_LBE_OB, M_LBE_AB): New.
(M_LBUE_OB, M_LBUE_AB): New.
(M_LHE_OB, M_LHE_AB): New.
(M_LHUE_OB, M_LHUE_AB): New.
(M_LLE_AB, M_LLE_OB): New.
(M_LWE_OB, M_LWE_AB): New.
(M_LWLE_AB, M_LWLE_OB): New.
(M_LWRE_AB, M_LWRE_OB): New.
(M_PREFE_AB, M_PREFE_OB): New.
(M_SCE_AB, M_SCE_OB): New.
(M_SBE_OB, M_SBE_AB): New.
(M_SHE_OB, M_SHE_AB): New.
(M_SWE_OB, M_SWE_AB): New.
(M_SWLE_AB, M_SWLE_OB): New.
(M_SWRE_AB, M_SWRE_OB): New.
(MICROMIPSOP_SH_EVAOFFSET): Define.
(MICROMIPSOP_MASK_EVAOFFSET): Define.
2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
* nios2.h (OP_MATCH_ERET): Correct eret encoding.

55
include/opcode/mips.h
View File

@ -330,6 +330,10 @@
#define OP_MASK_IMMY 0
#define OP_SH_IMMY 0
/* Enhanced VA Scheme */
#define OP_SH_EVAOFFSET 7
#define OP_MASK_EVAOFFSET 0x1ff
/* This structure holds information for a particular instruction. */
struct mips_opcode
@ -521,6 +525,9 @@ struct mips_opcode
"+z" 5-bit rz register (OP_*_RZ)
"+Z" 5-bit fz register (OP_*_FZ)
Enhanced VA Scheme:
"+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
Other:
"()" parens surrounding optional value
"," separates operands
@ -537,7 +544,7 @@ struct mips_opcode
following), for quick reference when adding more:
"1234"
"ABCDEFGHIJPQSTXZ"
"abcpstxz"
"abcjpstxz"
*/
/* These are the bits which may be set in the pinfo field of an
@ -733,9 +740,6 @@ static const unsigned int mips_isa_table[] =
#define INSN_OCTEONP 0x00000200
#define INSN_OCTEON2 0x00000100
/* Masks used for MIPS-defined ASEs. */
#define INSN_ASE_MASK 0x3c00f0d0
/* MIPS R5900 instruction */
#define INSN_5900 0x00004000
@ -774,6 +778,8 @@ static const unsigned int mips_isa_table[] =
#define ASE_DSP64 0x00000002
/* DSP R2 ASE */
#define ASE_DSPR2 0x00000004
/* Enhanced VA Scheme */
#define ASE_EVA 0x00000008
/* MCU (MicroController) ASE */
#define ASE_MCU 0x00000010
/* MDMX ASE */
@ -1020,6 +1026,8 @@ enum
M_BNEL_I,
M_CACHE_AB,
M_CACHE_OB,
M_CACHEE_AB,
M_CACHEE_OB,
M_DABS,
M_DADD_I,
M_DADDU_I,
@ -1061,8 +1069,12 @@ enum
M_LA_AB,
M_LB_A,
M_LB_AB,
M_LBE_OB,
M_LBE_AB,
M_LBU_A,
M_LBU_AB,
M_LBUE_OB,
M_LBUE_AB,
M_LCA_AB,
M_LD_A,
M_LD_OB,
@ -1082,8 +1094,12 @@ enum
M_LDR_OB,
M_LH_A,
M_LH_AB,
M_LHE_OB,
M_LHE_AB,
M_LHU_A,
M_LHU_AB,
M_LHUE_OB,
M_LHUE_AB,
M_LI,
M_LI_D,
M_LI_DD,
@ -1093,10 +1109,14 @@ enum
M_LL_OB,
M_LLD_AB,
M_LLD_OB,
M_LLE_AB,
M_LLE_OB,
M_LQ_AB,
M_LS_A,
M_LW_A,
M_LW_AB,
M_LWE_OB,
M_LWE_AB,
M_LWC0_A,
M_LWC0_AB,
M_LWC1_A,
@ -1109,6 +1129,8 @@ enum
M_LWL_A,
M_LWL_AB,
M_LWL_OB,
M_LWLE_AB,
M_LWLE_OB,
M_LWM_AB,
M_LWM_OB,
M_LWP_AB,
@ -1116,6 +1138,8 @@ enum
M_LWR_A,
M_LWR_AB,
M_LWR_OB,
M_LWRE_AB,
M_LWRE_OB,
M_LWU_AB,
M_LWU_OB,
M_MSGSND,
@ -1134,6 +1158,8 @@ enum
M_OR_I,
M_PREF_AB,
M_PREF_OB,
M_PREFE_AB,
M_PREFE_OB,
M_REM_3,
M_REM_3I,
M_REMU_3,
@ -1158,6 +1184,8 @@ enum
M_SC_OB,
M_SCD_AB,
M_SCD_OB,
M_SCE_AB,
M_SCE_OB,
M_SD_A,
M_SD_OB,
M_SD_AB,
@ -1194,11 +1222,17 @@ enum
M_SNE_I,
M_SB_A,
M_SB_AB,
M_SBE_OB,
M_SBE_AB,
M_SH_A,
M_SH_AB,
M_SHE_OB,
M_SHE_AB,
M_SQ_AB,
M_SW_A,
M_SW_AB,
M_SWE_OB,
M_SWE_AB,
M_SWC0_A,
M_SWC0_AB,
M_SWC1_A,
@ -1211,6 +1245,8 @@ enum
M_SWL_A,
M_SWL_AB,
M_SWL_OB,
M_SWLE_AB,
M_SWLE_OB,
M_SWM_AB,
M_SWM_OB,
M_SWP_AB,
@ -1218,6 +1254,8 @@ enum
M_SWR_A,
M_SWR_AB,
M_SWR_OB,
M_SWRE_AB,
M_SWRE_OB,
M_SUB_I,
M_SUBU_I,
M_SUBU_I_2,
@ -1638,6 +1676,10 @@ extern const int bfd_mips16_num_opcodes;
#define MICROMIPSOP_SH_FZ 0
#define MICROMIPSOP_MASK_FZ 0
/* microMIPS Enhanced VA Scheme */
#define MICROMIPSOP_SH_EVAOFFSET 0
#define MICROMIPSOP_MASK_EVAOFFSET 0x1ff
/* These are the characters which may appears in the args field of a microMIPS
instruction. They appear in the order in which the fields appear
when the instruction is used. Commas and parentheses in the args
@ -1795,6 +1837,9 @@ extern const int bfd_mips16_num_opcodes;
"@" 10-bit signed immediate (MICROMIPSOP_*_IMM10)
"^" 5-bit unsigned immediate (MICROMIPSOP_*_RD)
microMIPS Enhanced VA Scheme:
"+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET)
Other:
"()" parens surrounding optional value
"," separates operands
@ -1809,7 +1854,7 @@ extern const int bfd_mips16_num_opcodes;
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
""
"j"
""
"ABCDEFGHI"
""

14
opcodes/ChangeLog
View File

@ -1,3 +1,17 @@
2013-06-17 Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
Chao-Ying Fu <fu@mips.com>
* micromips-opc.c (EVA): Define.
(TLBINV): Define.
(micromips_opcodes): Add EVA opcodes.
* mips-dis.c (mips_arch_choices): Update for ASE_EVA.
(print_insn_args): Handle EVA offsets.
(print_insn_micromips): Likewise.
* mips-opc.c (EVA): Define.
(TLBINV): Define.
(mips_builtin_opcodes): Add EVA opcodes.
2013-06-17 Alan Modra <amodra@gmail.com>
* Makefile.am (mips-opc.lo): Add rules to create automatic

57
opcodes/micromips-opc.c
View File

@ -110,6 +110,12 @@
/* MIPS MCU (MicroController) ASE support. */
#define MC ASE_MCU
/* MIPS Enhanced VA Scheme. */
#define EVA ASE_EVA
/* TLB invalidate instruction support. */
#define TLBINV ASE_EVA
/* MIPS Virtualization ASE. */
#define IVIRT ASE_VIRT
#define IVIRT64 ASE_VIRT64
@ -955,6 +961,8 @@ const struct mips_opcode micromips_opcodes[] =
{"tgeu", "s,t,|", 0x0000043c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 },
{"tgeu", "s,j", 0x41600000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* tgeiu */
{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I1 },
{"tlbinv", "", 0x0000437c, 0xffffffff, INSN_TLB, 0, 0, TLBINV },
{"tlbinvf", "", 0x0000537c, 0xffffffff, INSN_TLB, 0, 0, TLBINV },
{"tlbginv", "", 0x0000417c, 0xffffffff, INSN_TLB, 0, 0, IVIRT },
{"tlbginvf","", 0x0000517c, 0xffffffff, INSN_TLB, 0, 0, IVIRT },
{"tlbgp", "", 0x0000017c, 0xffffffff, INSN_TLB, 0, 0, IVIRT },
@ -1007,6 +1015,55 @@ const struct mips_opcode micromips_opcodes[] =
{"xor", "d,v,t", 0x00000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
{"xori", "t,r,i", 0x70000000, 0xfc000000, WR_t|RD_s, 0, I1 },
/* microMIPS Enhanced VA Scheme */
{"lbue", "t,+j(b)", 0x60006000, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
{"lbue", "t,o(b)", 0, (int) M_LBUE_OB, INSN_MACRO, 0, 0, EVA },
{"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA },
{"lhue", "t,+j(b)", 0x60006200, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
{"lhue", "t,o(b)", 0, (int) M_LHUE_OB, INSN_MACRO, 0, 0, EVA },
{"lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA },
{"lbe", "t,+j(b)", 0x60006800, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
{"lbe", "t,o(b)", 0, (int) M_LBE_OB, INSN_MACRO, 0, 0, EVA },
{"lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA },
{"lhe", "t,+j(b)", 0x60006a00, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
{"lhe", "t,o(b)", 0, (int) M_LHE_OB, INSN_MACRO, 0, 0, EVA },
{"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA },
{"lle", "t,+j(b)", 0x60006c00, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
{"lle", "t,o(b)", 0, (int) M_LLE_OB, INSN_MACRO, 0, 0, EVA },
{"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA },
{"lwe", "t,+j(b)", 0x60006e00, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
{"lwe", "t,o(b)", 0, (int) M_LWE_OB, INSN_MACRO, 0, 0, EVA },
{"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA },
{"lwle", "t,+j(b)", 0x60006400, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
{"lwle", "t,o(b)", 0, (int) M_LWLE_OB, INSN_MACRO, 0, 0, EVA },
{"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA },
{"lwre", "t,+j(b)", 0x60006600, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
{"lwre", "t,o(b)", 0, (int) M_LWRE_OB, INSN_MACRO, 0, 0, EVA },
{"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA },
{"sbe", "t,+j(b)", 0x6000a800, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
{"sbe", "t,o(b)", 0, (int) M_SBE_OB, INSN_MACRO, 0, 0, EVA },
{"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA },
{"sce", "t,+j(b)", 0x6000ac00, 0xfc00fe00, SM|RD_t|WR_t|RD_b, 0, 0, EVA },
{"sce", "t,o(b)", 0, (int) M_SCE_OB, INSN_MACRO, 0, 0, EVA },
{"sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA },
{"she", "t,+j(b)", 0x6000aa00, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
{"she", "t,o(b)", 0, (int) M_SHE_OB, INSN_MACRO, 0, 0, EVA },
{"she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA },
{"swe", "t,+j(b)", 0x6000ae00, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
{"swe", "t,o(b)", 0, (int) M_SWE_OB, INSN_MACRO, 0, 0, EVA },
{"swe", "t,A(b)", 0, (int) M_SWE_AB, INSN_MACRO, 0, 0, EVA },
{"swle", "t,+j(b)", 0x6000a000, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
{"swle", "t,o(b)", 0, (int) M_SWLE_OB, INSN_MACRO, 0, 0, EVA },
{"swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA },
{"swre", "t,+j(b)", 0x6000a200, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
{"swre", "t,o(b)", 0, (int) M_SWRE_OB, INSN_MACRO, 0, 0, EVA },
{"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA },
{"cachee", "k,+j(b)", 0x6000a600, 0xfc00fe00, RD_b, 0, 0, EVA },
{"cachee", "k,o(b)", 0, (int) M_CACHEE_OB,INSN_MACRO, 0, 0, EVA },
{"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA },
{"prefe", "k,+j(b)", 0x6000a400, 0xfc00fe00, RD_b, 0, 0, EVA },
{"prefe", "k,o(b)", 0, (int) M_PREFE_OB, INSN_MACRO, 0, 0, EVA },
{"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA },
/* MIPS DSP ASE. */
{"absq_s.ph", "t,s", 0x0000113c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
{"absq_s.w", "t,s", 0x0000213c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },

17
opcodes/mips-dis.c
View File

@ -591,8 +591,8 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
ISA_MIPS32R2,
(ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_MIPS3D | ASE_MT
| ASE_MCU | ASE_VIRT),
(ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
| ASE_MT | ASE_MCU | ASE_VIRT),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
@ -606,8 +606,8 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
ISA_MIPS64R2,
(ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_MT | ASE_MDMX
| ASE_MCU | ASE_VIRT | ASE_VIRT64),
(ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
| ASE_MDMX | ASE_MCU | ASE_VIRT | ASE_VIRT64),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
@ -1152,6 +1152,10 @@ print_insn_args (const char *d,
infprintf (is, "%s", mips_fpr_names[GET_OP (l, FZ)]);
break;
case 'j': /* 9-bit signed offset in bit 7. */
infprintf (is, "%d", GET_OP_S (l, EVAOFFSET));
break;
default:
/* xgettext:c-format */
infprintf (is,
@ -2659,6 +2663,11 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
infprintf (is, "0x%x", msbd + 1);
break;
case 'j': /* 9-bit signed offset in bit 0. */
delta = GET_OP_S (insn, EVAOFFSET);
infprintf (is, "%d", delta);
break;
default:
/* xgettext:c-format */
infprintf (is,

57
opcodes/mips-opc.c
View File

@ -194,6 +194,12 @@
/* MIPS MCU (MicroController) ASE support. */
#define MC ASE_MCU
/* MIPS Enhanced VA Scheme. */
#define EVA ASE_EVA
/* TLB invalidate instruction support. */
#define TLBINV ASE_EVA
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
for arguments must apear in the correct order in this table for the
@ -1640,6 +1646,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgeiu */
{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2 },
{"tlbinv", "", 0x42000003, 0xffffffff, INSN_TLB, 0, 0, TLBINV },
{"tlbinvf", "", 0x42000004, 0xffffffff, INSN_TLB, 0, 0, TLBINV },
{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 },
{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 },
{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 },
@ -2296,6 +2304,55 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"punpcklwd", "D,S,T", 0x4b80000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"sequ", "S,T", 0x46800032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E },
{"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A },
/* MIPS Enhanced VA Scheme */
{"lbue", "t,+j(b)", 0x7c000028, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
{"lbue", "t,o(b)", 0, (int) M_LBUE_OB, INSN_MACRO, 0, 0, EVA },
{"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA },
{"lhue", "t,+j(b)", 0x7c000029, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
{"lhue", "t,o(b)", 0, (int) M_LHUE_OB, INSN_MACRO, 0, 0, EVA },
{"lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA },
{"lbe", "t,+j(b)", 0x7c00002c, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
{"lbe", "t,o(b)", 0, (int) M_LBE_OB, INSN_MACRO, 0, 0, EVA },
{"lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA },
{"lhe", "t,+j(b)", 0x7c00002d, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
{"lhe", "t,o(b)", 0, (int) M_LHE_OB, INSN_MACRO, 0, 0, EVA },
{"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA },
{"lle", "t,+j(b)", 0x7c00002e, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
{"lle", "t,o(b)", 0, (int) M_LLE_OB, INSN_MACRO, 0, 0, EVA },
{"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA },
{"lwe", "t,+j(b)", 0x7c00002f, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
{"lwe", "t,o(b)", 0, (int) M_LWE_OB, INSN_MACRO, 0, 0, EVA },
{"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA },
{"lwle", "t,+j(b)", 0x7c000019, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
{"lwle", "t,o(b)", 0, (int) M_LWLE_OB, INSN_MACRO, 0, 0, EVA },
{"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA },
{"lwre", "t,+j(b)", 0x7c00001a, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
{"lwre", "t,o(b)", 0, (int) M_LWRE_OB, INSN_MACRO, 0, 0, EVA },
{"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA },
{"sbe", "t,+j(b)", 0x7c00001c, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA },
{"sbe", "t,o(b)", 0, (int) M_SBE_OB, INSN_MACRO, 0, 0, EVA },
{"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA },
{"sce", "t,+j(b)", 0x7c00001e, 0xfc00007f, SM|RD_t|WR_t|RD_b, 0, 0, EVA },
{"sce", "t,o(b)", 0, (int) M_SCE_OB, INSN_MACRO, 0, 0, EVA },
{"sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA },
{"she", "t,+j(b)", 0x7c00001d, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA },
{"she", "t,o(b)", 0, (int) M_SHE_OB, INSN_MACRO, 0, 0, EVA },
{"she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA },
{"swe", "t,+j(b)", 0x7c00001f, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA },
{"swe", "t,o(b)", 0, (int) M_SWE_OB, INSN_MACRO, 0, 0, EVA },
{"swe", "t,A(b)", 0, (int) M_SWE_AB, INSN_MACRO, 0, 0, EVA },
{"swle", "t,+j(b)", 0x7c000021, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA },
{"swle", "t,o(b)", 0, (int) M_SWLE_OB, INSN_MACRO, 0, 0, EVA },
{"swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA },
{"swre", "t,+j(b)", 0x7c000022, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA },
{"swre", "t,o(b)", 0, (int) M_SWRE_OB, INSN_MACRO, 0, 0, EVA },
{"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA },
{"cachee", "k,+j(b)", 0x7c00001b, 0xfc00007f, RD_b, 0, 0, EVA },
{"cachee", "k,o(b)", 0, (int) M_CACHEE_OB,INSN_MACRO, 0, 0, EVA },
{"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA },
{"prefe", "k,+j(b)", 0x7c000023, 0xfc00007f, RD_b, 0, 0, EVA },
{"prefe", "k,o(b)", 0, (int) M_PREFE_OB, INSN_MACRO, 0, 0, EVA },
{"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA },
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the