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* interp.c (sim_open): Tidy up device creation.
* dv-mn103int.c (mn103int_port_event): Drive NMI with non-zero value. (mn103int_io_read_buffer): Convert absolute address to register block offsets. (read_icr, write_icr): Convert block offset into group offset.
This commit is contained in:
Andrew Cagney
parent
6100784a60
commit
8077fed51e
sim/mn10300
@ -28,8 +28,6 @@ Makefile.in
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config.in
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configure
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configure.in
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dv-mn103cpu.c
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dv-mn103int.c
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mn10300_sim.h
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gencode.c
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interp.c
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@ -41,6 +39,9 @@ op_utils.c
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Things-to-lose:
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dv-mn103cpu.c
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dv-mn103int.c
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Do-last:
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# End of file.
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@ -1,3 +1,13 @@
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Wed Mar 25 16:14:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (sim_open): Tidy up device creation.
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* dv-mn103int.c (mn103int_port_event): Drive NMI with non-zero
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value.
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(mn103int_io_read_buffer): Convert absolute address to register
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block offsets.
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(read_icr, write_icr): Convert block offset into group offset.
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Wed Mar 25 15:08:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (sim_open): Create second 1mb memory region at
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@ -119,10 +119,11 @@ enum mn103int_trigger {
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enum mn103int_type {
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NMI_GROUP,
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INT_GROUP,
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LEVEL_GROUP,
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};
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struct mn103int_group {
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int gid;
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int level;
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unsigned enable;
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unsigned request;
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@ -134,8 +135,8 @@ struct mn103int_group {
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enum {
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FIRST_NMI_GROUP = 0,
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LAST_NMI_GROUP = 1,
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FIRST_INT_GROUP = 2,
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LAST_INT_GROUP = 24,
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FIRST_LEVEL_GROUP = 2,
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LAST_LEVEL_GROUP = 24,
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NR_GROUPS,
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};
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@ -360,13 +361,14 @@ mn103int_finish (struct hw *me)
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struct mn103int_group *group = &controller->group[gid];
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group->enable = 0xf;
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group->trigger = NEGATIVE_EDGE;
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group->gid = gid;
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if (FIRST_NMI_GROUP <= gid && gid <= LAST_NMI_GROUP)
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{
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group->type = NMI_GROUP;
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}
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else if (FIRST_INT_GROUP <= gid && gid <= LAST_INT_GROUP)
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else if (FIRST_LEVEL_GROUP <= gid && gid <= LAST_LEVEL_GROUP)
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{
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group->type = INT_GROUP;
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group->type = LEVEL_GROUP;
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}
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else
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hw_abort (me, "internal error - unknown group id");
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@ -390,7 +392,7 @@ find_highest_interrupt_group (struct hw *me,
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selected = FIRST_NMI_GROUP;
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controller->group[FIRST_NMI_GROUP].level = 7;
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for (gid = FIRST_INT_GROUP; gid <= LAST_INT_GROUP; gid++)
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for (gid = FIRST_LEVEL_GROUP; gid <= LAST_LEVEL_GROUP; gid++)
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{
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struct mn103int_group *group = &controller->group[gid];
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if ((group->request & group->enable) != 0)
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@ -491,12 +493,12 @@ mn103int_port_event (struct hw *me,
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if ((group->request & group->enable) != 0)
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{
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HW_TRACE ((me, "port-out NMI"));
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hw_port_event (me, NMI_PORT, 0, NULL, NULL_CIA);
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hw_port_event (me, NMI_PORT, 1, NULL, NULL_CIA);
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}
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break;
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}
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case INT_GROUP:
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case LEVEL_GROUP:
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{
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/* if an interrupt is now pending */
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HW_TRACE ((me, "port-in port=%d group=%d interrupt=%d - INT",
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@ -513,12 +515,24 @@ mn103int_port_event (struct hw *me,
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/* Read/write to to an ICR (group control register) */
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static struct mn103int_group *
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decode_group (struct hw *me,
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struct mn103int *controller,
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unsigned_word base,
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unsigned_word *offset)
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{
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int gid = (base / 8) % NR_GROUPS;
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*offset = (base % 8);
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return &controller->group[gid];
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}
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static unsigned8
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read_icr (struct hw *me,
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struct mn103int *controller,
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struct mn103int_group *group,
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unsigned_word offset)
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unsigned_word base)
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{
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unsigned_word offset;
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struct mn103int_group *group = decode_group (me, controller, base, &offset);
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unsigned8 val = 0;
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switch (group->type)
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{
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@ -528,25 +542,35 @@ read_icr (struct hw *me,
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{
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case 0:
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val = INSERT_ID (group->request);
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HW_TRACE ((me, "read-icr 0x%02x", val));
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HW_TRACE ((me, "read-icr group=%d nmi 0x%02x",
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group->gid, val));
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break;
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default:
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break;
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}
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break;
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case INT_GROUP:
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case LEVEL_GROUP:
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switch (offset)
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{
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case 0:
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val = (INSERT_IR (group->request)
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| INSERT_ID (group->request & group->enable));
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HW_TRACE ((me, "read-icr 0:0x%02x", val));
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HW_TRACE ((me, "read-icr group=%d level 0 0x%02x",
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group->gid, val));
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break;
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case 1:
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val = (INSERT_LV (group->level)
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| INSERT_IE (group->enable));
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HW_TRACE ((me, "read-icr 1:0x%02x", val));
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HW_TRACE ((me, "read-icr level-%d level 1 0x%02x",
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group->gid, val));
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break;
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}
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break;
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default:
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break;
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}
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return val;
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@ -555,10 +579,11 @@ read_icr (struct hw *me,
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static void
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write_icr (struct hw *me,
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struct mn103int *controller,
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struct mn103int_group *group,
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unsigned_word offset,
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unsigned8 val)
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unsigned_word base,
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unsigned8 val)
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{
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unsigned_word offset;
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struct mn103int_group *group = decode_group (me, controller, base, &offset);
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switch (group->type)
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{
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@ -566,7 +591,8 @@ write_icr (struct hw *me,
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switch (offset)
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{
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case 0:
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HW_TRACE ((me, "write-icr 0x%02x", val));
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HW_TRACE ((me, "write-icr group=%d nmi 0x%02x",
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group->gid, val));
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group->request &= ~EXTRACT_ID (val);
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break;
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default:
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@ -574,17 +600,19 @@ write_icr (struct hw *me,
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}
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break;
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case INT_GROUP:
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case LEVEL_GROUP:
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switch (offset)
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{
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case 0: /* request/detect */
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/* Clear any ID bits and then set them according to IR */
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HW_TRACE ((me, "write-icr 0:0x%02x", val));
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HW_TRACE ((me, "write-icr group=%d level 0 0x%02x",
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group->gid, val));
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group->request &= EXTRACT_ID (val);
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group->request |= EXTRACT_IR (val) & EXTRACT_ID (val);
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break;
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case 1: /* level/enable */
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HW_TRACE ((me, "write-icr 1:0x%02x", val));
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HW_TRACE ((me, "write-icr group=%d level 1 0x%02x",
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group->gid, val));
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group->level = EXTRACT_LV (val);
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group->enable = EXTRACT_IE (val);
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break;
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@ -595,6 +623,9 @@ write_icr (struct hw *me,
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push_interrupt_level (me, controller);
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break;
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default:
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break;
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}
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}
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@ -616,10 +647,13 @@ read_iagr (struct hw *me,
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& controller->group[val].enable))
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/* oops, lost the request */
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val = 0;
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HW_TRACE ((me, "read-iagr %d", (int) val));
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break;
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}
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default:
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val = 0;
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HW_TRACE ((me, "read-iagr 0x%08lx bad offset", (long) offset));
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break;
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}
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return val;
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}
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@ -658,6 +692,7 @@ read_extmd (struct hw *me,
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val |= (group[gid].trigger << (gid * 2));
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}
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}
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HW_TRACE ((me, "read-extmd 0x%02lx", (long) val));
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return val;
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}
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@ -677,6 +712,7 @@ write_extmd (struct hw *me,
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/* MAYBE: interrupts already pending? */
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}
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}
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HW_TRACE ((me, "write-extmd 0x%02lx", (long) val));
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}
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@ -685,29 +721,23 @@ write_extmd (struct hw *me,
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static int
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decode_addr (struct hw *me,
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struct mn103int *controller,
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unsigned_word addr)
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unsigned_word address,
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unsigned_word *offset)
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{
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int i;
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for (i = 0; i < NR_BLOCKS; i++)
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{
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if (addr >= controller->block[i].base
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&& addr <= controller->block[i].bound)
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return i;
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if (address >= controller->block[i].base
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&& address <= controller->block[i].bound)
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{
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*offset = address - controller->block[i].base;
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return i;
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}
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}
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hw_abort (me, "bad address");
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return -1;
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}
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static struct mn103int_group *
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decode_group (struct hw *me,
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struct mn103int *controller,
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unsigned_word addr)
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{
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unsigned_word offset = (addr - controller->block[ICR_BLOCK].base);
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int gid = (offset / 8) % NR_GROUPS;
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return &controller->group[gid];
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}
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static unsigned
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mn103int_io_read_buffer (struct hw *me,
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void *dest,
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@ -720,21 +750,21 @@ mn103int_io_read_buffer (struct hw *me,
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struct mn103int *controller = hw_data (me);
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unsigned8 *buf = dest;
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unsigned byte;
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HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
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for (byte = 0; byte < nr_bytes; byte++)
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{
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unsigned_word address = base + byte;
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switch (decode_addr (me, controller, address))
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unsigned_word offset;
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switch (decode_addr (me, controller, address, &offset))
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{
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case ICR_BLOCK:
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buf[byte] = read_icr (me, controller,
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decode_group (me, controller, address),
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address);
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buf[byte] = read_icr (me, controller, offset);
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break;
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case IAGR_BLOCK:
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buf[byte] = read_iagr (me, controller, address);
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buf[byte] = read_iagr (me, controller, offset);
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break;
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case EXTMD_BLOCK:
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buf[byte] = read_extmd (me, controller, address);
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buf[byte] = read_extmd (me, controller, offset);
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break;
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default:
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hw_abort (me, "bad switch");
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@ -755,21 +785,21 @@ mn103int_io_write_buffer (struct hw *me,
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struct mn103int *controller = hw_data (me);
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const unsigned8 *buf = source;
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unsigned byte;
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HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
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for (byte = 0; byte < nr_bytes; byte++)
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{
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unsigned_word address = base + byte;
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switch (decode_addr (me, controller, address))
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unsigned_word offset;
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switch (decode_addr (me, controller, address, &offset))
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{
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case ICR_BLOCK:
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write_icr (me, controller,
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decode_group (me, controller, address),
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address, buf[byte]);
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write_icr (me, controller, offset, buf[byte]);
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break;
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case IAGR_BLOCK:
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/* not allowed */
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break;
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case EXTMD_BLOCK:
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write_extmd (me, controller, address, buf[byte]);
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write_extmd (me, controller, offset, buf[byte]);
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break;
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default:
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hw_abort (me, "bad switch");
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