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* mn10300-opc.c: Add some comments explaining the various
operands and such.
* mn10300-dis.c (disassemble): Fix minor gcc -Wall warnings.
This commit is contained in:
Jeff Law
parent
b2f7a7e5b3
commit
8329699005
@ -1,3 +1,10 @@
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Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com)
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* mn10300-opc.c: Add some comments explaining the various
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operands and such.
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* mn10300-dis.c (disassemble): Fix minor gcc -Wall warnings.
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Thu Dec 5 12:09:48 1996 J.T. Conklin <jtc@rtl.cygnus.com>
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* m68k-dis.c (print_insn_arg): Handle new < and > operand
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@ -283,7 +283,7 @@ disassemble (memaddr, info, insn, extension, size)
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&& size == mysize)
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{
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const unsigned char *opindex_ptr;
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unsigned int nocomma, memop;
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unsigned int nocomma;
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int paren = 0;
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match = 1;
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@ -304,7 +304,7 @@ disassemble (memaddr, info, insn, extension, size)
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value = insn & ((1 << operand->bits) - 1);
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value <<= (32 - operand->bits);
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temp = extension >> operand->shift;
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temp &= ((1 << 32 - operand->bits) - 1);
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temp &= ((1 << (32 - operand->bits)) - 1);
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value |= temp;
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}
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else if ((operand->flags & MN10300_OPERAND_EXTENDED) != 0)
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@ -23,51 +23,71 @@ const struct mn10300_operand mn10300_operands[] = {
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#define UNUSED 0
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{0, 0, 0},
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/* dn register in the first register operand position. */
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#define DN0 (UNUSED+1)
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{2, 0, MN10300_OPERAND_DREG},
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/* dn register in the second register operand position. */
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#define DN1 (DN0+1)
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{2, 2, MN10300_OPERAND_DREG},
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/* dn register in the third register operand position. */
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#define DN2 (DN1+1)
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{2, 4, MN10300_OPERAND_DREG},
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/* dm register in the first register operand position. */
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#define DM0 (DN2+1)
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{2, 0, MN10300_OPERAND_DREG},
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/* dm register in the second register operand position. */
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#define DM1 (DM0+1)
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{2, 2, MN10300_OPERAND_DREG},
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/* dm register in the third register operand position. */
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#define DM2 (DM1+1)
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{2, 4, MN10300_OPERAND_DREG},
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/* an register in the first register operand position. */
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#define AN0 (DM2+1)
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{2, 0, MN10300_OPERAND_AREG},
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/* an register in the second register operand position. */
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#define AN1 (AN0+1)
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{2, 2, MN10300_OPERAND_AREG},
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/* an register in the third register operand position. */
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#define AN2 (AN1+1)
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{2, 4, MN10300_OPERAND_AREG},
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/* am register in the first register operand position. */
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#define AM0 (AN2+1)
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{2, 0, MN10300_OPERAND_AREG},
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/* am register in the second register operand position. */
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#define AM1 (AM0+1)
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{2, 2, MN10300_OPERAND_AREG},
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/* am register in the third register operand position. */
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#define AM2 (AM1+1)
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{2, 4, MN10300_OPERAND_AREG},
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/* 8 bit unsigned immediate which may promote to a 16bit
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unsigned immediate. */
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#define IMM8 (AM2+1)
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{8, 0, MN10300_OPERAND_PROMOTE},
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/* 16 bit unsigned immediate which may promote to a 32bit
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unsigned immediate. */
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#define IMM16 (IMM8+1)
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{16, 0, MN10300_OPERAND_PROMOTE},
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/* 16 bit pc-relative immediate which may promote to a 16bit
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pc-relative immediate. */
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#define IMM16_PCREL (IMM16+1)
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{16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_PCREL},
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/* 16bit unsigned dispacement in a memory operation which
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may promote to a 32bit displacement. */
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#define IMM16_MEM (IMM16_PCREL+1)
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{16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
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@ -79,9 +99,11 @@ const struct mn10300_operand mn10300_operands[] = {
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#define IMM32 (IMM16_MEM+1)
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{16, 0, MN10300_OPERAND_SPLIT},
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/* 32bit pc-relative offset. */
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#define IMM32_PCREL (IMM32+1)
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{16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
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/* 32bit memory offset. */
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#define IMM32_MEM (IMM32_PCREL+1)
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{16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
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@ -111,63 +133,82 @@ const struct mn10300_operand mn10300_operands[] = {
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#define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1)
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{24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
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/* Stack pointer. */
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#define SP (IMM32_HIGH24_LOWSHIFT16+1)
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{8, 0, MN10300_OPERAND_SP},
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/* Processor status word. */
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#define PSW (SP+1)
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{0, 0, MN10300_OPERAND_PSW},
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/* MDR register. */
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#define MDR (PSW+1)
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{0, 0, MN10300_OPERAND_MDR},
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/* Index register. */
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#define DI (MDR+1)
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{2, 2, MN10300_OPERAND_DREG},
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/* 8 bit signed displacement, may promote to 16bit signed dispacement. */
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#define SD8 (DI+1)
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{8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
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/* 16 bit signed displacement, may promote to 32bit dispacement. */
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#define SD16 (SD8+1)
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{16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
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/* 8 bit signed displacement that can not promote. */
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#define SD8N (SD16+1)
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{8, 0, MN10300_OPERAND_SIGNED},
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/* 8 bit pc-relative displacement. */
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#define SD8N_PCREL (SD8N+1)
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{8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL},
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/* 8 bit signed displacement shifted left 8 bits in the instruction. */
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#define SD8N_SHIFT8 (SD8N_PCREL+1)
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{8, 8, MN10300_OPERAND_SIGNED},
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/* 8 bit signed immediate which may promote to 16bit signed immediate. */
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#define SIMM8 (SD8N_SHIFT8+1)
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{8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
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/* 16 bit signed immediate which may promote to 32bit immediate. */
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#define SIMM16 (SIMM8+1)
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{16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
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/* Either an open paren or close paren. */
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#define PAREN (SIMM16+1)
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{0, 0, MN10300_OPERAND_PAREN},
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/* dn register that appears in the first and second register positions. */
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#define DN01 (PAREN+1)
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{2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED},
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/* an register that appears in the first and second register positions. */
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#define AN01 (DN01+1)
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{2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},
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/* 16bit pc-relative displacement which may promote to 32bit pc-relative
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displacement. */
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#define D16_SHIFT (AN01+1)
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{16, 8, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_PCREL},
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/* 8 bit immediate found in the extension word. */
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#define IMM8E (D16_SHIFT+1)
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{8, 0, MN10300_OPERAND_EXTENDED},
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/* Register list found in the extension word shifted 8 bits left. */
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#define REGSE_SHIFT8 (IMM8E+1)
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{8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST},
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/* Register list shifted 8 bits left. */
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#define REGS_SHIFT8 (REGSE_SHIFT8 + 1)
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{8, 8, MN10300_OPERAND_REG_LIST},
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/* Reigster list. */
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#define REGS (REGS_SHIFT8+1)
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{8, 0, MN10300_OPERAND_REG_LIST},
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} ;
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#define MEM(ADDR) PAREN, ADDR, PAREN
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