mirror of
https://github.com/darlinghq/darling-gdb.git
synced 2024-11-28 22:40:24 +00:00
* Garbage collection overdue since January.
This commit is contained in:
Frank Ch. Eigler
parent
7b9f7f9917
commit
83657d850c
@ -1,75 +0,0 @@
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# .Sanitize for devo/sim/txvu.
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# Each directory to survive it's way into a release will need a file
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# like this one called "./.Sanitize". All keyword lines must exist,
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# and must exist in the order specified by this file. Each directory
|
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# in the tree will be processed, top down, in the following order.
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# Hash started lines like this one are comments and will be deleted
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# before anything else is done. Blank lines will also be squashed
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# out.
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# The lines between the "Do-first:" line and the "Things-to-keep:"
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# line are executed as a /bin/sh shell script before anything else is
|
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# done in this
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Do-first:
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# All files listed between the "Things-to-keep:" line and the
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||||
# "Files-to-sed:" line will be kept. All other files will be removed.
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# Directories listed in this section will have their own Sanitize
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# called. Directories not listed will be removed in their entirety
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# with rm -rf.
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|
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Things-to-keep:
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||||
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ChangeLog
|
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Makefile.in
|
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README.Cygnus
|
||||
acconfig.h
|
||||
config.in
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||||
configure
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||||
configure.in
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||||
device.c
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device.h
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dma.c
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dma.h
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engine-sky.c
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gencode.c
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gpuif.c
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gpuif.h
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hardware.c
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hardware.h
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interp.c
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libvpe.c
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libvpe.h
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m16.igen
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mdmx.igen
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mips.dc
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mips.igen
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pke.c
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pke.h
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r5900.igen
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sim-main.h
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tconfig.in
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vpe.h
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vr5400.igen
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vu.h
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vu0.c
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vu0.h
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vu1.c
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vu1.h
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Things-to-lose:
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Do-last:
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for i in * ; do
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if test ! -d $i && (grep sanitize $i > /dev/null) ; then
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echo '***' Some mentions of Sanitize are still left in $i! 1>&2
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fi
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done
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# End of file.
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@ -1,63 +0,0 @@
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Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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* config.in: Ditto.
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Sun Apr 26 15:19:30 1998 Tom Tromey <tromey@cygnus.com>
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* acconfig.h: New file.
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* configure.in: Reverted change of Apr 24; use sinclude again.
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Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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* config.in: Ditto.
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Fri Apr 24 11:18:16 1998 Tom Tromey <tromey@cygnus.com>
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* configure.in: Don't call sinclude.
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Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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Wed Mar 11 14:14:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (sim_write, sim_read, load_memory, store_memory):
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Replace sim_core_*_map with read_map, write_map, exec_map resp.
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Tue Jan 27 18:24:01 1998 Ian Carmichael <iancarm@cygnus.com>
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* Very, very early support for vu1 based on sce code.
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Thu Jan 22 15:44:46 1998 Ian Carmichael <iancarm@cygnus.com>
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* Incorporate GPR_SET from mips/sim-main.h.
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Fri Jan 16 14:25:54 1998 Ian Carmichael <iancarm@cygnus.com>
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* Devices now get decode() call.
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Fri Jan 16 14:25:54 1998 Ian Carmichael <iancarm@cygnus.com>
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* Initial Device Support.
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Thu Jan 15 10:25:54 1998 Ian Carmichael <iancarm@cygnus.com>
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* ChangeLog created.
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@ -1,262 +0,0 @@
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# template for Configure for the MIPS simulator.
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# Written by Cygnus Support.
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## COMMON_PRE_CONFIG_FRAG
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srcdir=@srcdir@
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srcroot=$(srcdir)/../../
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SIM_NO_OBJ =
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SIM_IGEN_OBJ = \
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support.o \
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itable.o \
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semantics.o \
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idecode.o \
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icache.o \
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irun.o
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SIM_M16_OBJ = \
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$(SIM_IGEN_OBJ) = \
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m16_support.o \
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m16_itable.o \
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m16_semantics.o \
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m16_idecode.o \
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m16_icache.o \
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m16_engine.o \
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m16_irun.o
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SIM_OBJS = \
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$(SIM_@sim_gen@_OBJ) \
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$(SIM_NEW_COMMON_OBJS) \
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engine-sky.o \
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interp.o \
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hardware.o \
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device.o \
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gpuif.o \
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dma.o \
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vu0.o \
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vu1.o \
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libvpe.o \
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pke.o \
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sim-hload.o \
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sim-engine.o \
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sim-stop.o \
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sim-resume.o \
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sim-reason.o
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# List of flags to always pass to $(CC).
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SIM_SUBTARGET=@SIM_SUBTARGET@
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SIM_NO_CFLAGS = -DWITH_IGEN=0
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SIM_IGEN_CFLAGS = -DWITH_IGEN=1
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SIM_M16_CFLAGS = -DWITH_IGEN=1
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# FIXME: Hack to find syscall.h? Better support for syscall.h
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# is in progress.
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SIM_EXTRA_CFLAGS = \
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$(SIM_SUBTARGET) \
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-I$(srcdir)/../../newlib/libc/sys/idt \
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$(SIM_@sim_gen@_CFLAGS)
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SIM_EXTRA_CCFLAGS = $(SIM_EXTRA_CFLAGS)
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SIM_EXTRA_CLEAN = clean-igen clean-m16 clean-extra
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SIM_EXTRA_ALL = $(SIM_@sim_gen@_ALL)
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# List of main object files for `run'.
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SIM_RUN_OBJS = nrun.o
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## COMMON_POST_CONFIG_FRAG
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interp.o: $(srcdir)/interp.c config.h sim-main.h oengine.c
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oengine.c: gencode
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./gencode @SIMCONF@ > tmp-oengine
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mv tmp-oengine oengine.c
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gencode: gencode.o getopt.o getopt1.o
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$(CC_FOR_BUILD) -o $@ gencode.o getopt.o getopt1.o
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gencode.o: $(srcdir)/gencode.c
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$(CC_FOR_BUILD) -c -g -I${srcroot}/include $(srcdir)/gencode.c
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getopt.o: $(srcdir)/../../libiberty/getopt.c
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$(CC_FOR_BUILD) -c -g -I${srcroot}/include $(srcdir)/../../libiberty/getopt.c
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getopt1.o: $(srcdir)/../../libiberty/getopt1.c
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$(CC_FOR_BUILD) -c -g -I${srcroot}/include $(srcdir)/../../libiberty/getopt1.c
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../igen/igen:
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cd ../igen && $(MAKE)
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IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
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IGEN_INSN=$(srcdir)/mips.igen
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IGEN_DC=$(srcdir)/mips.dc
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IGEN_INCLUDE=\
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$(start-sanitize-r5900) \
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$(srcdir)/r5900.igen \
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$(end-sanitize-r5900) \
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$(start-sanitize-vr5400) \
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$(srcdir)/vr5400.igen \
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$(srcdir)/mdmx.igen \
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$(end-sanitize-vr5400) \
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$(srcdir)/m16.igen
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SIM_IGEN_ALL = tmp-igen
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BUILT_SRC_FROM_IGEN = \
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icache.h \
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icache.c \
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idecode.h \
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idecode.c \
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semantics.h \
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semantics.c \
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model.h \
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model.c \
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support.h \
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support.c \
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itable.h \
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itable.c \
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engine.h \
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engine.c \
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irun.c
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$(BUILT_SRC_FROM_IGEN): tmp-igen
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.PHONY: clean-igen
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clean-igen:
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rm -f $(BUILT_SRC_FROM_IGEN)
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rm -f tmp-igen
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||||
|
||||
tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
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cd ../igen && $(MAKE)
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../igen/igen \
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$(IGEN_TRACE) \
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-I $(srcdir) \
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-Werror \
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-Wnodiscard \
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@sim_igen_flags@ \
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-G gen-direct-access \
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-G gen-zero-r0 \
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-i $(IGEN_INSN) \
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-o $(IGEN_DC) \
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-x \
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-n icache.h -hc tmp-icache.h \
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-n icache.c -c tmp-icache.c \
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-n semantics.h -hs tmp-semantics.h \
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||||
-n semantics.c -s tmp-semantics.c \
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-n idecode.h -hd tmp-idecode.h \
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||||
-n idecode.c -d tmp-idecode.c \
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||||
-n model.h -hm tmp-model.h \
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-n model.c -m tmp-model.c \
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||||
-n support.h -hf tmp-support.h \
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||||
-n support.c -f tmp-support.c \
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||||
-n itable.h -ht tmp-itable.h \
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||||
-n itable.c -t tmp-itable.c \
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-n engine.h -he tmp-engine.h \
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||||
-n engine.c -e tmp-engine.c \
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||||
-n irun.c -r tmp-irun.c
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||||
$(srcdir)/../../move-if-change tmp-icache.h icache.h
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||||
$(srcdir)/../../move-if-change tmp-icache.c icache.c
|
||||
$(srcdir)/../../move-if-change tmp-idecode.h idecode.h
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||||
$(srcdir)/../../move-if-change tmp-idecode.c idecode.c
|
||||
$(srcdir)/../../move-if-change tmp-semantics.h semantics.h
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||||
$(srcdir)/../../move-if-change tmp-semantics.c semantics.c
|
||||
$(srcdir)/../../move-if-change tmp-model.h model.h
|
||||
$(srcdir)/../../move-if-change tmp-model.c model.c
|
||||
$(srcdir)/../../move-if-change tmp-support.h support.h
|
||||
$(srcdir)/../../move-if-change tmp-support.c support.c
|
||||
$(srcdir)/../../move-if-change tmp-itable.h itable.h
|
||||
$(srcdir)/../../move-if-change tmp-itable.c itable.c
|
||||
$(srcdir)/../../move-if-change tmp-engine.h engine.h
|
||||
$(srcdir)/../../move-if-change tmp-engine.c engine.c
|
||||
$(srcdir)/../../move-if-change tmp-irun.c irun.c
|
||||
touch tmp-igen
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||||
|
||||
semantics.o: sim-main.h $(SIM_EXTRA_DEPS)
|
||||
engine.o: sim-main.h $(SIM_EXTRA_DEPS)
|
||||
support.o: sim-main.h $(SIM_EXTRA_DEPS)
|
||||
idecode.o: sim-main.h $(SIM_EXTRA_DEPS)
|
||||
itable.o: sim-main.h $(SIM_EXTRA_DEPS)
|
||||
|
||||
|
||||
|
||||
SIM_M16_ALL = tmp-igen $(SIM_M16_ALL)
|
||||
|
||||
BUILT_SRC_FROM_M16 = \
|
||||
m16_icache.h \
|
||||
m16_icache.c \
|
||||
m16_idecode.h \
|
||||
m16_idecode.c \
|
||||
m16_semantics.h \
|
||||
m16_semantics.c \
|
||||
m16_model.h \
|
||||
m16_model.c \
|
||||
m16_support.h \
|
||||
m16_support.c \
|
||||
m16_itable.h \
|
||||
m16_itable.c \
|
||||
m16_engine.h \
|
||||
m16_engine.c \
|
||||
m16_irun.c
|
||||
|
||||
$(BUILT_SRC_FROM_M16): tmp-m16
|
||||
|
||||
.PHONY: clean-m16
|
||||
clean-m16:
|
||||
rm -f $(BUILT_SRC_FROM_M16)
|
||||
rm -f tmp-m16
|
||||
|
||||
tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
|
||||
cd ../igen && $(MAKE)
|
||||
../igen/igen \
|
||||
$(IGEN_TRACE) \
|
||||
-I $(srcdir) \
|
||||
-Werror \
|
||||
-Wnodiscard \
|
||||
-F 16 \
|
||||
-M mips16 \
|
||||
-G gen-direct-access \
|
||||
-i $(IGEN_INSN) \
|
||||
-o $(IGEN_DC) \
|
||||
-x \
|
||||
-n m16_icache.h -hc tmp-icache.h \
|
||||
-n m16_icache.c -c tmp-icache.c \
|
||||
-n m16_semantics.h -hs tmp-semantics.h \
|
||||
-n m16_semantics.c -s tmp-semantics.c \
|
||||
-n m16_idecode.h -hd tmp-idecode.h \
|
||||
-n m16_idecode.c -d tmp-idecode.c \
|
||||
-n m16_model.h -hm tmp-model.h \
|
||||
-n m16_model.c -m tmp-model.c \
|
||||
-n m16_support.h -hf tmp-support.h \
|
||||
-n m16_support.c -f tmp-support.c \
|
||||
-n m16_itable.h -ht tmp-itable.h \
|
||||
-n m16_itable.c -t tmp-itable.c \
|
||||
-n m16_engine.h -he tmp-engine.h \
|
||||
-n m16_engine.c -e tmp-engine.c \
|
||||
-n m16_irun.c -r tmp-irun.c
|
||||
$(srcdir)/../../move-if-change tmp-icache.h m16_icache.h
|
||||
$(srcdir)/../../move-if-change tmp-icache.c m16_icache.c
|
||||
$(srcdir)/../../move-if-change tmp-idecode.h m16_idecode.h
|
||||
$(srcdir)/../../move-if-change tmp-idecode.c m16_idecode.c
|
||||
$(srcdir)/../../move-if-change tmp-semantics.h m16_semantics.h
|
||||
$(srcdir)/../../move-if-change tmp-semantics.c m16_semantics.c
|
||||
$(srcdir)/../../move-if-change tmp-model.h m16_model.h
|
||||
$(srcdir)/../../move-if-change tmp-model.c m16_model.c
|
||||
$(srcdir)/../../move-if-change tmp-support.h m16_support.h
|
||||
$(srcdir)/../../move-if-change tmp-support.c m16_support.c
|
||||
$(srcdir)/../../move-if-change tmp-itable.h m16_itable.h
|
||||
$(srcdir)/../../move-if-change tmp-itable.c m16_itable.c
|
||||
$(srcdir)/../../move-if-change tmp-engine.h m16_engine.h
|
||||
$(srcdir)/../../move-if-change tmp-engine.c m16_engine.c
|
||||
$(srcdir)/../../move-if-change tmp-irun.c m16_irun.c
|
||||
touch tmp-m16
|
||||
|
||||
|
||||
clean-extra:
|
||||
rm -f gencode oengine.c tmp.igen
|
||||
@ -1,38 +0,0 @@
|
||||
> README.Cygnus
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
The following are the main reasons for constructing the simulator as a
|
||||
generator:
|
||||
|
||||
1) Avoid large fixed decode source file, with lots of #ifs controlling
|
||||
the compilation. i.e. keep the source cleaner, smaller and easier
|
||||
to parse.
|
||||
|
||||
2) Allow optimum code to be created, without run-time checks on
|
||||
instruction types. Ensure that the simulator engine only includes
|
||||
code for the architecture being targetted. e.g. This avoids
|
||||
run-time checks on ISA conformance, aswell as increasing
|
||||
throughput.
|
||||
|
||||
3) Allow updates to the instruction sets to be added quickly. Having a
|
||||
table means that the information is together, and is easier to
|
||||
manipulate. Having the table generate the engine, rather than the
|
||||
run-time parse the table gives higher performance at simulation
|
||||
time.
|
||||
|
||||
4) Keep all the similar simulation code together. i.e. have a single
|
||||
place where, for example, the addition code is held. This ensures that
|
||||
updates to the simulation are not spread over a large flat source
|
||||
file maintained by the developer.
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
To keep the simulator simple (and to avoid the slight chance of
|
||||
mis-matched files) the manifests describing an engine, and the
|
||||
simulator engine itself, are held in the same source file.
|
||||
|
||||
This means that the engine must be included twice, with the first pass
|
||||
controlled by the SIM_MANIFESTS definition.
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
> EOF README.Cygnus
|
||||
@ -1,15 +0,0 @@
|
||||
|
||||
/* Define to 1 if NLS is requested. */
|
||||
#undef ENABLE_NLS
|
||||
|
||||
/* Define as 1 if you have catgets and don't want to use GNU gettext. */
|
||||
#undef HAVE_CATGETS
|
||||
|
||||
/* Define as 1 if you have gettext and don't want to use GNU gettext. */
|
||||
#undef HAVE_GETTEXT
|
||||
|
||||
/* Define as 1 if you have the stpcpy function. */
|
||||
#undef HAVE_STPCPY
|
||||
|
||||
/* Define if your locale.h file contains LC_MESSAGES. */
|
||||
#undef HAVE_LC_MESSAGES
|
||||
@ -1,174 +0,0 @@
|
||||
/* config.in. Generated automatically from configure.in by autoheader. */
|
||||
|
||||
/* Define if using alloca.c. */
|
||||
#undef C_ALLOCA
|
||||
|
||||
/* Define to empty if the keyword does not work. */
|
||||
#undef const
|
||||
|
||||
/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems.
|
||||
This function is required for alloca.c support on those systems. */
|
||||
#undef CRAY_STACKSEG_END
|
||||
|
||||
/* Define if you have alloca, as a function or macro. */
|
||||
#undef HAVE_ALLOCA
|
||||
|
||||
/* Define if you have <alloca.h> and it should be used (not on Ultrix). */
|
||||
#undef HAVE_ALLOCA_H
|
||||
|
||||
/* Define if you have a working `mmap' system call. */
|
||||
#undef HAVE_MMAP
|
||||
|
||||
/* Define as __inline if that's what the C compiler calls it. */
|
||||
#undef inline
|
||||
|
||||
/* Define to `long' if <sys/types.h> doesn't define. */
|
||||
#undef off_t
|
||||
|
||||
/* Define if you need to in order for stat and other things to work. */
|
||||
#undef _POSIX_SOURCE
|
||||
|
||||
/* Define as the return type of signal handlers (int or void). */
|
||||
#undef RETSIGTYPE
|
||||
|
||||
/* Define to `unsigned' if <sys/types.h> doesn't define. */
|
||||
#undef size_t
|
||||
|
||||
/* If using the C implementation of alloca, define if you know the
|
||||
direction of stack growth for your system; otherwise it will be
|
||||
automatically deduced at run-time.
|
||||
STACK_DIRECTION > 0 => grows toward higher addresses
|
||||
STACK_DIRECTION < 0 => grows toward lower addresses
|
||||
STACK_DIRECTION = 0 => direction of growth unknown
|
||||
*/
|
||||
#undef STACK_DIRECTION
|
||||
|
||||
/* Define if you have the ANSI C header files. */
|
||||
#undef STDC_HEADERS
|
||||
|
||||
/* Define if your processor stores words with the most significant
|
||||
byte first (like Motorola and SPARC, unlike Intel and VAX). */
|
||||
#undef WORDS_BIGENDIAN
|
||||
|
||||
/* Define to 1 if NLS is requested. */
|
||||
#undef ENABLE_NLS
|
||||
|
||||
/* Define as 1 if you have gettext and don't want to use GNU gettext. */
|
||||
#undef HAVE_GETTEXT
|
||||
|
||||
/* Define as 1 if you have the stpcpy function. */
|
||||
#undef HAVE_STPCPY
|
||||
|
||||
/* Define if your locale.h file contains LC_MESSAGES. */
|
||||
#undef HAVE_LC_MESSAGES
|
||||
|
||||
/* Define if you have the __argz_count function. */
|
||||
#undef HAVE___ARGZ_COUNT
|
||||
|
||||
/* Define if you have the __argz_next function. */
|
||||
#undef HAVE___ARGZ_NEXT
|
||||
|
||||
/* Define if you have the __argz_stringify function. */
|
||||
#undef HAVE___ARGZ_STRINGIFY
|
||||
|
||||
/* Define if you have the __setfpucw function. */
|
||||
#undef HAVE___SETFPUCW
|
||||
|
||||
/* Define if you have the aint function. */
|
||||
#undef HAVE_AINT
|
||||
|
||||
/* Define if you have the anint function. */
|
||||
#undef HAVE_ANINT
|
||||
|
||||
/* Define if you have the dcgettext function. */
|
||||
#undef HAVE_DCGETTEXT
|
||||
|
||||
/* Define if you have the getcwd function. */
|
||||
#undef HAVE_GETCWD
|
||||
|
||||
/* Define if you have the getpagesize function. */
|
||||
#undef HAVE_GETPAGESIZE
|
||||
|
||||
/* Define if you have the getrusage function. */
|
||||
#undef HAVE_GETRUSAGE
|
||||
|
||||
/* Define if you have the munmap function. */
|
||||
#undef HAVE_MUNMAP
|
||||
|
||||
/* Define if you have the putenv function. */
|
||||
#undef HAVE_PUTENV
|
||||
|
||||
/* Define if you have the setenv function. */
|
||||
#undef HAVE_SETENV
|
||||
|
||||
/* Define if you have the setlocale function. */
|
||||
#undef HAVE_SETLOCALE
|
||||
|
||||
/* Define if you have the sigaction function. */
|
||||
#undef HAVE_SIGACTION
|
||||
|
||||
/* Define if you have the sqrt function. */
|
||||
#undef HAVE_SQRT
|
||||
|
||||
/* Define if you have the stpcpy function. */
|
||||
#undef HAVE_STPCPY
|
||||
|
||||
/* Define if you have the strcasecmp function. */
|
||||
#undef HAVE_STRCASECMP
|
||||
|
||||
/* Define if you have the strchr function. */
|
||||
#undef HAVE_STRCHR
|
||||
|
||||
/* Define if you have the time function. */
|
||||
#undef HAVE_TIME
|
||||
|
||||
/* Define if you have the <argz.h> header file. */
|
||||
#undef HAVE_ARGZ_H
|
||||
|
||||
/* Define if you have the <fcntl.h> header file. */
|
||||
#undef HAVE_FCNTL_H
|
||||
|
||||
/* Define if you have the <fpu_control.h> header file. */
|
||||
#undef HAVE_FPU_CONTROL_H
|
||||
|
||||
/* Define if you have the <limits.h> header file. */
|
||||
#undef HAVE_LIMITS_H
|
||||
|
||||
/* Define if you have the <locale.h> header file. */
|
||||
#undef HAVE_LOCALE_H
|
||||
|
||||
/* Define if you have the <malloc.h> header file. */
|
||||
#undef HAVE_MALLOC_H
|
||||
|
||||
/* Define if you have the <nl_types.h> header file. */
|
||||
#undef HAVE_NL_TYPES_H
|
||||
|
||||
/* Define if you have the <stdlib.h> header file. */
|
||||
#undef HAVE_STDLIB_H
|
||||
|
||||
/* Define if you have the <string.h> header file. */
|
||||
#undef HAVE_STRING_H
|
||||
|
||||
/* Define if you have the <strings.h> header file. */
|
||||
#undef HAVE_STRINGS_H
|
||||
|
||||
/* Define if you have the <sys/param.h> header file. */
|
||||
#undef HAVE_SYS_PARAM_H
|
||||
|
||||
/* Define if you have the <sys/resource.h> header file. */
|
||||
#undef HAVE_SYS_RESOURCE_H
|
||||
|
||||
/* Define if you have the <sys/time.h> header file. */
|
||||
#undef HAVE_SYS_TIME_H
|
||||
|
||||
/* Define if you have the <time.h> header file. */
|
||||
#undef HAVE_TIME_H
|
||||
|
||||
/* Define if you have the <unistd.h> header file. */
|
||||
#undef HAVE_UNISTD_H
|
||||
|
||||
/* Define if you have the <values.h> header file. */
|
||||
#undef HAVE_VALUES_H
|
||||
|
||||
/* Define if you have the m library (-lm). */
|
||||
#undef HAVE_LIBM
|
||||
4379
sim/txvu/configure
vendored
4379
sim/txvu/configure
vendored
File diff suppressed because it is too large
Load Diff
@ -1,185 +0,0 @@
|
||||
dnl Process this file with autoconf to produce a configure script.
|
||||
sinclude(../common/aclocal.m4)
|
||||
AC_PREREQ(2.5)dnl
|
||||
AC_INIT(Makefile.in)
|
||||
|
||||
SIM_AC_COMMON
|
||||
|
||||
dnl Options available in this module
|
||||
SIM_AC_OPTION_INLINE(0)
|
||||
SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
|
||||
SIM_AC_OPTION_HOSTENDIAN
|
||||
SIM_AC_OPTION_WARNINGS
|
||||
|
||||
|
||||
# Ensure a reasonable default simulator is constructed:
|
||||
case "${target}" in
|
||||
# start-sanitize-tx19
|
||||
mipstx19*-*-*) SIMCONF="-mips1 -mcpu=r1900 -mno-fp --warnings";;
|
||||
# end-sanitize-tx19
|
||||
# start-sanitize-tx49
|
||||
mips64tx49*-*-*) SIMCONF="-mips3 --warnings -mcpu=r4900";;
|
||||
# end-sanitize-tx49
|
||||
# start-sanitize-r5900
|
||||
mips64r59*-*-*) SIMCONF="-mips3 --warnings -mcpu=r5900";;
|
||||
# end-sanitize-r5900
|
||||
# start-sanitize-sky
|
||||
txvu-*-*) SIMCONF="-mips3 --warnings -mcpu=r5900";;
|
||||
# end-sanitize-sky
|
||||
mips64*-*-*) SIMCONF="-mips0 --warnings";;
|
||||
mips16*-*-*) SIMCONF="-mips0 --warnings";;
|
||||
mips*-*-*) SIMCONF="-mips2 --warnings";;
|
||||
*) SIMCONF="-mips0 --warnings";;
|
||||
esac
|
||||
AC_SUBST(SIMCONF)
|
||||
|
||||
case "${target}" in
|
||||
# start-sanitize-tx19
|
||||
mipstx19*-*-*) SIM_SUBTARGET="-DSUBTARGET_R3900=1";;
|
||||
# end-sanitize-tx19
|
||||
*) SIM_SUBTARGET="";;
|
||||
esac
|
||||
AC_SUBST(SIM_SUBTARGET)
|
||||
|
||||
|
||||
#
|
||||
# Select the byte order of the target
|
||||
#
|
||||
case "${target}" in
|
||||
# start-sanitize-tx19
|
||||
mipstx19*-*-*) mips_endian=0 ;;
|
||||
# end-sanitize-tx19
|
||||
# start-sanitize-r5900
|
||||
mips64r59*-*-*) mips_endian=LITTLE_ENDIAN ;;
|
||||
# end-sanitize-r5900
|
||||
# start-sanitize-sky
|
||||
txvu-*-*) mips_endian=LITTLE_ENDIAN ;;
|
||||
# end-sanitize-sky
|
||||
mips64*-*-*) mips_endian=0 ;;
|
||||
mips16*-*-*) mips_endian=0 ;;
|
||||
mips*-*-*) mips_endian=0 ;;
|
||||
*) mips_endian=0 ;;
|
||||
esac
|
||||
SIM_AC_OPTION_ENDIAN($mips_endian)
|
||||
|
||||
|
||||
#
|
||||
# Select the bitsize of the target
|
||||
#
|
||||
case "${target}" in
|
||||
# start-sanitize-tx19
|
||||
mipstx19*-*-*) mips_bitsize=32 ; mips_msb=31 ;;
|
||||
# end-sanitize-tx19
|
||||
# start-sanitize-r5900
|
||||
mips64r59*-*-*) mips_bitsize=64 ; mips_msb=63 ;;
|
||||
# end-sanitize-r5900
|
||||
# start-sanitize-sky
|
||||
txvu-*-*) mips_bitsize=64 ; mips_msb=63 ;;
|
||||
# end-sanitize-sky
|
||||
mips64*-*-*) mips_bitsize=64 ; mips_msb=63 ;;
|
||||
mips16*-*-*) mips_bitsize=64 ; mips_msb=63 ;;
|
||||
mips*-*-*) mips_bitsize=32 ; mips_msb=31 ;;
|
||||
*) mips_bitsize=64 ; mips_msb=63 ;;
|
||||
esac
|
||||
SIM_AC_OPTION_BITSIZE($mips_bitsize,$mips_msb)
|
||||
|
||||
|
||||
#
|
||||
# Select the floating hardware support of the target
|
||||
#
|
||||
mips_fpu=HARDWARE_FLOATING_POINT
|
||||
case "${target}" in
|
||||
# start-sanitize-tx19
|
||||
mipstx19*-*-*) mips_fpu=SOFT_FLOATING_POINT ;;
|
||||
# end-sanitize-tx19
|
||||
# start-sanitize-r5900
|
||||
mips64r59*-*-*) mips_fpu=HARD_FLOATING_POINT ;;
|
||||
# end-sanitize-r5900
|
||||
# start-sanitize-sky
|
||||
txvu-*-*) mips_fpu=HARD_FLOATING_POINT ;;
|
||||
# end-sanitize-sky
|
||||
mips64*-*-*) mips_fpu=HARD_FLOATING_POINT ;;
|
||||
mips16*-*-*) mips_fpu=HARD_FLOATING_POINT ;;
|
||||
mips*-*-*) mips_fpu=HARD_FLOATING_POINT ;;
|
||||
*) mips_fpu=HARD_FLOATING_POINT ;;
|
||||
esac
|
||||
SIM_AC_OPTION_FLOAT($mips_fpu)
|
||||
|
||||
|
||||
#
|
||||
# Select the IGEN architecture
|
||||
#
|
||||
sim_use_gen=NO
|
||||
sim_igen_machine="-M mipsIV"
|
||||
sim_m16_machine="-M mips16"
|
||||
sim_igen_filter="32,64,f"
|
||||
sim_m16_filter="16"
|
||||
|
||||
case "${target}" in
|
||||
# start-sanitize-tx19
|
||||
mipstx19*-*-*) sim_default_gen=M16
|
||||
sim_igen_machine="-M tx19"
|
||||
sim_m16_machine="-M tx19"
|
||||
sim_igen_filter="32"
|
||||
sim_m16_filter="16"
|
||||
;;
|
||||
# end-sanitize-tx19
|
||||
# start-sanitize-r5900
|
||||
mips64r59*-*-*) sim_default_gen=IGEN
|
||||
sim_igen_machine="-M r5900"
|
||||
;;
|
||||
# end-sanitize-r5900
|
||||
# start-sanitize-sky
|
||||
txvu-*-*) sim_default_gen=IGEN
|
||||
sim_igen_machine="-M r5900"
|
||||
;;
|
||||
# end-sanitize-sky
|
||||
# start-sanitize-vr5400
|
||||
mips64vr54*-*-*) sim_default_gen=IGEN
|
||||
sim_use_gen=IGEN
|
||||
sim_igen_machine="-M vr5000,vr5400 -G gen-multi-sim=vr5400"
|
||||
;;
|
||||
# end-sanitize-vr5400
|
||||
mips64vr5*-*-*) sim_default_gen=IGEN
|
||||
sim_use_gen=IGEN
|
||||
sim_igen_machine="-M vr5000"
|
||||
# start-sanitize-vr5400
|
||||
sim_igen_machine="-M vr5000,vr5400 -G gen-multi-sim=vr5000"
|
||||
# end-sanitize-vr5400
|
||||
;;
|
||||
mips16*-*-*) sim_default_gen=M16
|
||||
;;
|
||||
mips32*-*-*) sim_default_gen=IGEN
|
||||
sim_igen_filter="32,f"
|
||||
;;
|
||||
*) sim_default_gen=IGEN
|
||||
;;
|
||||
esac
|
||||
sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine}"
|
||||
sim_m16_flags=" -F ${sim_m16_filter} ${sim_m16_machine}"
|
||||
AC_SUBST(sim_igen_flags)
|
||||
AC_SUBST(sim_m16_flags)
|
||||
|
||||
#
|
||||
# Enable igen
|
||||
#
|
||||
AC_ARG_ENABLE(sim-igen,
|
||||
[ --enable-sim-igen=opts Enable IGEN simulator],
|
||||
[case "${enableval}" in
|
||||
yes) sim_gen="${sim_default_gen}";;
|
||||
no) sim_gen=NO;;
|
||||
16) sim_gen=M16;;
|
||||
*) AC_MSG_ERROR("Unknown value $enableval passed to --enable-sim-stdio"); sim_gen="";;
|
||||
esac
|
||||
if test x"$silent" != x"yes" && test x"$sim_gen" != x""; then
|
||||
echo "Setting sim_igen = $sim_gen" 6>&1
|
||||
fi],[sim_gen="${sim_use_gen}"])dnl
|
||||
AC_SUBST(sim_gen)
|
||||
|
||||
|
||||
|
||||
AC_CHECK_HEADERS(string.h strings.h stdlib.h stdlib.h)
|
||||
AC_CHECK_LIB(m, fabs)
|
||||
AC_CHECK_FUNCS(aint anint sqrt)
|
||||
|
||||
SIM_AC_OUTPUT
|
||||
@ -1,59 +0,0 @@
|
||||
/* Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
|
||||
Copyright (C) 1998, Cygnus Solutions
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
*/
|
||||
|
||||
#include "sim-main.h"
|
||||
#include "device.h"
|
||||
|
||||
void
|
||||
device_error (device *me, char* message)
|
||||
{
|
||||
fprintf(stderr, "device_error: %s: %s", me->name, message);
|
||||
}
|
||||
|
||||
int
|
||||
device_io_read_buffer(device *me,
|
||||
void *dest,
|
||||
int space,
|
||||
address_word addr,
|
||||
unsigned nr_bytes,
|
||||
sim_cpu *processor,
|
||||
sim_cia cia)
|
||||
{
|
||||
if (me->io_read_buffer_callback == NULL)
|
||||
device_error(me, "no io_read_buffer_callback method");
|
||||
return me->io_read_buffer_callback(me, dest, space,
|
||||
addr, nr_bytes,
|
||||
processor, cia);
|
||||
}
|
||||
|
||||
int
|
||||
device_io_write_buffer(device *me,
|
||||
const void *source,
|
||||
int space,
|
||||
address_word addr,
|
||||
unsigned nr_bytes,
|
||||
sim_cpu *processor,
|
||||
sim_cia cia)
|
||||
{
|
||||
if (me->io_write_buffer_callback == NULL)
|
||||
device_error(me, "no io_write_buffer_callback method");
|
||||
return me->io_write_buffer_callback(me, source, space,
|
||||
addr, nr_bytes,
|
||||
processor, cia);
|
||||
}
|
||||
@ -1,24 +0,0 @@
|
||||
/* Copyright (C) 1998, Cygnus Solutions
|
||||
|
||||
*/
|
||||
|
||||
#ifndef DEVICE_H_
|
||||
#define DEVICE_H_
|
||||
|
||||
#include "sim-main.h"
|
||||
|
||||
typedef int io_read_buffer_callback_type (device *, void *, int,
|
||||
address_word, unsigned ,
|
||||
sim_cpu *, sim_cia);
|
||||
|
||||
typedef int io_write_buffer_callback_type (device *, const void *, int,
|
||||
address_word, unsigned ,
|
||||
sim_cpu *, sim_cia);
|
||||
|
||||
struct _device {
|
||||
char *name;
|
||||
io_read_buffer_callback_type *io_read_buffer_callback;
|
||||
io_write_buffer_callback_type *io_write_buffer_callback;
|
||||
};
|
||||
|
||||
#endif
|
||||
@ -1,70 +0,0 @@
|
||||
/* Copyright (C) 1998, Cygnus Solutions
|
||||
|
||||
*/
|
||||
|
||||
#include "sim-main.h"
|
||||
|
||||
#include "device.h"
|
||||
#include "dma.h"
|
||||
|
||||
int
|
||||
dma_io_read_buffer(device *me,
|
||||
void *dest,
|
||||
int space,
|
||||
address_word addr,
|
||||
unsigned nr_bytes,
|
||||
sim_cpu *processor,
|
||||
sim_cia cia)
|
||||
{
|
||||
printf("%s: Read!\n", me->name);
|
||||
return nr_bytes;
|
||||
}
|
||||
|
||||
static sim_event_handler do_the_dma_thing_handler;
|
||||
|
||||
int
|
||||
dma_io_write_buffer(device *me,
|
||||
const void *source,
|
||||
int space,
|
||||
address_word addr,
|
||||
unsigned nr_bytes,
|
||||
sim_cpu *processor,
|
||||
sim_cia cia)
|
||||
{
|
||||
printf("%s: Write!\n", me->name);
|
||||
|
||||
/* Do an event before the next instruction! */
|
||||
sim_events_schedule (CPU_STATE(processor),
|
||||
0 /*time*/,
|
||||
do_the_dma_thing_handler,
|
||||
CPU_STATE(processor) /*data*/);
|
||||
return nr_bytes;
|
||||
}
|
||||
|
||||
device dma_device =
|
||||
{
|
||||
"Dma Controller",
|
||||
&dma_io_read_buffer,
|
||||
&dma_io_write_buffer
|
||||
};
|
||||
|
||||
void
|
||||
dma_attach(SIM_DESC sd)
|
||||
{
|
||||
sim_core_attach (sd,
|
||||
NULL,
|
||||
0 /*level*/,
|
||||
access_read_write,
|
||||
0 /*space ???*/,
|
||||
DMA_REGISTER_WINDOW_START,
|
||||
DMA_REGISTER_WINDOW_SIZE /*nr_bytes*/,
|
||||
0 /*modulo*/,
|
||||
&dma_device,
|
||||
NULL /*buffer*/);
|
||||
}
|
||||
|
||||
static void
|
||||
do_the_dma_thing_handler(SIM_DESC sd, void *data)
|
||||
{
|
||||
printf("Dma Event!!!\n");
|
||||
}
|
||||
@ -1,54 +0,0 @@
|
||||
/* Copyright (C) 1998, Cygnus Solutions
|
||||
|
||||
*/
|
||||
|
||||
#ifndef DMA_H_
|
||||
#define DMA_H_
|
||||
|
||||
#include "sim-main.h"
|
||||
|
||||
void dma_attach(SIM_DESC sd);
|
||||
|
||||
#define DMA_REGISTER_WINDOW_START 0x10001000
|
||||
|
||||
#define DMA_D0_CHCR_ADDR 0x10001000
|
||||
#define DMA_D0_MADR_ADDR 0x10001010
|
||||
#define DMA_D0_QWC_ADDR 0x10001020
|
||||
#define DMA_D0_TADR_ADDR 0x10001030
|
||||
#define DMA_D0_ASR0_ADDR 0x10001040
|
||||
#define DMA_D0_ASR1_ADDR 0x10001050
|
||||
|
||||
#define DMA_D1_CHCR_ADDR 0x10001100
|
||||
#define DMA_D1_MADR_ADDR 0x10001110
|
||||
#define DMA_D1_QWC_ADDR 0x10001120
|
||||
#define DMA_D1_TADR_ADDR 0x10001130
|
||||
#define DMA_D1_ASR0_ADDR 0x10001140
|
||||
#define DMA_D1_ASR1_ADDR 0x10001150
|
||||
|
||||
#define DMA_D2_CHCR_ADDR 0x10001200
|
||||
#define DMA_D2_MADR_ADDR 0x10001210
|
||||
#define DMA_D2_QWC_ADDR 0x10001220
|
||||
#define DMA_D2_TADR_ADDR 0x10001230
|
||||
#define DMA_D2_ASR0_ADDR 0x10001240
|
||||
#define DMA_D2_ASR1_ADDR 0x10001250
|
||||
|
||||
#define DMA_D_CTRL 0x10001c00
|
||||
#define DMA_D_STAT 0x10001c10
|
||||
#define DMA_D_PCR 0x10001c20
|
||||
#define DMA_D_SQWC 0x10001c30
|
||||
#define DMA_D_RBSR 0x10001c40
|
||||
#define DMA_D_RBOR 0x10001c50
|
||||
#define DMA_D_STADR 0x10001c60
|
||||
|
||||
#define DMA_REGISTER_WINDOW_END 0x10001c70
|
||||
#define DMA_REGISTER_WINDOW_SIZE (DMA_REGISTER_WINDOW_END - DMA_REGISTER_WINDOW_START)
|
||||
|
||||
/* virtual addresses for source-addr tracking */
|
||||
#define DMA_CHANNEL0_SRCADDR 0x20000000
|
||||
#define DMA_CHANNEL1_SRCADDR 0x20000004
|
||||
#define DMA_CHANNEL2_SRCADDR 0x20000008
|
||||
#define DMA_CHANNEL0_PKTFLAG 0x20000010
|
||||
#define DMA_CHANNEL1_PKTFLAG 0x20000014
|
||||
#define DMA_CHANNEL2_PKTFLAG 0x20000018
|
||||
|
||||
#endif
|
||||
@ -1,125 +0,0 @@
|
||||
/* Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
|
||||
Copyright (C) 1998, Cygnus Solutions
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _ENGINE_C_
|
||||
#define _ENGINE_C_
|
||||
|
||||
#include "sim-inline.c"
|
||||
|
||||
#include "sim-main.h"
|
||||
#include "itable.h"
|
||||
#include "idecode.h"
|
||||
#include "semantics.h"
|
||||
#include "icache.h"
|
||||
#include "engine.h"
|
||||
#include "support.h"
|
||||
|
||||
#include "sim-assert.h"
|
||||
|
||||
#include "hardware.h"
|
||||
|
||||
enum {
|
||||
/* greater or equal to zero => table */
|
||||
function_entry = -1,
|
||||
boolean_entry = -2,
|
||||
};
|
||||
|
||||
typedef struct _idecode_table_entry {
|
||||
int shift;
|
||||
unsigned32 mask;
|
||||
unsigned32 value;
|
||||
void *function_or_table;
|
||||
} idecode_table_entry;
|
||||
|
||||
|
||||
INLINE_ENGINE\
|
||||
(void) engine_run
|
||||
(SIM_DESC sd,
|
||||
int next_cpu_nr,
|
||||
int siggnal)
|
||||
{
|
||||
sim_cpu *processor = NULL;
|
||||
instruction_address cia;
|
||||
int current_cpu = next_cpu_nr;
|
||||
instruction_word instruction_0;
|
||||
|
||||
/* Hard coded main loop. Not pretty, but should work. */
|
||||
ASSERT(current_cpu >= 0 && current_cpu < NUMBER_CPUS);
|
||||
|
||||
cia = CPU_CIA (0); /* Only the 5900 uses this. */
|
||||
processor = STATE_CPU (sd, 0); /* Only the 5900 uses this. */
|
||||
|
||||
switch(current_cpu)
|
||||
{
|
||||
case 0:
|
||||
goto cpu_0;
|
||||
case 1:
|
||||
goto cpu_1;
|
||||
case 2:
|
||||
goto cpu_2;
|
||||
case 3:
|
||||
goto cpu_3;
|
||||
case 4:
|
||||
goto cpu_4;
|
||||
}
|
||||
|
||||
while (1)
|
||||
{
|
||||
|
||||
cpu_0:
|
||||
|
||||
cia = CPU_CIA (processor);
|
||||
instruction_0 = IMEM (cia);
|
||||
|
||||
#if defined (ENGINE_ISSUE_PREFIX_HOOK)
|
||||
ENGINE_ISSUE_PREFIX_HOOK();
|
||||
#endif
|
||||
|
||||
cia = idecode_issue(sd, instruction_0, cia);
|
||||
|
||||
#if defined (ENGINE_ISSUE_POSTFIX_HOOK)
|
||||
ENGINE_ISSUE_POSTFIX_HOOK();
|
||||
#endif
|
||||
|
||||
/* Update the instruction address */
|
||||
CPU_CIA (processor) = cia;
|
||||
|
||||
cpu_1:
|
||||
pke0_issue();
|
||||
|
||||
cpu_2:
|
||||
pke1_issue();
|
||||
|
||||
cpu_3:
|
||||
vu0_issue();
|
||||
|
||||
cpu_4:
|
||||
vu1_issue();
|
||||
|
||||
events:
|
||||
|
||||
/* process any events */
|
||||
if (sim_events_tick (sd))
|
||||
{
|
||||
sim_events_process (sd);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* _ENGINE_C_*/
|
||||
4846
sim/txvu/gencode.c
4846
sim/txvu/gencode.c
File diff suppressed because it is too large
Load Diff
@ -1,55 +0,0 @@
|
||||
/* Copyright (C) 1998, Cygnus Solutions
|
||||
|
||||
*/
|
||||
|
||||
#include "sim-main.h"
|
||||
|
||||
#include "device.h"
|
||||
#include "gpuif.h"
|
||||
|
||||
int
|
||||
gpuif_io_read_buffer(device *me,
|
||||
void *dest,
|
||||
int space,
|
||||
address_word addr,
|
||||
unsigned nr_bytes,
|
||||
sim_cpu *processor,
|
||||
sim_cia cia)
|
||||
{
|
||||
printf("%s: Read!\n", me->name);
|
||||
return nr_bytes;
|
||||
}
|
||||
|
||||
int
|
||||
gpuif_io_write_buffer(device *me,
|
||||
const void *source,
|
||||
int space,
|
||||
address_word addr,
|
||||
unsigned nr_bytes,
|
||||
sim_cpu *processor,
|
||||
sim_cia cia)
|
||||
{
|
||||
printf("%s: Write!\n", me->name);
|
||||
return nr_bytes;
|
||||
}
|
||||
|
||||
device gpuif_device =
|
||||
{
|
||||
"Gpuif deivce",
|
||||
&gpuif_io_read_buffer,
|
||||
&gpuif_io_write_buffer
|
||||
};
|
||||
|
||||
void
|
||||
gpuif_attach(SIM_DESC sd)
|
||||
{
|
||||
sim_core_attach (sd, NULL,
|
||||
0 /*level*/,
|
||||
access_read_write,
|
||||
0 /*space ???*/,
|
||||
GPUIF_REGISTER_WINDOW_START,
|
||||
GPUIF_REGISTER_WINDOW_SIZE /*nr_bytes*/,
|
||||
0 /*modulo*/,
|
||||
&gpuif_device,
|
||||
NULL /*buffer*/);
|
||||
}
|
||||
@ -1,19 +0,0 @@
|
||||
/* Copyright (C) 1998, Cygnus Solutions
|
||||
|
||||
*/
|
||||
|
||||
#ifndef GPUIF_H_
|
||||
#define GPUIF_H_
|
||||
|
||||
#include "sim-main.h"
|
||||
|
||||
void gpuif_attach(SIM_DESC sd);
|
||||
|
||||
#define GPUIF_REGISTER_WINDOW_START 0x10000700
|
||||
|
||||
#define GPUIF_CTRL_ADDR 0x10000700
|
||||
|
||||
#define GPUIF_REGISTER_WINDOW_END 0x10000790
|
||||
#define GPUIF_REGISTER_WINDOW_SIZE (GPUIF_REGISTER_WINDOW_END - GPUIF_REGISTER_WINDOW_START)
|
||||
|
||||
#endif
|
||||
@ -1,23 +0,0 @@
|
||||
/* Copyright (C) 1998, Cygnus Solutions
|
||||
|
||||
*/
|
||||
|
||||
#include "gpuif.h"
|
||||
#include "dma.h"
|
||||
#include "pke.h"
|
||||
#include "vu0.h"
|
||||
#include "vu1.h"
|
||||
|
||||
#include "hardware.h"
|
||||
|
||||
void
|
||||
register_devices(SIM_DESC sd)
|
||||
{
|
||||
/* Attach a bunch of devices... */
|
||||
gpuif_attach(sd);
|
||||
dma_attach(sd);
|
||||
pke0_attach(sd);
|
||||
vu0_attach(sd);
|
||||
vu1_init(sd);
|
||||
pke1_attach(sd);
|
||||
}
|
||||
@ -1,14 +0,0 @@
|
||||
/* Copyright (C) 1998, Cygnus Solutions
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _HARDWARE_H_
|
||||
#define _HARDWARE_H_
|
||||
|
||||
#include "sim-main.h"
|
||||
|
||||
void create_devices(SIM_DESC sd);
|
||||
|
||||
#define NUMBER_CPUS 5
|
||||
|
||||
#endif
|
||||
3456
sim/txvu/interp.c
3456
sim/txvu/interp.c
File diff suppressed because it is too large
Load Diff
5877
sim/txvu/libvpe.c
5877
sim/txvu/libvpe.c
File diff suppressed because it is too large
Load Diff
@ -1,35 +0,0 @@
|
||||
/****************************************************************************/
|
||||
/* */
|
||||
/* Sony Computer Entertainment CONFIDENTIAL */
|
||||
/* (C) 1997 Sony Computer Entertainment Inc. All Rights Reserved */
|
||||
/* */
|
||||
/* VPE1 simulator (part of VU1) global variables */
|
||||
/* */
|
||||
/****************************************************************************/
|
||||
|
||||
#ifndef LIBVPE_H_
|
||||
#define LIBVPE_H_
|
||||
|
||||
extern unsigned long _ITOP;
|
||||
extern unsigned long _TOP;
|
||||
extern unsigned long _vpepc;
|
||||
extern int _is_dbg;
|
||||
extern int _is_verb;
|
||||
extern int _is_dump;
|
||||
extern int _pgpuif;
|
||||
extern FILE *_fp_gpu;
|
||||
|
||||
extern int _GIF_SIM_OFF;
|
||||
extern int _GIF_BUSY;
|
||||
extern int _GIF_VUCALL;
|
||||
extern int _GIF_VUADDR;
|
||||
|
||||
#include "vu.h"
|
||||
|
||||
void initvpe(VectorUnitState *state);
|
||||
|
||||
void vpecallms_init(VectorUnitState *state);
|
||||
void vpecallms_cycle(VectorUnitState* state);
|
||||
|
||||
|
||||
#endif
|
||||
2692
sim/txvu/m16.igen
2692
sim/txvu/m16.igen
File diff suppressed because it is too large
Load Diff
1298
sim/txvu/mdmx.igen
1298
sim/txvu/mdmx.igen
File diff suppressed because it is too large
Load Diff
@ -1,16 +0,0 @@
|
||||
# most instructions
|
||||
# ------ options ------ : Fst : Lst : ff : fl : fe : word : --- fmt --- : model ...
|
||||
# { : mask : value : word }
|
||||
|
||||
# Top level - create a very big switch statement.
|
||||
|
||||
padded-switch,combine : 31 : 26 : : : : : :
|
||||
|
||||
switch,combine : 5 : 0 : : : : : :
|
||||
|
||||
switch,combine : 20 : 16 : : : : : :
|
||||
|
||||
switch,combine : 25 : 21 : : : : : :
|
||||
|
||||
switch,combine : 10 : 6 : : : : : :
|
||||
|
||||
5209
sim/txvu/mips.igen
5209
sim/txvu/mips.igen
File diff suppressed because it is too large
Load Diff
306
sim/txvu/pke.c
306
sim/txvu/pke.c
@ -1,306 +0,0 @@
|
||||
/* Copyright (C) 1998, Cygnus Solutions */
|
||||
|
||||
#include "pke.h"
|
||||
#include <stdlib.h>
|
||||
|
||||
|
||||
/* Imported functions */
|
||||
|
||||
void device_error (device *me, char* message); /* device.c */
|
||||
|
||||
|
||||
/* Internal function declarations */
|
||||
|
||||
static int pke_io_read_buffer(device*, void*, int, address_word,
|
||||
unsigned, sim_cpu*, sim_cia);
|
||||
static int pke_io_write_buffer(device*, const void*, int, address_word,
|
||||
unsigned, sim_cpu*, sim_cia);
|
||||
static void pke_issue(struct pke_device*);
|
||||
|
||||
|
||||
/* Static data */
|
||||
|
||||
struct pke_device pke0_device =
|
||||
{
|
||||
{ "pke0", &pke_io_read_buffer, &pke_io_write_buffer }, /* device */
|
||||
0, 0, /* ID, flags */
|
||||
PKE0_REGISTER_WINDOW_START, PKE0_FIFO_START, /* memory-mapping addresses */
|
||||
{}, /* regs */
|
||||
NULL, 0, 0, NULL, /* FIFO */
|
||||
0 /* pc */
|
||||
};
|
||||
|
||||
|
||||
struct pke_device pke1_device =
|
||||
{
|
||||
{ "pke1", &pke_io_read_buffer, &pke_io_write_buffer }, /* device */
|
||||
1, 0, /* ID, flags */
|
||||
PKE1_REGISTER_WINDOW_START, PKE1_FIFO_START, /* memory-mapping addresses */
|
||||
{}, /* regs */
|
||||
NULL, 0, 0, NULL, /* FIFO */
|
||||
0 /* pc */
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* External functions */
|
||||
|
||||
|
||||
/* Attach PKE0 addresses to main memory */
|
||||
|
||||
void
|
||||
pke0_attach(SIM_DESC sd)
|
||||
{
|
||||
sim_core_attach (sd,
|
||||
NULL,
|
||||
0 /*level*/,
|
||||
access_read_write,
|
||||
0 /*space ???*/,
|
||||
pke0_device.register_memory_addr,
|
||||
PKE_REGISTER_WINDOW_SIZE /*nr_bytes*/,
|
||||
0 /*modulo*/,
|
||||
(device*) &pke0_device,
|
||||
NULL /*buffer*/);
|
||||
|
||||
sim_core_attach (sd,
|
||||
NULL,
|
||||
0 /*level*/,
|
||||
access_read_write,
|
||||
0 /*space ???*/,
|
||||
pke0_device.fifo_memory_addr,
|
||||
sizeof(quadword) /*nr_bytes*/,
|
||||
0 /*modulo*/,
|
||||
(device*) &pke1_device,
|
||||
NULL /*buffer*/);
|
||||
}
|
||||
|
||||
|
||||
/* Attach PKE1 addresses to main memory */
|
||||
|
||||
void
|
||||
pke1_attach(SIM_DESC sd)
|
||||
{
|
||||
sim_core_attach (sd,
|
||||
NULL,
|
||||
0 /*level*/,
|
||||
access_read_write,
|
||||
0 /*space ???*/,
|
||||
pke1_device.register_memory_addr,
|
||||
PKE_REGISTER_WINDOW_SIZE /*nr_bytes*/,
|
||||
0 /*modulo*/,
|
||||
(device*) &pke1_device,
|
||||
NULL /*buffer*/);
|
||||
|
||||
sim_core_attach (sd,
|
||||
NULL,
|
||||
0 /*level*/,
|
||||
access_read_write,
|
||||
0 /*space ???*/,
|
||||
pke1_device.fifo_memory_addr,
|
||||
sizeof(quadword) /*nr_bytes*/,
|
||||
0 /*modulo*/,
|
||||
(device*) &pke1_device,
|
||||
NULL /*buffer*/);
|
||||
}
|
||||
|
||||
|
||||
/* Issue a PKE0 instruction if possible */
|
||||
|
||||
void
|
||||
pke0_issue()
|
||||
{
|
||||
pke_issue(& pke0_device);
|
||||
}
|
||||
|
||||
|
||||
/* Issue a PKE1 instruction if possible */
|
||||
|
||||
void
|
||||
pke1_issue()
|
||||
{
|
||||
pke_issue(& pke0_device);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Internal functions */
|
||||
|
||||
|
||||
/* Handle a PKE read; return no. of bytes read */
|
||||
|
||||
int
|
||||
pke_io_read_buffer(device *me_,
|
||||
void *dest,
|
||||
int space,
|
||||
address_word addr,
|
||||
unsigned nr_bytes,
|
||||
sim_cpu *processor,
|
||||
sim_cia cia)
|
||||
{
|
||||
/* downcast to gather embedding pke_device struct */
|
||||
struct pke_device* me = (struct pke_device*) me_;
|
||||
|
||||
/* enforce that an access does not span more than one quadword */
|
||||
address_word low = ADDR_TRUNC_QW(addr);
|
||||
address_word high = ADDR_TRUNC_QW(addr + nr_bytes - 1);
|
||||
if(low != high)
|
||||
return 0;
|
||||
|
||||
/* classify address & handle */
|
||||
if(addr >= me->register_memory_addr &&
|
||||
addr < me->register_memory_addr + PKE_REGISTER_WINDOW_SIZE)
|
||||
{
|
||||
/* register bank */
|
||||
int reg_num = ADDR_TRUNC_QW(addr - me->register_memory_addr) >> 4;
|
||||
int readable = 1;
|
||||
|
||||
/* ensure readibility of register: all okay except PKE1-only ones read on PKE0 */
|
||||
switch(reg_num)
|
||||
{
|
||||
case PKE_REG_BASE:
|
||||
case PKE_REG_OFST:
|
||||
case PKE_REG_TOPS:
|
||||
case PKE_REG_TOP:
|
||||
case PKE_REG_DBF:
|
||||
if(me->pke_number == 0) /* PKE0 cannot access these registers */
|
||||
readable = 0;
|
||||
}
|
||||
|
||||
/* perform read & return */
|
||||
if(readable)
|
||||
{
|
||||
/* find byte-offset inside register bank */
|
||||
int reg_byte = ADDR_OFFSET_QW(addr);
|
||||
void* src = ((unsigned_1*) (& me->regs[reg_num])) + reg_byte;
|
||||
/* copy the bits */
|
||||
memcpy(dest, src, nr_bytes);
|
||||
/* okay */
|
||||
return nr_bytes;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* error */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* NOTREACHED */
|
||||
}
|
||||
else if(addr >= me->fifo_memory_addr &&
|
||||
addr < me->fifo_memory_addr + sizeof(quadword))
|
||||
{
|
||||
/* FIFO */
|
||||
|
||||
/* XXX: FIFO is not readable. */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* NOTREACHED */
|
||||
}
|
||||
|
||||
|
||||
/* Handle a PKE read; return no. of bytes written */
|
||||
|
||||
int
|
||||
pke_io_write_buffer(device *me_,
|
||||
const void *src,
|
||||
int space,
|
||||
address_word addr,
|
||||
unsigned nr_bytes,
|
||||
sim_cpu *processor,
|
||||
sim_cia cia)
|
||||
{
|
||||
/* downcast to gather embedding pke_device struct */
|
||||
struct pke_device* me = (struct pke_device*) me_;
|
||||
|
||||
/* enforce that an access does not span more than one quadword */
|
||||
address_word low = ADDR_TRUNC_QW(addr);
|
||||
address_word high = ADDR_TRUNC_QW(addr + nr_bytes - 1);
|
||||
if(low != high)
|
||||
return 0;
|
||||
|
||||
/* classify address & handle */
|
||||
if(addr >= me->register_memory_addr &&
|
||||
addr < me->register_memory_addr + PKE_REGISTER_WINDOW_SIZE)
|
||||
{
|
||||
/* register bank */
|
||||
int reg_num = ADDR_TRUNC_QW(addr - me->register_memory_addr) >> 4;
|
||||
int writeable = 1;
|
||||
|
||||
/* ensure readibility of register: all okay except PKE1-only ones read on PKE0 */
|
||||
switch(reg_num)
|
||||
{
|
||||
case PKE_REG_BASE:
|
||||
case PKE_REG_OFST:
|
||||
case PKE_REG_TOPS:
|
||||
case PKE_REG_TOP:
|
||||
case PKE_REG_DBF:
|
||||
if(me->pke_number == 0) /* PKE0 cannot access these registers */
|
||||
writeable = 0;
|
||||
}
|
||||
|
||||
/* perform write & return */
|
||||
if(writeable)
|
||||
{
|
||||
/* find byte-offset inside register bank */
|
||||
int reg_byte = ADDR_OFFSET_QW(addr);
|
||||
void* dest = ((unsigned_1*) (& me->regs[reg_num])) + reg_byte;
|
||||
/* copy the bits */
|
||||
memcpy(dest, src, nr_bytes);
|
||||
return nr_bytes;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* error */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* NOTREACHED */
|
||||
}
|
||||
else if(addr >= me->fifo_memory_addr &&
|
||||
addr < me->fifo_memory_addr + sizeof(quadword))
|
||||
{
|
||||
/* FIFO */
|
||||
|
||||
/* assert transfer size == 128 bits */
|
||||
if(nr_bytes != sizeof(quadword))
|
||||
return 0;
|
||||
|
||||
/* ensure FIFO has enough elements */
|
||||
if(me->fifo_num_elements == me->fifo_buffer_size)
|
||||
{
|
||||
/* time to grow */
|
||||
int new_fifo_buffer_size = me->fifo_buffer_size + 20;
|
||||
void* ptr = realloc((void*) me->fifo, new_fifo_buffer_size*sizeof(quadword));
|
||||
|
||||
if(ptr == NULL)
|
||||
{
|
||||
/* oops, cannot enlarge FIFO any more */
|
||||
device_error(me_, "Cannot enlarge FIFO buffer\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
me->fifo_buffer_size = new_fifo_buffer_size;
|
||||
}
|
||||
|
||||
/* add new quadword at end of FIFO */
|
||||
memcpy(& me->fifo[++me->fifo_num_elements], src, nr_bytes);
|
||||
|
||||
/* okay */
|
||||
return nr_bytes;
|
||||
}
|
||||
|
||||
/* NOTREACHED */
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Issue & swallow one PKE opcode if possible */
|
||||
|
||||
void
|
||||
pke_issue(struct pke_device* me)
|
||||
{
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
117
sim/txvu/pke.h
117
sim/txvu/pke.h
@ -1,117 +0,0 @@
|
||||
/* Copyright (C) 1998, Cygnus Solutions */
|
||||
|
||||
#ifndef H_PKE_H
|
||||
#define H_PKE_H
|
||||
|
||||
#include "sim-main.h"
|
||||
#include "device.h"
|
||||
|
||||
|
||||
/* External functions */
|
||||
|
||||
void pke0_attach(SIM_DESC sd);
|
||||
void pke0_issue();
|
||||
void pke1_attach(SIM_DESC sd);
|
||||
void pke1_issue();
|
||||
|
||||
|
||||
/* Quadword data type */
|
||||
|
||||
typedef unsigned int quadword[4];
|
||||
|
||||
/* truncate address to quadword */
|
||||
#define ADDR_TRUNC_QW(addr) ((addr) & ~0x0f)
|
||||
/* extract offset in quadword */
|
||||
#define ADDR_OFFSET_QW(addr) ((addr) & 0x0f)
|
||||
|
||||
|
||||
/* SCEI memory mapping information */
|
||||
|
||||
#define PKE0_REGISTER_WINDOW_START 0x10000800
|
||||
#define PKE1_REGISTER_WINDOW_START 0x10000A00
|
||||
#define PKE0_FIFO_START 0x10008000
|
||||
#define PKE1_FIFO_START 0x10008010
|
||||
|
||||
|
||||
/* Quadword indices of PKE registers. Actual registers sit at bottom
|
||||
32 bits of each quadword. */
|
||||
#define PKE_REG_STAT 0x00
|
||||
#define PKE_REG_FBRST 0x01
|
||||
#define PKE_REG_ERR 0x02
|
||||
#define PKE_REG_MARK 0x03
|
||||
#define PKE_REG_CYCLE 0x04
|
||||
#define PKE_REG_MODE 0x05
|
||||
#define PKE_REG_NUM 0x06
|
||||
#define PKE_REG_MASK 0x07
|
||||
#define PKE_REG_CODE 0x08
|
||||
#define PKE_REG_ITOPS 0x09
|
||||
#define PKE_REG_BASE 0x0a /* pke1 only */
|
||||
#define PKE_REG_OFST 0x0b /* pke1 only */
|
||||
#define PKE_REG_TOPS 0x0c /* pke1 only */
|
||||
#define PKE_REG_ITOP 0x0d
|
||||
#define PKE_REG_TOP 0x0e /* pke1 only */
|
||||
#define PKE_REG_DBF 0x0f /* pke1 only */
|
||||
#define PKE_REG_R0 0x10
|
||||
#define PKE_REG_R1 0x11
|
||||
#define PKE_REG_R2 0x12
|
||||
#define PKE_REG_R3 0x13
|
||||
#define PKE_REG_C0 0x14
|
||||
#define PKE_REG_C1 0x15
|
||||
#define PKE_REG_C2 0x16
|
||||
#define PKE_REG_C3 0x17
|
||||
/* one plus last index */
|
||||
#define PKE_NUM_REGS 0x18
|
||||
|
||||
#define PKE_REGISTER_WINDOW_SIZE (sizeof(quadword) * PKE_NUM_REGS)
|
||||
|
||||
/* virtual addresses for source-addr tracking */
|
||||
#define PKE0_SRCADDR 0x20000020
|
||||
#define PKE1_SRCADDR 0x20000024
|
||||
|
||||
|
||||
/* One row in the FIFO */
|
||||
struct fifo_quadword
|
||||
{
|
||||
/* 128 bits of data */
|
||||
quadword data;
|
||||
/* source main memory address (or 0: unknown) */
|
||||
address_word source_address;
|
||||
};
|
||||
|
||||
|
||||
/* PKE internal state: FIFOs, registers, handle to VU friend */
|
||||
struct pke_device
|
||||
{
|
||||
/* common device info */
|
||||
device dev;
|
||||
|
||||
/* identity: 0=PKE0, 1=PKE1 */
|
||||
int pke_number;
|
||||
int flags;
|
||||
|
||||
address_word register_memory_addr;
|
||||
address_word fifo_memory_addr;
|
||||
|
||||
/* quadword registers */
|
||||
quadword regs[PKE_NUM_REGS];
|
||||
|
||||
/* FIFO */
|
||||
struct fifo_quadword* fifo;
|
||||
int fifo_num_elements; /* no. of quadwords occupied in FIFO */
|
||||
int fifo_buffer_size; /* no. of quadwords of space in FIFO */
|
||||
FILE* fifo_trace_file; /* or 0 for no trace */
|
||||
|
||||
/* index into FIFO of current instruction */
|
||||
int program_counter;
|
||||
|
||||
};
|
||||
|
||||
|
||||
/* Flags for PKE.flags */
|
||||
|
||||
#define PKE_FLAG_NONE 0
|
||||
/* none at present */
|
||||
|
||||
|
||||
|
||||
#endif /* H_PKE_H */
|
||||
2463
sim/txvu/r5900.igen
2463
sim/txvu/r5900.igen
File diff suppressed because it is too large
Load Diff
@ -1,732 +0,0 @@
|
||||
/* MIPS Simulator definition.
|
||||
Copyright (C) 1997 Free Software Foundation, Inc.
|
||||
Contributed by Cygnus Support.
|
||||
|
||||
This file is part of GDB, the GNU debugger.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
#ifndef SIM_MAIN_H
|
||||
#define SIM_MAIN_H
|
||||
|
||||
/* This simulator doesn't cache the Current Instruction Address */
|
||||
/* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
|
||||
/* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
|
||||
|
||||
#define SIM_HAVE_BIENDIAN
|
||||
|
||||
|
||||
/* hobble some common features for moment */
|
||||
#define WITH_WATCHPOINTS 1
|
||||
#define WITH_MODULO_MEMORY 1
|
||||
|
||||
/* For device support. FIXME: revisit. */
|
||||
#define WITH_DEVICES 1
|
||||
|
||||
#include "sim-basics.h"
|
||||
|
||||
typedef address_word sim_cia;
|
||||
|
||||
#if (WITH_IGEN)
|
||||
/* Get the number of instructions. FIXME: must be a more elegant way
|
||||
of doing this. */
|
||||
#include "itable.h"
|
||||
#define MAX_INSNS (nr_itable_entries)
|
||||
#define INSN_NAME(i) itable[(i)].name
|
||||
#endif
|
||||
|
||||
#include "sim-base.h"
|
||||
|
||||
|
||||
/* Depreciated macros and types for manipulating 64bit values. Use
|
||||
../common/sim-bits.h and ../common/sim-endian.h macros instead. */
|
||||
|
||||
typedef signed64 word64;
|
||||
typedef unsigned64 uword64;
|
||||
|
||||
#define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
|
||||
#define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
|
||||
#define SET64LO(t) (((uword64)(t))&0xFFFFFFFF)
|
||||
#define SET64HI(t) (((uword64)(t))<<32)
|
||||
#define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
|
||||
#define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
|
||||
|
||||
/* Sign-extend the given value (e) as a value (b) bits long. We cannot
|
||||
assume the HI32bits of the operand are zero, so we must perform a
|
||||
mask to ensure we can use the simple subtraction to sign-extend. */
|
||||
#define SIGNEXTEND(e,b) \
|
||||
((unsigned_word) \
|
||||
(((e) & ((uword64) 1 << ((b) - 1))) \
|
||||
? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
|
||||
: ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
|
||||
|
||||
/* Check if a value will fit within a halfword: */
|
||||
#define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
|
||||
|
||||
|
||||
|
||||
/* Floating-point operations: */
|
||||
|
||||
#include "sim-fpu.h"
|
||||
|
||||
/* FPU registers must be one of the following types. All other values
|
||||
are reserved (and undefined). */
|
||||
typedef enum {
|
||||
fmt_single = 0,
|
||||
fmt_double = 1,
|
||||
fmt_word = 4,
|
||||
fmt_long = 5,
|
||||
/* The following are well outside the normal acceptable format
|
||||
range, and are used in the register status vector. */
|
||||
fmt_unknown = 0x10000000,
|
||||
fmt_uninterpreted = 0x20000000,
|
||||
fmt_uninterpreted_32 = 0x40000000,
|
||||
fmt_uninterpreted_64 = 0x80000000,
|
||||
} FP_formats;
|
||||
|
||||
unsigned64 value_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats));
|
||||
#define ValueFPR(FPR,FMT) value_fpr (sd, cia, (FPR), (FMT))
|
||||
|
||||
void store_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
|
||||
#define StoreFPR(FPR,FMT,VALUE) store_fpr (sd, cia, (FPR), (FMT), (VALUE))
|
||||
|
||||
int NaN PARAMS ((unsigned64 op, FP_formats fmt));
|
||||
int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
|
||||
int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
|
||||
int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
|
||||
unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
|
||||
unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
|
||||
unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
|
||||
unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
|
||||
unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
|
||||
unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
|
||||
unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
|
||||
unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
|
||||
unsigned64 convert PARAMS ((SIM_DESC sd, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
|
||||
#define Convert(rm,op,from,to) convert(sd,cia,rm,op,from,to)
|
||||
|
||||
/* Macro to update FPSR condition-code field. This is complicated by
|
||||
the fact that there is a hole in the index range of the bits within
|
||||
the FCSR register. Also, the number of bits visible depends on the
|
||||
MIPS ISA version being supported. */
|
||||
|
||||
#define SETFCC(cc,v) {\
|
||||
int bit = ((cc == 0) ? 23 : (24 + (cc)));\
|
||||
FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
|
||||
}
|
||||
#define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0)
|
||||
|
||||
/* This should be the COC1 value at the start of the preceding
|
||||
instruction: */
|
||||
#define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
|
||||
|
||||
#if 1
|
||||
#define SizeFGR() (WITH_TARGET_WORD_BITSIZE)
|
||||
#else
|
||||
/* They depend on the CPU being simulated */
|
||||
#define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
|
||||
#endif
|
||||
|
||||
/* Standard FCRS bits: */
|
||||
#define IR (0) /* Inexact Result */
|
||||
#define UF (1) /* UnderFlow */
|
||||
#define OF (2) /* OverFlow */
|
||||
#define DZ (3) /* Division by Zero */
|
||||
#define IO (4) /* Invalid Operation */
|
||||
#define UO (5) /* Unimplemented Operation */
|
||||
|
||||
/* Get masks for individual flags: */
|
||||
#if 1 /* SAFE version */
|
||||
#define FP_FLAGS(b) (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
|
||||
#define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
|
||||
#define FP_CAUSE(b) (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
|
||||
#else
|
||||
#define FP_FLAGS(b) (1 << ((b) + 2))
|
||||
#define FP_ENABLE(b) (1 << ((b) + 7))
|
||||
#define FP_CAUSE(b) (1 << ((b) + 12))
|
||||
#endif
|
||||
|
||||
#define FP_FS (1 << 24) /* MIPS III onwards : Flush to Zero */
|
||||
|
||||
#define FP_MASK_RM (0x3)
|
||||
#define FP_SH_RM (0)
|
||||
#define FP_RM_NEAREST (0) /* Round to nearest (Round) */
|
||||
#define FP_RM_TOZERO (1) /* Round to zero (Trunc) */
|
||||
#define FP_RM_TOPINF (2) /* Round to Plus infinity (Ceil) */
|
||||
#define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */
|
||||
#define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
|
||||
|
||||
|
||||
|
||||
/* Integer ALU operations: */
|
||||
|
||||
#include "sim-alu.h"
|
||||
|
||||
#define ALU32_END(ANS) \
|
||||
if (ALU32_HAD_OVERFLOW) \
|
||||
SignalExceptionIntegerOverflow (); \
|
||||
(ANS) = ALU32_OVERFLOW_RESULT
|
||||
|
||||
|
||||
#define ALU64_END(ANS) \
|
||||
if (ALU64_HAD_OVERFLOW) \
|
||||
SignalExceptionIntegerOverflow (); \
|
||||
(ANS) = ALU64_OVERFLOW_RESULT;
|
||||
|
||||
/* start-sanitize-r5900 */
|
||||
|
||||
#define BYTES_IN_MMI_REGS (sizeof(signed_word) + sizeof(signed_word))
|
||||
#define HALFWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/2)
|
||||
#define WORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/4)
|
||||
#define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
|
||||
|
||||
#define BYTES_IN_MIPS_REGS (sizeof(signed_word))
|
||||
#define HALFWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/2)
|
||||
#define WORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/4)
|
||||
#define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
|
||||
|
||||
/* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
|
||||
T - type of the sub part
|
||||
TC - # of T's in the mips part of the "register"
|
||||
I - index (from 0) of desired sub part
|
||||
A - low part of "register"
|
||||
A1 - high part of register
|
||||
*/
|
||||
#define SUB_REG_FETCH(T,TC,A,A1,I) \
|
||||
(*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
|
||||
+ (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
|
||||
? ((TC) - 1 - (I) % (TC)) \
|
||||
: ((I) % (TC)) \
|
||||
) \
|
||||
) \
|
||||
)
|
||||
|
||||
/*
|
||||
GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
|
||||
where <type> has two letters:
|
||||
1 is S=signed or U=unsigned
|
||||
2 is B=byte H=halfword W=word D=doubleword
|
||||
*/
|
||||
|
||||
#define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8, BYTES_IN_MIPS_REGS, A, A1, I)
|
||||
#define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
|
||||
#define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS, A, A1, I)
|
||||
#define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
|
||||
|
||||
#define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8, BYTES_IN_MIPS_REGS, A, A1, I)
|
||||
#define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
|
||||
#define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS, A, A1, I)
|
||||
#define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
|
||||
|
||||
#define GPR_SB(R,I) SUB_REG_SB(®ISTERS[R], ®ISTERS1[R], I)
|
||||
#define GPR_SH(R,I) SUB_REG_SH(®ISTERS[R], ®ISTERS1[R], I)
|
||||
#define GPR_SW(R,I) SUB_REG_SW(®ISTERS[R], ®ISTERS1[R], I)
|
||||
#define GPR_SD(R,I) SUB_REG_SD(®ISTERS[R], ®ISTERS1[R], I)
|
||||
|
||||
#define GPR_UB(R,I) SUB_REG_UB(®ISTERS[R], ®ISTERS1[R], I)
|
||||
#define GPR_UH(R,I) SUB_REG_UH(®ISTERS[R], ®ISTERS1[R], I)
|
||||
#define GPR_UW(R,I) SUB_REG_UW(®ISTERS[R], ®ISTERS1[R], I)
|
||||
#define GPR_UD(R,I) SUB_REG_UD(®ISTERS[R], ®ISTERS1[R], I)
|
||||
|
||||
|
||||
#define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
|
||||
#define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
|
||||
#define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
|
||||
#define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
|
||||
|
||||
#define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
|
||||
#define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
|
||||
#define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
|
||||
#define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
|
||||
|
||||
#define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
|
||||
#define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
|
||||
#define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
|
||||
#define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
|
||||
|
||||
#define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
|
||||
#define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
|
||||
#define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
|
||||
#define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
|
||||
|
||||
|
||||
|
||||
#define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
|
||||
#define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
|
||||
#define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
|
||||
#define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
|
||||
|
||||
#define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
|
||||
#define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
|
||||
#define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
|
||||
#define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
|
||||
|
||||
#define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
|
||||
#define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
|
||||
#define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
|
||||
#define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
|
||||
|
||||
#define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
|
||||
#define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
|
||||
#define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
|
||||
#define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
|
||||
|
||||
/* end-sanitize-r5900 */
|
||||
|
||||
|
||||
|
||||
|
||||
struct _sim_cpu {
|
||||
|
||||
|
||||
/* The following are internal simulator state variables: */
|
||||
#define CPU_CIA(CPU) (PC)
|
||||
address_word dspc; /* delay-slot PC */
|
||||
#define DSPC ((STATE_CPU (sd,0))->dspc)
|
||||
|
||||
/* Issue a delay slot instruction immediatly by re-calling
|
||||
idecode_issue */
|
||||
#define DELAY_SLOT(TARGET) \
|
||||
do { \
|
||||
address_word target = (TARGET); \
|
||||
instruction_word delay_insn; \
|
||||
sim_events_slip (sd, 1); \
|
||||
CIA = CIA + 4; \
|
||||
STATE |= simDELAYSLOT; \
|
||||
delay_insn = IMEM (CIA); \
|
||||
idecode_issue (sd, delay_insn, (CIA)); \
|
||||
STATE &= ~simDELAYSLOT; \
|
||||
NIA = target; \
|
||||
} while (0)
|
||||
#define NULLIFY_NEXT_INSTRUCTION() \
|
||||
do { \
|
||||
sim_events_slip (sd, 1); \
|
||||
dotrace (sd, tracefh, 2, NIA, 4, "load instruction"); \
|
||||
NIA = CIA + 8; \
|
||||
} while (0)
|
||||
|
||||
|
||||
|
||||
/* State of the simulator */
|
||||
unsigned int state;
|
||||
unsigned int dsstate;
|
||||
#define STATE ((STATE_CPU (sd,0))->state)
|
||||
#define DSSTATE ((STATE_CPU (sd,0))->dsstate)
|
||||
|
||||
/* Flags in the "state" variable: */
|
||||
#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
|
||||
#define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
|
||||
#define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
|
||||
#define simPCOC0 (1 << 17) /* COC[1] from current */
|
||||
#define simPCOC1 (1 << 18) /* COC[1] from previous */
|
||||
#define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
|
||||
#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
|
||||
#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
|
||||
#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
|
||||
|
||||
#define ENGINE_ISSUE_PREFIX_HOOK() \
|
||||
{ \
|
||||
/* Set previous flag, depending on current: */ \
|
||||
if (STATE & simPCOC0) \
|
||||
STATE |= simPCOC1; \
|
||||
else \
|
||||
STATE &= ~simPCOC1; \
|
||||
/* and update the current value: */ \
|
||||
if (GETFCC(0)) \
|
||||
STATE |= simPCOC0; \
|
||||
else \
|
||||
STATE &= ~simPCOC0; \
|
||||
}
|
||||
|
||||
|
||||
/* This is nasty, since we have to rely on matching the register
|
||||
numbers used by GDB. Unfortunately, depending on the MIPS target
|
||||
GDB uses different register numbers. We cannot just include the
|
||||
relevant "gdb/tm.h" link, since GDB may not be configured before
|
||||
the sim world, and also the GDB header file requires too much other
|
||||
state. */
|
||||
|
||||
#ifndef TM_MIPS_H
|
||||
#define LAST_EMBED_REGNUM (89)
|
||||
#define NUM_REGS (LAST_EMBED_REGNUM + 1)
|
||||
/* start-sanitize-r5900 */
|
||||
#undef NUM_REGS
|
||||
#define NUM_REGS (128)
|
||||
/* end-sanitize-r5900 */
|
||||
#endif
|
||||
|
||||
/* To keep this default simulator simple, and fast, we use a direct
|
||||
vector of registers. The internal simulator engine then uses
|
||||
manifests to access the correct slot. */
|
||||
|
||||
unsigned_word registers[LAST_EMBED_REGNUM + 1];
|
||||
int register_widths[NUM_REGS];
|
||||
#define REGISTERS ((STATE_CPU (sd,0))->registers)
|
||||
|
||||
#define GPR (®ISTERS[0])
|
||||
#define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
|
||||
#define FGRIDX (38)
|
||||
#define FGR (®ISTERS[FGRIDX])
|
||||
#define LO (REGISTERS[33])
|
||||
#define HI (REGISTERS[34])
|
||||
#define PC (REGISTERS[37])
|
||||
#define CAUSE (REGISTERS[36])
|
||||
#define SRIDX (32)
|
||||
#define SR (REGISTERS[SRIDX]) /* CPU status register */
|
||||
#define FCR0IDX (71)
|
||||
#define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
|
||||
#define FCR31IDX (70)
|
||||
#define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
|
||||
#define FCSR (FCR31)
|
||||
#define Debug (REGISTERS[86])
|
||||
#define DEPC (REGISTERS[87])
|
||||
#define EPC (REGISTERS[88])
|
||||
#define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
|
||||
|
||||
unsigned_word c0_config_reg;
|
||||
#define C0_CONFIG ((STATE_CPU (sd,0))->c0_config_reg)
|
||||
|
||||
/* The following are pseudonyms for standard registers */
|
||||
#define ZERO (REGISTERS[0])
|
||||
#define V0 (REGISTERS[2])
|
||||
#define A0 (REGISTERS[4])
|
||||
#define A1 (REGISTERS[5])
|
||||
#define A2 (REGISTERS[6])
|
||||
#define A3 (REGISTERS[7])
|
||||
#define SP (REGISTERS[29])
|
||||
#define RA (REGISTERS[31])
|
||||
|
||||
/* Keep the current format state for each register: */
|
||||
FP_formats fpr_state[32];
|
||||
#define FPR_STATE ((STATE_CPU (sd, 0))->fpr_state)
|
||||
|
||||
|
||||
/* Slots for delayed register updates. For the moment we just have a
|
||||
fixed number of slots (rather than a more generic, dynamic
|
||||
system). This keeps the simulator fast. However, we only allow
|
||||
for the register update to be delayed for a single instruction
|
||||
cycle. */
|
||||
#define PSLOTS (5) /* Maximum number of instruction cycles */
|
||||
int pending_in;
|
||||
int pending_out;
|
||||
int pending_total;
|
||||
int pending_slot_count[PSLOTS];
|
||||
int pending_slot_reg[PSLOTS];
|
||||
unsigned_word pending_slot_value[PSLOTS];
|
||||
#define PENDING_IN ((STATE_CPU (sd, 0))->pending_in)
|
||||
#define PENDING_OUT ((STATE_CPU (sd, 0))->pending_out)
|
||||
#define PENDING_TOTAL ((STATE_CPU (sd, 0))->pending_total)
|
||||
#define PENDING_SLOT_COUNT ((STATE_CPU (sd, 0))->pending_slot_count)
|
||||
#define PENDING_SLOT_REG ((STATE_CPU (sd, 0))->pending_slot_reg)
|
||||
#define PENDING_SLOT_VALUE ((STATE_CPU (sd, 0))->pending_slot_value)
|
||||
|
||||
/* The following are not used for MIPS IV onwards: */
|
||||
#define PENDING_FILL(r,v) {\
|
||||
/* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); */\
|
||||
if (PENDING_SLOT_REG[PENDING_IN] != (LAST_EMBED_REGNUM + 1))\
|
||||
sim_io_eprintf(sd,"Attempt to over-write pending value\n");\
|
||||
PENDING_SLOT_COUNT[PENDING_IN] = 2;\
|
||||
PENDING_SLOT_REG[PENDING_IN] = (r);\
|
||||
PENDING_SLOT_VALUE[PENDING_IN] = (uword64)(v);\
|
||||
/*printf("DBG: FILL reg %d value = 0x%s\n",(r),pr_addr(v));*/\
|
||||
PENDING_TOTAL++;\
|
||||
PENDING_IN++;\
|
||||
if (PENDING_IN == PSLOTS)\
|
||||
PENDING_IN = 0;\
|
||||
/*printf("DBG: FILL AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);*/\
|
||||
}
|
||||
|
||||
|
||||
/* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
|
||||
read-write instructions. It is set when a linked load occurs. It
|
||||
is tested and cleared by the conditional store. It is cleared
|
||||
(during other CPU operations) when a store to the location would
|
||||
no longer be atomic. In particular, it is cleared by exception
|
||||
return instructions. */
|
||||
int llbit;
|
||||
#define LLBIT ((STATE_CPU (sd, 0))->llbit)
|
||||
|
||||
|
||||
/* The HIACCESS and LOACCESS counts are used to ensure that
|
||||
corruptions caused by using the HI or LO register to close to a
|
||||
following operation are spotted. */
|
||||
|
||||
int hiaccess;
|
||||
int loaccess;
|
||||
#define HIACCESS ((STATE_CPU (sd, 0))->hiaccess)
|
||||
#define LOACCESS ((STATE_CPU (sd, 0))->loaccess)
|
||||
/* start-sanitize-r5900 */
|
||||
int hi1access;
|
||||
int lo1access;
|
||||
#define HI1ACCESS ((STATE_CPU (sd, 0))->hi1access)
|
||||
#define LO1ACCESS ((STATE_CPU (sd, 0))->lo1access)
|
||||
/* end-sanitize-r5900 */
|
||||
#if 1
|
||||
/* The 4300 and a few other processors have interlocks on hi/lo
|
||||
register reads, and hence do not have this problem. To avoid
|
||||
spurious warnings, we just disable this always. */
|
||||
#define CHECKHILO(s)
|
||||
#else
|
||||
unsigned_word HLPC;
|
||||
/* If either of the preceding two instructions have accessed the HI
|
||||
or LO registers, then the values they see should be
|
||||
undefined. However, to keep the simulator world simple, we just
|
||||
let them use the value read and raise a warning to notify the
|
||||
user: */
|
||||
#define CHECKHILO(s) {\
|
||||
if ((HIACCESS != 0) || (LOACCESS != 0)) \
|
||||
sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
|
||||
}
|
||||
/* start-sanitize-r5900 */
|
||||
#undef CHECKHILO
|
||||
#define CHECKHILO(s) {\
|
||||
if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\
|
||||
sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
|
||||
}
|
||||
/* end-sanitize-r5900 */
|
||||
#endif
|
||||
|
||||
|
||||
/* start-sanitize-r5900 */
|
||||
/* The R5900 has 128 bit registers, but the hi 64 bits are only
|
||||
touched by multimedia (MMI) instructions. The normal mips
|
||||
instructions just use the lower 64 bits. To avoid changing the
|
||||
older parts of the simulator to handle this weirdness, the high
|
||||
64 bits of each register are kept in a separate array
|
||||
(registers1). The high 64 bits of any register are by convention
|
||||
refered by adding a '1' to the end of the normal register's name.
|
||||
So LO still refers to the low 64 bits of the LO register, LO1
|
||||
refers to the high 64 bits of that same register. */
|
||||
|
||||
signed_word registers1[LAST_EMBED_REGNUM + 1];
|
||||
#define REGISTERS1 ((STATE_CPU (sd, 0))->registers1)
|
||||
#define GPR1 (®ISTERS1[0])
|
||||
#define LO1 (REGISTERS1[32])
|
||||
#define HI1 (REGISTERS1[33])
|
||||
#define REGISTER_SA (124)
|
||||
|
||||
unsigned_word sa; /* the shift amount register */
|
||||
#define SA ((STATE_CPU (sd, 0))->sa)
|
||||
|
||||
/* end-sanitize-r5900 */
|
||||
/* start-sanitize-vr5400 */
|
||||
|
||||
/* The MDMX ISA has a very very large accumulator */
|
||||
unsigned8 acc[3 * 8];
|
||||
/* end-sanitize-vr5400 */
|
||||
|
||||
sim_cpu_base base;
|
||||
};
|
||||
|
||||
|
||||
/* MIPS specific simulator watch config */
|
||||
|
||||
void watch_options_install PARAMS ((SIM_DESC sd));
|
||||
|
||||
struct swatch {
|
||||
sim_event *pc;
|
||||
sim_event *clock;
|
||||
sim_event *cycles;
|
||||
};
|
||||
|
||||
|
||||
/* FIXME: At present much of the simulator is still static */
|
||||
struct sim_state {
|
||||
|
||||
struct swatch watch;
|
||||
|
||||
sim_cpu cpu[1];
|
||||
#if (WITH_SMP)
|
||||
#define STATE_CPU(sd,n) (&(sd)->cpu[n])
|
||||
#else
|
||||
#define STATE_CPU(sd,n) (&(sd)->cpu[0])
|
||||
#endif
|
||||
|
||||
sim_state_base base;
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* Status information: */
|
||||
|
||||
/* TODO : these should be the bitmasks for these bits within the
|
||||
status register. At the moment the following are VR4300
|
||||
bit-positions: */
|
||||
#define status_KSU_mask (0x3) /* mask for KSU bits */
|
||||
#define status_KSU_shift (3) /* shift for field */
|
||||
#define ksu_kernel (0x0)
|
||||
#define ksu_supervisor (0x1)
|
||||
#define ksu_user (0x2)
|
||||
#define ksu_unknown (0x3)
|
||||
|
||||
#define status_IE (1 << 0) /* Interrupt enable */
|
||||
#define status_EXL (1 << 1) /* Exception level */
|
||||
#define status_RE (1 << 25) /* Reverse Endian in user mode */
|
||||
#define status_FR (1 << 26) /* enables MIPS III additional FP registers */
|
||||
#define status_SR (1 << 20) /* soft reset or NMI */
|
||||
#define status_BEV (1 << 22) /* Location of general exception vectors */
|
||||
#define status_TS (1 << 21) /* TLB shutdown has occurred */
|
||||
#define status_ERL (1 << 2) /* Error level */
|
||||
#define status_RP (1 << 27) /* Reduced Power mode */
|
||||
|
||||
#define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */
|
||||
|
||||
/* NOTE: We keep the following status flags as bit values (1 for true,
|
||||
0 for false). This allows them to be used in binary boolean
|
||||
operations without worrying about what exactly the non-zero true
|
||||
value is. */
|
||||
|
||||
/* UserMode */
|
||||
#define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
|
||||
|
||||
/* BigEndianMem */
|
||||
/* Hardware configuration. Affects endianness of LoadMemory and
|
||||
StoreMemory and the endianness of Kernel and Supervisor mode
|
||||
execution. The value is 0 for little-endian; 1 for big-endian. */
|
||||
#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
|
||||
/*(state & simBE) ? 1 : 0)*/
|
||||
|
||||
/* ReverseEndian */
|
||||
/* This mode is selected if in User mode with the RE bit being set in
|
||||
SR (Status Register). It reverses the endianness of load and store
|
||||
instructions. */
|
||||
#define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
|
||||
|
||||
/* BigEndianCPU */
|
||||
/* The endianness for load and store instructions (0=little;1=big). In
|
||||
User mode this endianness may be switched by setting the state_RE
|
||||
bit in the SR register. Thus, BigEndianCPU may be computed as
|
||||
(BigEndianMem EOR ReverseEndian). */
|
||||
#define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
|
||||
|
||||
|
||||
|
||||
/* Exceptions: */
|
||||
|
||||
/* NOTE: These numbers depend on the processor architecture being
|
||||
simulated: */
|
||||
#define Interrupt (0)
|
||||
#define TLBModification (1)
|
||||
#define TLBLoad (2)
|
||||
#define TLBStore (3)
|
||||
#define AddressLoad (4)
|
||||
#define AddressStore (5)
|
||||
#define InstructionFetch (6)
|
||||
#define DataReference (7)
|
||||
#define SystemCall (8)
|
||||
#define BreakPoint (9)
|
||||
#define ReservedInstruction (10)
|
||||
#define CoProcessorUnusable (11)
|
||||
#define IntegerOverflow (12) /* Arithmetic overflow (IDT monitor raises SIGFPE) */
|
||||
#define Trap (13)
|
||||
#define FPE (15)
|
||||
#define DebugBreakPoint (16)
|
||||
#define Watch (23)
|
||||
|
||||
/* The following exception code is actually private to the simulator
|
||||
world. It is *NOT* a processor feature, and is used to signal
|
||||
run-time errors in the simulator. */
|
||||
#define SimulatorFault (0xFFFFFFFF)
|
||||
|
||||
void signal_exception (SIM_DESC sd, address_word cia, int exception, ...);
|
||||
#define SignalException(exc,instruction) signal_exception (sd, cia, (exc), (instruction))
|
||||
#define SignalExceptionInterrupt() signal_exception (sd, NULL_CIA, Interrupt)
|
||||
#define SignalExceptionInstructionFetch() signal_exception (sd, cia, InstructionFetch)
|
||||
#define SignalExceptionAddressStore() signal_exception (sd, cia, AddressStore)
|
||||
#define SignalExceptionAddressLoad() signal_exception (sd, cia, AddressLoad)
|
||||
#define SignalExceptionSimulatorFault(buf) signal_exception (sd, cia, SimulatorFault, buf)
|
||||
#define SignalExceptionFPE() signal_exception (sd, cia, FPE)
|
||||
#define SignalExceptionIntegerOverflow() signal_exception (sd, cia, IntegerOverflow)
|
||||
#define SignalExceptionCoProcessorUnusable() signal_exception (sd, cia, CoProcessorUnusable)
|
||||
|
||||
|
||||
/* Co-processor accesses */
|
||||
|
||||
void cop_lw PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
|
||||
void cop_ld PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
|
||||
unsigned int cop_sw PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg));
|
||||
uword64 cop_sd PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg));
|
||||
|
||||
#define COP_LW(coproc_num,coproc_reg,memword) cop_lw(sd,cia,coproc_num,coproc_reg,memword)
|
||||
#define COP_LD(coproc_num,coproc_reg,memword) cop_ld(sd,cia,coproc_num,coproc_reg,memword)
|
||||
#define COP_SW(coproc_num,coproc_reg) cop_sw(sd,cia,coproc_num,coproc_reg)
|
||||
#define COP_SD(coproc_num,coproc_reg) cop_sd(sd,cia,coproc_num,coproc_reg)
|
||||
|
||||
void decode_coproc PARAMS ((SIM_DESC sd, address_word cia, unsigned int instruction));
|
||||
#define DecodeCoproc(instruction) decode_coproc(sd, cia, (instruction))
|
||||
|
||||
|
||||
|
||||
/* Memory accesses */
|
||||
|
||||
/* The following are generic to all versions of the MIPS architecture
|
||||
to date: */
|
||||
|
||||
/* Memory Access Types (for CCA): */
|
||||
#define Uncached (0)
|
||||
#define CachedNoncoherent (1)
|
||||
#define CachedCoherent (2)
|
||||
#define Cached (3)
|
||||
|
||||
#define isINSTRUCTION (1 == 0) /* FALSE */
|
||||
#define isDATA (1 == 1) /* TRUE */
|
||||
#define isLOAD (1 == 0) /* FALSE */
|
||||
#define isSTORE (1 == 1) /* TRUE */
|
||||
#define isREAL (1 == 0) /* FALSE */
|
||||
#define isRAW (1 == 1) /* TRUE */
|
||||
/* The parameter HOST (isTARGET / isHOST) is ignored */
|
||||
#define isTARGET (1 == 0) /* FALSE */
|
||||
/* #define isHOST (1 == 1) TRUE */
|
||||
|
||||
/* The "AccessLength" specifications for Loads and Stores. NOTE: This
|
||||
is the number of bytes minus 1. */
|
||||
#define AccessLength_BYTE (0)
|
||||
#define AccessLength_HALFWORD (1)
|
||||
#define AccessLength_TRIPLEBYTE (2)
|
||||
#define AccessLength_WORD (3)
|
||||
#define AccessLength_QUINTIBYTE (4)
|
||||
#define AccessLength_SEXTIBYTE (5)
|
||||
#define AccessLength_SEPTIBYTE (6)
|
||||
#define AccessLength_DOUBLEWORD (7)
|
||||
#define AccessLength_QUADWORD (15)
|
||||
|
||||
int address_translation PARAMS ((SIM_DESC sd, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
|
||||
#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
|
||||
address_translation(sd,cia,vAddr,IorD,LorS,pAddr,CCA,raw)
|
||||
|
||||
void load_memory PARAMS ((SIM_DESC sd, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, address_word pAddr, address_word vAddr, int IorD));
|
||||
#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
|
||||
load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD)
|
||||
|
||||
void store_memory PARAMS ((SIM_DESC sd, address_word cia, int CCA, int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
|
||||
#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
|
||||
store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr)
|
||||
|
||||
void cache_op PARAMS ((SIM_DESC sd, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
|
||||
#define CacheOp(op,pAddr,vAddr,instruction) cache_op(sd,cia,op,pAddr,vAddr,instruction)
|
||||
|
||||
void sync_operation PARAMS ((SIM_DESC sd, address_word cia, int stype));
|
||||
#define SyncOperation(stype) sync_operation (sd, cia, (stype))
|
||||
|
||||
void prefetch PARAMS ((SIM_DESC sd, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
|
||||
#define Prefetch(CCA,pAddr,vAddr,DATA,hint) prefetch(sd,cia,CCA,pAddr,vAddr,DATA,hint)
|
||||
|
||||
unsigned32 ifetch32 PARAMS ((SIM_DESC sd, address_word cia, address_word vaddr));
|
||||
#define IMEM(CIA) ifetch32 (SD, (CIA), (CIA))
|
||||
|
||||
void dotrace PARAMS ((SIM_DESC sd, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
|
||||
FILE *tracefh;
|
||||
|
||||
#endif
|
||||
@ -1,17 +0,0 @@
|
||||
/* mips target configuration file. */
|
||||
|
||||
/* Define this if the simulator supports profiling.
|
||||
See the mips simulator for an example.
|
||||
This enables the `-p foo' and `-s bar' options.
|
||||
The target is required to provide sim_set_profile{,_size}. */
|
||||
#define SIM_HAVE_PROFILE
|
||||
|
||||
/* Define this if the simulator uses an instruction cache.
|
||||
See the h8/300 simulator for an example.
|
||||
This enables the `-c size' option to set the size of the cache.
|
||||
The target is required to provide sim_set_simcache_size. */
|
||||
/* #define SIM_HAVE_SIMCACHE */
|
||||
|
||||
/* Define this if the target cpu is bi-endian
|
||||
and the simulator supports it. */
|
||||
#define SIM_HAVE_BIENDIAN
|
||||
114
sim/txvu/vpe.h
114
sim/txvu/vpe.h
@ -1,114 +0,0 @@
|
||||
/****************************************************************************/
|
||||
/* */
|
||||
/* Sony Computer Entertainment CONFIDENTIAL */
|
||||
/* (C) 1997 Sony Computer Entertainment Inc. All Rights Reserved */
|
||||
/* */
|
||||
/* VU simulator global definitions */
|
||||
/* */
|
||||
/****************************************************************************/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <sys/types.h>
|
||||
#include <strings.h>
|
||||
#include <math.h>
|
||||
|
||||
typedef struct {
|
||||
int no; /* destination register number VF:0-31 VI:32-47*/
|
||||
int mask; /* specify which units calculate */
|
||||
float vf[4]; /* calculated value */
|
||||
int flag; /*0: empty in this pipeline stage,
|
||||
1: write value to reg,
|
||||
2: store value from reg,
|
||||
3: write value to I-reg ( not used ),
|
||||
4: write only status to statusflag,
|
||||
5: write only clip value to clipflag,
|
||||
6: move value from EFU reg */
|
||||
u_long status; /* calculation unit status */
|
||||
u_long addr; /* store address ( store operation )*/
|
||||
char code[32]; /* instruction */
|
||||
} PIPELINE; /* pipeline stage specification for FMAC, Ld/St, RANDU, FDIV */
|
||||
|
||||
typedef struct {
|
||||
int no; /* destination register number VI:0-15 */
|
||||
short vi; /* calculated value */
|
||||
int flag; /* 0: empty in this pipeline stage,
|
||||
1: write value to reg */
|
||||
char code[32]; /* instruction */
|
||||
} IPIPELINE; /* pipeline stage specification for IALU */
|
||||
|
||||
typedef struct {
|
||||
int flag; /* 0: empty in this pipeline stage,
|
||||
1: write value to I-reg */
|
||||
float val; /* calculated value */
|
||||
} LOIPIPELINE; /* pipeline stage specification for I bit */
|
||||
|
||||
typedef struct {
|
||||
int mask; /* specify which units calculate */
|
||||
float acc[4]; /* calculated value */
|
||||
int flag; /* 0: empty in this pipeline stage,
|
||||
1: write value to ACC */
|
||||
} APIPELINE; /* accumulator pipeline stage specification */
|
||||
|
||||
typedef struct {
|
||||
int no; /* left stage count of pipeline */
|
||||
float vn; /* calculated value */
|
||||
int flag; /* 0: move to VN[4]
|
||||
1: move to VN[0] (not used)*/
|
||||
} SUPIPELINE;
|
||||
|
||||
u_long instbuf[2]; /* instruction buffer. instbuf[0]:Upper, instbuf[1]:Lower*/
|
||||
u_long pc, opc; /* pc is next PC, opc is executed PC. see fetch_inst() */
|
||||
u_long jaddr; /* branch address */
|
||||
|
||||
float VF[32][4]; /* VF registers */
|
||||
/* VF[?][0] = x, VF[?][1] = y, VF[?][2] = z, VF[?][3] = w */
|
||||
short VI[16]; /* VI registers */
|
||||
float ACC[4]; /* accumulator registers */
|
||||
float Q; /* FDIV register */
|
||||
float I; /* I register */
|
||||
u_long R; /* RANDU register */
|
||||
float VN[32]; /* EFU registers */
|
||||
u_long MACflag;
|
||||
u_long statusflag;
|
||||
u_long clipflag;
|
||||
|
||||
u_long MEM[4096][4]; /* VU (data) memory */
|
||||
u_long uMEM[1024][2]; /* Micro (instruction) memory */
|
||||
|
||||
PIPELINE pipe[4][2]; /* FMAC, Ld/St, RANDU piepline */
|
||||
PIPELINE qpipe[7]; /* FDIV(DIV,DQRT) pipeline */
|
||||
PIPELINE rqpipe[13]; /*FDIV(RSQRT) pipeline */
|
||||
IPIPELINE ipipe[2]; /* IALU pipeline */
|
||||
APIPELINE apipe; /* ACC pipeline stage */
|
||||
SUPIPELINE spipe; /* EFU pipeline stage */
|
||||
LOIPIPELINE Ipipe; /* I-bit pipeline stage */
|
||||
|
||||
int eflag, jflag, peflag, sflag;
|
||||
/* eflag: E-bit detect flag
|
||||
0: not detect, 1: detect, -1: fetch stage terminate
|
||||
jflag: branch detect flag
|
||||
0: not detect, 1: detect
|
||||
peflag: end delay slot execute flag
|
||||
0: not execute, 1: execute, -1: finished ececution
|
||||
sflag: data hazard stall flag
|
||||
0: not stall, 1: stall */
|
||||
u_long bp; /* break point address */
|
||||
u_long ecount; /* end counter */
|
||||
int intr_mode; /* interactive mode enable */
|
||||
int verb_mode; /* verbose mode enable */
|
||||
int dpr_mode; /* PRT (debug print) instruction enable */
|
||||
u_long all_count; /* amount of executed cycles */
|
||||
u_long hc_count; /* amount of hazard stall cycles */
|
||||
|
||||
extern int _GIF_SIM_OFF; /* internal GPUIF simulator disable */
|
||||
extern int _GIF_BUSY; /* external GPUIF simulator is BUSY flag,
|
||||
this flag uses when _GIF_SIM_OFF = 1 */
|
||||
extern int _GIF_VUCALL; /* XGKICK instruction detect flag,
|
||||
this flag uses when _GIF_SIM_OFF = 1 */
|
||||
extern int _GIF_VUADDR; /* appointed address by XGKICK instruction,
|
||||
this flag uses when _GIF_SIM_OFF = 1 */
|
||||
|
||||
#define DEST_X 0x8
|
||||
#define DEST_Y 0x4
|
||||
#define DEST_Z 0x2
|
||||
#define DEST_W 0x1
|
||||
@ -1,241 +0,0 @@
|
||||
|
||||
|
||||
// Integer Instructions
|
||||
// --------------------
|
||||
//
|
||||
// MulAcc is the Multiply Accumulator.
|
||||
// This register is mapped on the the HI and LO registers.
|
||||
// Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
|
||||
// Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.
|
||||
|
||||
|
||||
:function:::unsigned64:MulAcc:
|
||||
{
|
||||
unsigned64 result = U8_4 (HI, LO);
|
||||
return result;
|
||||
}
|
||||
|
||||
:function:::void:SET_MulAcc:unsigned64 value
|
||||
{
|
||||
*AL4_8 (&HI) = VH4_8 (value);
|
||||
*AL4_8 (&LO) = VL4_8 (value);
|
||||
}
|
||||
|
||||
:function:::signed64:SignedMultiply:signed32 l, signed32 r
|
||||
{
|
||||
signed64 result = (signed64) l * (signed64) r;
|
||||
return result;
|
||||
}
|
||||
|
||||
:function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
|
||||
{
|
||||
unsigned64 result = (unsigned64) l * (unsigned64) r;
|
||||
return result;
|
||||
}
|
||||
|
||||
:function:::unsigned64:Low32Bits:unsigned64 value
|
||||
{
|
||||
unsigned64 result = (signed64) (signed32) VL4_8 (value);
|
||||
return result;
|
||||
}
|
||||
|
||||
:function:::unsigned64:High32Bits:unsigned64 value
|
||||
{
|
||||
unsigned64 result = (signed64) (signed32) VH4_8 (value);
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
|
||||
// Multiply and Move LO.
|
||||
000000,5.RS,5.RT,5.RD,00001,011000::::MUL
|
||||
"mul r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// Unsigned Multiply and Move LO.
|
||||
000000,5.RS,5.RT,5.RD,00001,011001::::MULU
|
||||
"mulu r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// Multiply and Move HI.
|
||||
000000,5.RS,5.RT,5.RD,01001,011000::::MULHI
|
||||
"mulhi r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// Unsigned Multiply and Move HI.
|
||||
000000,5.RS,5.RT,5.RD,01001,011001::::MULHIU
|
||||
"mulhiu r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
|
||||
// Multiply, Negate and Move LO.
|
||||
000000,5.RS,5.RT,5.RD,00011,011000::::MULS
|
||||
"muls r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, 0 - SignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// Unsigned Multiply, Negate and Move LO.
|
||||
000000,5.RS,5.RT,5.RD,00011,011001::::MULSU
|
||||
"mulsu r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// Multiply, Negate and Move HI.
|
||||
000000,5.RS,5.RT,5.RD,01011,011000::::MULSHI
|
||||
"mulshi r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, 0 - SignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// Unsigned Multiply, Negate and Move HI.
|
||||
000000,5.RS,5.RT,5.RD,01011,011001::::MULSHIU
|
||||
"mulshiu r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
|
||||
// Multiply, Accumulate and Move LO.
|
||||
000000,5.RS,5.RT,5.RD,00101,011000::::MACC
|
||||
"macc r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// Unsigned Multiply, Accumulate and Move LO.
|
||||
000000,5.RS,5.RT,5.RD,00101,011001::::MACCU
|
||||
"maccu r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// Multiply, Accumulate and Move HI.
|
||||
000000,5.RS,5.RT,5.RD,01101,011000::::MACCHI
|
||||
"macchi r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// Unsigned Multiply, Accumulate and Move HI.
|
||||
000000,5.RS,5.RT,5.RD,01101,011001::::MACCHIU
|
||||
"macchiu r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
|
||||
|
||||
}
|
||||
|
||||
// Multiply, Negate, Accumulate and Move LO.
|
||||
000000,5.RS,5.RT,5.RD,00111,011000::::MSAC
|
||||
"msac r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// Unsigned Multiply, Negate, Accumulate and Move LO.
|
||||
000000,5.RS,5.RT,5.RD,00111,011001::::MSACU
|
||||
"msacu r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// Multiply, Negate, Accumulate and Move HI.
|
||||
000000,5.RS,5.RT,5.RD,01111,011000::::MSACHI
|
||||
"msachi r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
// Unsigned Multiply, Negate, Accumulate and Move HI.
|
||||
000000,5.RS,5.RT,5.RD,01111,011001::::MSACHIU
|
||||
"msachiu r<RD>, r<RS>, r<RT>"
|
||||
*vr5400:
|
||||
{
|
||||
SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
|
||||
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
|
||||
}
|
||||
|
||||
|
||||
// Rotate Right.
|
||||
000000,00001,5.RT,5.RD,5.SHIFT,000010::::ROR
|
||||
"ror r<RD>, r<RT>, <SHIFT>"
|
||||
*vr5400:
|
||||
{
|
||||
int s = SHIFT;
|
||||
GPR[RD] = ROTR32 (GPR[RT], s);
|
||||
}
|
||||
|
||||
// Rotate Right Variable.
|
||||
000000,5.RS,5.RT,5.RD,00001,000110::::RORV
|
||||
"rorv r<RD>, r<RT>, <RS>"
|
||||
*vr5400:
|
||||
{
|
||||
int s = MASKED (GPR[RS], 4, 0);
|
||||
GPR[RD] = ROTR32 (GPR[RT], s);
|
||||
}
|
||||
|
||||
// Double Rotate Right.
|
||||
000000,00001,5.RT,5.RD,5.SHIFT,111010::::DROR
|
||||
"dror r<RD>, r<RT>, <SHIFT>"
|
||||
*vr5400:
|
||||
{
|
||||
int s = SHIFT;
|
||||
GPR[RD] = ROTR64 (GPR[RT], s);
|
||||
}
|
||||
|
||||
// Double Rotate Right Plus 32.
|
||||
000000,00001,5.RT,5.RD,5.SHIFT,111110::::DROR32
|
||||
"dror32 r<RD>, r<RT>, <SHIFT>"
|
||||
*vr5400:
|
||||
{
|
||||
int s = SHIFT + 32;
|
||||
GPR[RD] = ROTR64 (GPR[RT], s);
|
||||
}
|
||||
|
||||
// Double Rotate Right Variable.
|
||||
000000,5.RS,5.RT,5.RD,00001,010110::::DRORV
|
||||
"drorv r<RD>, r<RT>, <RS>"
|
||||
*vr5400:
|
||||
{
|
||||
int s = MASKED (GPR[RS], 5, 0);
|
||||
GPR[RD] = ROTR64 (GPR[RT], s);
|
||||
}
|
||||
@ -1,49 +0,0 @@
|
||||
/* Copyright (C) 1998, Cygnus Solutions
|
||||
|
||||
*/
|
||||
|
||||
#ifndef VU_H_
|
||||
#define VU_H_
|
||||
|
||||
#include "sim-main.h"
|
||||
#include <sys/types.h>
|
||||
|
||||
typedef u_long MEM_Entry_Type[4];
|
||||
typedef u_long uMEM_Entry_Type[2];
|
||||
|
||||
typedef enum { VU_READY, VU_RUN, VU_BREAK } RunState;
|
||||
|
||||
/* See VU Specifications (Ver. 2.10), p7-11 */
|
||||
typedef struct {
|
||||
u_long vbs : 1; /* busy 0: Idle, 1: Busy */
|
||||
u_long vds : 1; /* D bit stop 0: No D bit stop, 1: D bit stop */
|
||||
u_long vts : 1; /* T bit stop 0: No T bit stop, 1: T bit stop*/
|
||||
u_long vfs : 1; /* ForceBreak stop 0: no ForceBreak stop, 1: ForceBreak stop*/
|
||||
u_long vgw : 1; /* XGKICK wait 0: Do not wait, 1: Wait */
|
||||
u_long div : 1; /* DIV busy 0: Idle, 1: Busy*/
|
||||
u_long efu : 1; /* EF busy 0: Idle, 1: Busy */
|
||||
u_long reserved_2:25;
|
||||
} VpeStat;
|
||||
|
||||
typedef struct {
|
||||
float VF[32][4];
|
||||
short VI[16];
|
||||
u_long MST;
|
||||
u_long MMC;
|
||||
u_long MCP;
|
||||
u_long MR;
|
||||
u_long MI;
|
||||
u_long MQ;
|
||||
u_long MP;
|
||||
u_long MTPC;
|
||||
VpeStat VPE_STAT;
|
||||
} VectorUnitRegs;
|
||||
|
||||
typedef struct {
|
||||
MEM_Entry_Type *MEM; /* VU (data) memory */
|
||||
uMEM_Entry_Type *uMEM; /* Micro (instruction) memory */
|
||||
VectorUnitRegs regs;
|
||||
RunState runState;
|
||||
} VectorUnitState;
|
||||
|
||||
#endif
|
||||
@ -1,86 +0,0 @@
|
||||
/* Copyright (C) 1998, Cygnus Solutions
|
||||
|
||||
*/
|
||||
|
||||
#include "sim-main.h"
|
||||
|
||||
#include "device.h"
|
||||
#include "vu0.h"
|
||||
|
||||
static char vu0_mem0_buffer[VU0_MEM0_SIZE];
|
||||
static char vu0_mem1_buffer[VU0_MEM1_SIZE];
|
||||
|
||||
void
|
||||
vu0_issue()
|
||||
{
|
||||
}
|
||||
|
||||
int
|
||||
vu0_io_read_buffer(device *me,
|
||||
void *dest,
|
||||
int space,
|
||||
address_word addr,
|
||||
unsigned nr_bytes,
|
||||
sim_cpu *processor,
|
||||
sim_cia cia)
|
||||
{
|
||||
printf("%s: Read!\n", me->name);
|
||||
return nr_bytes;
|
||||
}
|
||||
|
||||
int
|
||||
vu0_io_write_buffer(device *me,
|
||||
const void *source,
|
||||
int space,
|
||||
address_word addr,
|
||||
unsigned nr_bytes,
|
||||
sim_cpu *processor,
|
||||
sim_cia cia)
|
||||
{
|
||||
printf("%s: Write!\n", me->name);
|
||||
return nr_bytes;
|
||||
}
|
||||
|
||||
device vu0_device =
|
||||
{
|
||||
"vu0",
|
||||
&vu0_io_read_buffer,
|
||||
&vu0_io_write_buffer
|
||||
};
|
||||
|
||||
void
|
||||
vu0_attach(SIM_DESC sd)
|
||||
{
|
||||
sim_core_attach (sd,
|
||||
NULL,
|
||||
0 /*level*/,
|
||||
access_read_write,
|
||||
0 /*space ???*/,
|
||||
VU0_REGISTER_WINDOW_START,
|
||||
VU0_REGISTER_WINDOW_SIZE /*nr_bytes*/,
|
||||
0 /*modulo*/,
|
||||
&vu0_device,
|
||||
NULL /*buffer*/);
|
||||
|
||||
sim_core_attach (sd,
|
||||
NULL,
|
||||
0 /*level*/,
|
||||
access_read_write,
|
||||
0 /*space ???*/,
|
||||
VU0_MEM0_WINDOW_START,
|
||||
VU0_MEM0_SIZE /*nr_bytes*/,
|
||||
0 /*modulo*/,
|
||||
0 /*device*/,
|
||||
&vu0_mem0_buffer /*buffer*/);
|
||||
|
||||
sim_core_attach (sd,
|
||||
NULL,
|
||||
0 /*level*/,
|
||||
access_read_write,
|
||||
0 /*space ???*/,
|
||||
VU0_MEM1_WINDOW_START,
|
||||
VU0_MEM1_SIZE /*nr_bytes*/,
|
||||
0 /*modulo*/,
|
||||
0 /*device*/,
|
||||
&vu0_mem1_buffer /*buffer*/);
|
||||
}
|
||||
@ -1,37 +0,0 @@
|
||||
/* Copyright (C) 1998, Cygnus Solutions
|
||||
|
||||
*/
|
||||
|
||||
#ifndef VU0_H_
|
||||
#define VU0_H_
|
||||
|
||||
#include "sim-main.h"
|
||||
|
||||
void vu0_attach(SIM_DESC sd);
|
||||
void vu0_issue();
|
||||
|
||||
#define VU0_MEM0_WINDOW_START 0x11000000
|
||||
#define VU0_MEM0_SIZE 0x1000 /* 4K = 4096 */
|
||||
|
||||
#define VU0_MEM1_WINDOW_START 0x11004000
|
||||
#define VU0_MEM1_SIZE 0x1000 /* 4K = 4096 */
|
||||
|
||||
#define VU0_REGISTER_WINDOW_START 0x10000c00
|
||||
|
||||
#define VU0_VF00 0x10000c00
|
||||
/* ... */
|
||||
#define VU0_VF31 0x10000df0
|
||||
|
||||
#define VU0_VI00 0x10000e00
|
||||
/* ... */
|
||||
#define VU0_VI15 0x10000ef0
|
||||
|
||||
/* ... */
|
||||
|
||||
#define VPE0_STAT 0x10000fd0
|
||||
|
||||
#define VU0_REGISTER_WINDOW_END 0x10000fe0
|
||||
|
||||
#define VU0_REGISTER_WINDOW_SIZE (VU0_REGISTER_WINDOW_END - VU0_REGISTER_WINDOW_START)
|
||||
|
||||
#endif
|
||||
323
sim/txvu/vu1.c
323
sim/txvu/vu1.c
@ -1,323 +0,0 @@
|
||||
/* Copyright (C) 1998, Cygnus Solutions
|
||||
|
||||
*/
|
||||
|
||||
#include "sim-main.h"
|
||||
|
||||
#include "device.h"
|
||||
#include "vu1.h"
|
||||
#include "libvpe.h"
|
||||
#include "vu.h"
|
||||
|
||||
VectorUnitState vu1_state;
|
||||
|
||||
static char vu1_umem_buffer[VU1_MEM0_SIZE];
|
||||
static char vu1_mem_buffer[VU1_MEM1_SIZE];
|
||||
|
||||
void init_vu1();
|
||||
void init_vu(VectorUnitState *state, char* umem_buffer, char* mem_buffer);
|
||||
|
||||
void
|
||||
vu1_issue()
|
||||
{
|
||||
if (vu1_state.runState == VU_RUN)
|
||||
vpecallms_cycle(&vu1_state);
|
||||
}
|
||||
|
||||
int
|
||||
vu1_io_read_register_window(device *me,
|
||||
void *dest,
|
||||
int space,
|
||||
address_word addr,
|
||||
unsigned nr_bytes,
|
||||
sim_cpu *processor,
|
||||
sim_cia cia)
|
||||
{
|
||||
/* Slow and crappy hack ... */
|
||||
|
||||
int i;
|
||||
|
||||
char source_buffer[VU1_REGISTER_WINDOW_SIZE];
|
||||
char* src;
|
||||
|
||||
memcpy(source_buffer, &vu1_state.regs.VF[0][0], 0x200); /* copy VF registers */
|
||||
for (i = 0; i<16; i++ ) {
|
||||
*(short*)&source_buffer[0x200 + i*16] = vu1_state.regs.VI[i];
|
||||
}
|
||||
*(u_long*)&source_buffer[VU1_MST - VU1_REGISTER_WINDOW_START] = vu1_state.regs.MST;
|
||||
*(u_long*)&source_buffer[VU1_MMC - VU1_REGISTER_WINDOW_START] = vu1_state.regs.MMC;
|
||||
*(u_long*)&source_buffer[VU1_MCP - VU1_REGISTER_WINDOW_START] = vu1_state.regs.MCP;
|
||||
*(u_long*)&source_buffer[VU1_MR - VU1_REGISTER_WINDOW_START] = vu1_state.regs.MR;
|
||||
*(u_long*)&source_buffer[VU1_MI - VU1_REGISTER_WINDOW_START] = vu1_state.regs.MI;
|
||||
*(u_long*)&source_buffer[VU1_MQ - VU1_REGISTER_WINDOW_START] = vu1_state.regs.MQ;
|
||||
*(u_long*)&source_buffer[VU1_MP - VU1_REGISTER_WINDOW_START] = vu1_state.regs.MP;
|
||||
*(u_long*)&source_buffer[VU1_MTPC - VU1_REGISTER_WINDOW_START] = vu1_state.regs.MTPC;
|
||||
*(VpeStat*)&source_buffer[VPE1_STAT - VU1_REGISTER_WINDOW_START] = vu1_state.regs.VPE_STAT;
|
||||
|
||||
printf("%s: Read: %x, %d, dest: %x, space: %d, %x!\n", me->name, addr, nr_bytes, dest, space, vu1_state.regs.VPE_STAT);
|
||||
printf(" vu1_state.regs.VPE_STAT = %x\n", vu1_state.regs.VPE_STAT);
|
||||
|
||||
if (addr + nr_bytes > VU1_REGISTER_WINDOW_END) {
|
||||
fprintf(stderr, "Error: Read past end of vu1 register window!!!\n");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
src = &source_buffer[0] + (addr - VU1_REGISTER_WINDOW_START);
|
||||
memcpy(dest, src, nr_bytes);
|
||||
return nr_bytes;
|
||||
}
|
||||
|
||||
int
|
||||
vu1_io_write_register_window(device *me,
|
||||
const void *source,
|
||||
int space,
|
||||
address_word addr,
|
||||
unsigned nr_bytes,
|
||||
sim_cpu *processor,
|
||||
sim_cia cia)
|
||||
{
|
||||
char *dest;
|
||||
|
||||
if (addr == VPE1_STAT && nr_bytes == 4) {
|
||||
/* Magic to switch VU to run state, until other methods are available. */
|
||||
vu1_state.runState = VU_RUN;
|
||||
vu1_state.regs.VPE_STAT.vbs = 1;
|
||||
printf("Magic start run...\n");
|
||||
printf("%x,%x,%x,%x\n", &vu1_state.regs.VF[0][0], &vu1_state.regs.VPE_STAT,
|
||||
((char*)&vu1_state.regs.VPE_STAT) - ((char*)&vu1_state.regs.VF[0][0]),
|
||||
((char*)&vu1_state.regs.VPE_STAT) - ((char*)&vu1_state.regs.VF[0][0]) + VU1_REGISTER_WINDOW_START
|
||||
);
|
||||
|
||||
printf("%x,%x,%x,%x\n", &vu1_state.regs.VF[0][0], &vu1_state.regs.VI[0],
|
||||
((char*)&vu1_state.regs.VI[0]) - ((char*)&vu1_state.regs.VF[0][0]),
|
||||
((char*)&vu1_state.regs.VI[0]) - ((char*)&vu1_state.regs.VF[0][0]) + VU1_REGISTER_WINDOW_START
|
||||
);
|
||||
printf("%x,%x,%x,%x\n", &vu1_state.regs.VF[0][0], &vu1_state.regs.MST,
|
||||
((char*)&vu1_state.regs.MST) - ((char*)&vu1_state.regs.VF[0][0]),
|
||||
((char*)&vu1_state.regs.MST) - ((char*)&vu1_state.regs.VF[0][0]) + VU1_REGISTER_WINDOW_START
|
||||
);
|
||||
return nr_bytes;
|
||||
}
|
||||
|
||||
printf("%s: Write: %x, %d, source: %x, space: %d!\n", me->name, addr, nr_bytes, source, space);
|
||||
|
||||
if (addr + nr_bytes > VU1_REGISTER_WINDOW_END) {
|
||||
fprintf(stderr, "Error: Read past end of vu1 register window!!!\n");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
dest = ((char*) (&vu1_state.regs)) + (addr - VU1_REGISTER_WINDOW_START);
|
||||
|
||||
memcpy(dest, source, nr_bytes);
|
||||
|
||||
return nr_bytes;
|
||||
}
|
||||
|
||||
device vu1_device =
|
||||
{
|
||||
"vu1",
|
||||
&vu1_io_read_register_window,
|
||||
&vu1_io_write_register_window
|
||||
};
|
||||
|
||||
void
|
||||
vu1_init(SIM_DESC sd)
|
||||
{
|
||||
|
||||
sim_core_attach (sd,
|
||||
NULL,
|
||||
0 /*level*/,
|
||||
access_read_write,
|
||||
0 /*space ???*/,
|
||||
VU1_REGISTER_WINDOW_START,
|
||||
VU1_REGISTER_WINDOW_SIZE /*nr_bytes*/,
|
||||
0 /*modulo*/,
|
||||
&vu1_device,
|
||||
NULL /*buffer*/);
|
||||
|
||||
sim_core_attach (sd,
|
||||
NULL,
|
||||
0 /*level*/,
|
||||
access_read_write,
|
||||
0 /*space ???*/,
|
||||
VU1_MEM0_WINDOW_START,
|
||||
VU1_MEM0_SIZE /*nr_bytes*/,
|
||||
0 /*modulo*/,
|
||||
0 /*device*/,
|
||||
&vu1_umem_buffer /*buffer*/);
|
||||
|
||||
sim_core_attach (sd,
|
||||
NULL,
|
||||
0 /*level*/,
|
||||
access_read_write,
|
||||
0 /*space ???*/,
|
||||
VU1_MEM1_WINDOW_START,
|
||||
VU1_MEM1_SIZE /*nr_bytes*/,
|
||||
0 /*modulo*/,
|
||||
0 /*device*/,
|
||||
&vu1_mem_buffer /*buffer*/);
|
||||
|
||||
init_vu1();
|
||||
/*initvpe();*/
|
||||
vpecallms_init(&vu1_state);
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/* */
|
||||
/* Sony Computer Entertainment CONFIDENTIAL */
|
||||
/* (C) 1997 Sony Computer Entertainment Inc. All Rights Reserved */
|
||||
/* */
|
||||
/* VPE1 simulator */
|
||||
/* */
|
||||
/****************************************************************************/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <sys/types.h>
|
||||
#include <strings.h>
|
||||
#include "libvpe.h"
|
||||
|
||||
char ifilename[64] = "vu.bin";
|
||||
char ofilename[64] = "";
|
||||
char pfilename[64] = "";
|
||||
|
||||
void abend2(char *fmt, char* p) {
|
||||
fprintf(stderr, fmt, p);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
void getoption();
|
||||
|
||||
void init_vu1() {
|
||||
init_vu(&vu1_state, &vu1_umem_buffer[0], &vu1_mem_buffer[0]);
|
||||
}
|
||||
|
||||
void init_vu(VectorUnitState *state, char* umem_buffer, char* mem_buffer)
|
||||
{
|
||||
FILE *fp;
|
||||
int i, j;
|
||||
u_long data[4];
|
||||
|
||||
/* set up memory buffers */
|
||||
state->uMEM = (uMEM_Entry_Type *) umem_buffer;
|
||||
state->MEM = (MEM_Entry_Type*) mem_buffer;
|
||||
|
||||
/* set up run state */
|
||||
state->runState = VU_READY;
|
||||
|
||||
/* read option */
|
||||
getoption();
|
||||
|
||||
/* read instruction file (mandatory) */
|
||||
if (*ifilename) {
|
||||
if((fp = fopen(ifilename, "r")) == NULL)
|
||||
abend2("%s: can not open\n", ifilename);
|
||||
|
||||
for (i = 0; fread(&data[0], 4, 1, fp) != 0; i++) {
|
||||
fread(&data[1], 4, 1, fp);
|
||||
LoadMMem(state, i, data, 1);
|
||||
}
|
||||
fclose(fp);
|
||||
}
|
||||
|
||||
/* PKE dirven simvpe */
|
||||
if (*pfilename) {
|
||||
/* initpke(pfilename); */
|
||||
initvpe(&vu1_state);
|
||||
/* while (simpke() != -1)
|
||||
simvpe(); */
|
||||
}
|
||||
|
||||
/* conventional simvpe */
|
||||
else {
|
||||
initvpe(&vu1_state);
|
||||
/*simvpe();*/
|
||||
}
|
||||
|
||||
/* write result memory image (optional) */
|
||||
if (*ofilename) {
|
||||
if((fp = fopen(ofilename, "w")) == NULL)
|
||||
abend2("%s: can not open\n", ofilename);
|
||||
|
||||
for(i = 0; i < 2048; i++){
|
||||
StoreVUMem(i, data, 1);
|
||||
for(j = 0; j < 4; j++)
|
||||
fwrite(&data[j], 4, 1, fp);
|
||||
}
|
||||
fclose(fp);
|
||||
}
|
||||
}
|
||||
|
||||
static void Usage(void)
|
||||
{
|
||||
fprintf(stderr, "Usage: simvpe [options]\n");
|
||||
fprintf(stderr, "\t\t-i instruction-file\n");
|
||||
fprintf(stderr, "\t\t-o output-memory-file\n");
|
||||
fprintf(stderr, "\t\t-t PKE-file (text type)\n");
|
||||
fprintf(stderr, "\t\t-s start-address [default = 0]\n");
|
||||
fprintf(stderr, "\t\t-d [interactive mode enable: default desable]\n");
|
||||
fprintf(stderr, "\t\t-v [statistics mode enable: default desable]\n");
|
||||
fprintf(stderr, "\t\t-p [debug print mode enable: default desable]\n");
|
||||
}
|
||||
|
||||
void getoption()
|
||||
{
|
||||
int startline = 0;
|
||||
int count = 1;
|
||||
|
||||
_is_dbg = 1;
|
||||
_vpepc = 0;
|
||||
_is_verb = 0;
|
||||
_is_dump = 0;
|
||||
_pgpuif = 2;
|
||||
_ITOP = 20;
|
||||
_TOP = 10;
|
||||
|
||||
#if 0
|
||||
while(argc - count){
|
||||
if(argv[count][0] == '-'){
|
||||
switch(argv[count][1]){
|
||||
case 'i':
|
||||
strcpy(ifilename, argv[count+1]);
|
||||
count += 2;
|
||||
break;
|
||||
case 'o':
|
||||
strcpy(ofilename, argv[count+1]);
|
||||
count += 2;
|
||||
break;
|
||||
case 't':
|
||||
strcpy(pfilename, argv[count+1]);
|
||||
count += 2;
|
||||
break;
|
||||
case 's':
|
||||
sscanf(argv[count+1], "%d", &startline);
|
||||
_vpepc = startline;
|
||||
count += 2;
|
||||
break;
|
||||
case 'd':
|
||||
_is_dbg = 1;
|
||||
count += 1;
|
||||
break;
|
||||
case 'v':
|
||||
_is_verb = 1;
|
||||
count += 1;
|
||||
break;
|
||||
case 'p':
|
||||
_is_dump = 1;
|
||||
count += 1;
|
||||
break;
|
||||
case 'h':
|
||||
case '?':
|
||||
Usage();
|
||||
exit(1);
|
||||
break;
|
||||
default:
|
||||
Usage();
|
||||
exit(1);
|
||||
}
|
||||
}else{
|
||||
Usage();
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
@ -1,43 +0,0 @@
|
||||
/* Copyright (C) 1998, Cygnus Solutions
|
||||
|
||||
*/
|
||||
|
||||
#ifndef VU1_H_
|
||||
#define VU1_H_
|
||||
|
||||
#include "sim-main.h"
|
||||
|
||||
void vu1_attach(SIM_DESC sd);
|
||||
void vu1_issue();
|
||||
|
||||
#define VU1_MEM0_WINDOW_START 0x11008000
|
||||
#define VU1_MEM0_SIZE 0x4000 /* 16K = 16384 */
|
||||
|
||||
#define VU1_MEM1_WINDOW_START 0x1100c000
|
||||
#define VU1_MEM1_SIZE 0x4000 /* 16K = 16384 */
|
||||
|
||||
#define VU1_REGISTER_WINDOW_START 0x11007000
|
||||
|
||||
#define VU1_VF00 0x11007000
|
||||
/* ... */
|
||||
#define VU1_VF31 0x110071f0
|
||||
|
||||
#define VU1_VI00 0x11007200
|
||||
/* ... */
|
||||
#define VU1_VI15 0x110072f0
|
||||
|
||||
#define VU1_MST 0x11007300
|
||||
#define VU1_MMC 0x11007310
|
||||
#define VU1_MCP 0x11007320
|
||||
#define VU1_MR 0x11007330
|
||||
#define VU1_MI 0x11007340
|
||||
#define VU1_MQ 0x11007350
|
||||
#define VU1_MP 0x11007360
|
||||
#define VU1_MTPC 0x110073a0
|
||||
#define VPE1_STAT 0x110073d0
|
||||
|
||||
#define VU1_REGISTER_WINDOW_END 0x110073e0
|
||||
|
||||
#define VU1_REGISTER_WINDOW_SIZE (VU1_REGISTER_WINDOW_END - VU1_REGISTER_WINDOW_START)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user