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* config/tc-xtensa.c (xg_get_build_instr_size): Remove.
(xg_is_narrow_insn, xg_expand_narrow): Remove. Merge into... (xg_is_single_relaxable_insn): ...here. Add "targ" and "narrow_only" parameters. (xg_assembly_relax, xg_find_narrowest_format, relaxation_requirements, convert_frag_narrow): Use new version of xg_is_single_relaxable_insn.
This commit is contained in:
Bob Wilson
parent
1c04af1399
commit
84b08ed948
@ -1,3 +1,12 @@
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2005-04-22 Bob Wilson <bob.wilson@acm.org>
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* config/tc-xtensa.c (xg_get_build_instr_size): Remove.
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(xg_is_narrow_insn, xg_expand_narrow): Remove. Merge into...
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(xg_is_single_relaxable_insn): ...here. Add "targ" and "narrow_only"
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parameters.
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(xg_assembly_relax, xg_find_narrowest_format, relaxation_requirements,
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convert_frag_narrow): Use new version of xg_is_single_relaxable_insn.
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2005-04-21 Christian Groessler <chris@groessler.org>
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* config/tc-z8k.c (md_assemble): Fix buffer overrun in operand[]
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@ -435,6 +435,8 @@ static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *);
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/* Various Other Internal Functions. */
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extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean);
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static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *);
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static void xtensa_mark_literal_pool_location (void);
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static addressT get_expanded_loop_offset (xtensa_opcode);
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static fragS *get_literal_pool_location (segT);
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@ -2984,20 +2986,23 @@ is_unique_insn_expansion (TransitionRule *r)
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}
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static int
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xg_get_build_instr_size (BuildInstr *insn)
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{
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assert (insn->typ == INSTR_INSTR);
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return xg_get_single_size (insn->opcode);
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}
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/* Check if there is exactly one relaxation for INSN that converts it to
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another instruction of equal or larger size. If so, and if TARG is
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non-null, go ahead and generate the relaxed instruction into TARG. If
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NARROW_ONLY is true, then only consider relaxations that widen a narrow
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instruction, i.e., ignore relaxations that convert to an instruction of
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equal size. In some contexts where this function is used, only
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a single widening is allowed and the NARROW_ONLY argument is used to
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exclude cases like ADDI being "widened" to an ADDMI, which may
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later be relaxed to an ADDMI/ADDI pair. */
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static bfd_boolean
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xg_is_narrow_insn (TInsn *insn)
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bfd_boolean
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xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only)
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{
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TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
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TransitionList *l;
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int num_match = 0;
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TransitionRule *match = 0;
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assert (insn->insn_type == ITYPE_INSN);
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assert (insn->opcode < table->num_opcodes);
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@ -3006,53 +3011,21 @@ xg_is_narrow_insn (TInsn *insn)
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TransitionRule *rule = l->rule;
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if (xg_instruction_matches_rule (insn, rule)
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&& is_unique_insn_expansion (rule))
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&& is_unique_insn_expansion (rule)
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&& (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0)
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<= xg_get_single_size (rule->to_instr->opcode)))
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{
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/* It only generates one instruction... */
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assert (insn->insn_type == ITYPE_INSN);
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/* ...and it is a larger instruction. */
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if (xg_get_single_size (insn->opcode)
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< xg_get_build_instr_size (rule->to_instr))
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{
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num_match++;
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if (num_match > 1)
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return FALSE;
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}
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if (match)
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return FALSE;
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match = rule;
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}
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}
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return (num_match == 1);
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}
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if (!match)
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return FALSE;
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static bfd_boolean
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xg_is_single_relaxable_insn (TInsn *insn)
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{
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TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
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TransitionList *l;
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int num_match = 0;
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assert (insn->insn_type == ITYPE_INSN);
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assert (insn->opcode < table->num_opcodes);
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for (l = table->table[insn->opcode]; l != NULL; l = l->next)
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{
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TransitionRule *rule = l->rule;
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if (xg_instruction_matches_rule (insn, rule)
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&& is_unique_insn_expansion (rule))
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{
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/* It only generates one instruction... */
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assert (insn->insn_type == ITYPE_INSN);
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/* ... and it is a larger instruction. */
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if (xg_get_single_size (insn->opcode)
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<= xg_get_build_instr_size (rule->to_instr))
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{
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num_match++;
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if (num_match > 1)
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return FALSE;
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}
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}
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}
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return (num_match == 1);
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if (targ)
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xg_build_to_insn (targ, insn, match->to_instr);
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return TRUE;
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}
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@ -3580,34 +3553,6 @@ xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps)
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return FALSE;
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}
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static bfd_boolean
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xg_expand_narrow (TInsn *targ, TInsn *insn)
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{
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TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
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TransitionList *l;
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assert (insn->insn_type == ITYPE_INSN);
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assert (insn->opcode < table->num_opcodes);
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for (l = table->table[insn->opcode]; l != NULL; l = l->next)
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{
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TransitionRule *rule = l->rule;
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if (xg_instruction_matches_rule (insn, rule)
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&& is_unique_insn_expansion (rule))
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{
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/* Is it a larger instruction? */
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if (xg_get_single_size (insn->opcode)
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<= xg_get_build_instr_size (rule->to_instr))
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{
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xg_build_to_insn (targ, insn, rule->to_instr);
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return FALSE;
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}
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}
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}
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return TRUE;
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}
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/* Relax the assembly instruction at least "min_steps".
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Return the number of steps taken. */
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@ -3644,12 +3589,8 @@ xg_assembly_relax (IStack *istack,
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current_insn = *insn;
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/* Walk through all of the single instruction expansions. */
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while (xg_is_single_relaxable_insn (¤t_insn))
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while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE))
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{
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int error_val = xg_expand_narrow (&single_target, ¤t_insn);
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assert (!error_val);
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if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset,
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stretch))
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{
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@ -6492,22 +6433,11 @@ xg_find_narrowest_format (vliw_insn *vinsn)
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/* Try the widened version. */
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if (!v_copy.slots[slot].keep_wide
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&& !v_copy.slots[slot].is_specific_opcode
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&& xg_is_narrow_insn (&v_copy.slots[slot])
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&& !xg_expand_narrow (&widened, &v_copy.slots[slot])
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&& xg_is_single_relaxable_insn (&v_copy.slots[slot],
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&widened, TRUE)
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&& opcode_fits_format_slot (widened.opcode,
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format, slot))
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{
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/* The xg_is_narrow clause requires some explanation:
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addi can be "widened" to an addmi, which is then
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expanded to an addmi/addi pair if the immediate
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requires it, but here we must have a single widen
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only.
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xg_is_narrow tells us that addi isn't really
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narrow. The widen_spec_list says that there are
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other cases. */
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v_copy.slots[slot] = widened;
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fit++;
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}
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@ -6548,7 +6478,7 @@ relaxation_requirements (vliw_insn *vinsn)
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{
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/* A narrow instruction could be widened later to help
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alignment issues. */
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if (xg_is_narrow_insn (tinsn)
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if (xg_is_single_relaxable_insn (tinsn, 0, TRUE)
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&& !tinsn->is_specific_opcode
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&& vinsn->num_slots == 1)
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{
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@ -9146,7 +9076,7 @@ convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot)
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{
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TInsn tinsn, single_target;
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xtensa_format single_fmt;
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int size, old_size, diff, error_val;
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int size, old_size, diff;
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offsetT frag_offset;
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assert (slot == 0);
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@ -9181,8 +9111,7 @@ convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot)
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tinsn_init (&single_target);
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frag_offset = fragP->fr_opcode - fragP->fr_literal;
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error_val = xg_expand_narrow (&single_target, &tinsn);
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if (error_val)
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if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE))
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{
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as_bad (_("unable to widen instruction"));
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return;
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